static int aduc702x_register_commands(struct command_context_s *cmd_ctx);
static int aduc702x_erase(struct flash_bank_s *bank, int first, int last);
static int aduc702x_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int aduc702x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
-static int aduc702x_write_single(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
-static int aduc702x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int aduc702x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
+static int aduc702x_write_single(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
+static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int aduc702x_probe(struct flash_bank_s *bank);
static int aduc702x_info(struct flash_bank_s *bank, char *buf, int buf_size);
static int aduc702x_protect_check(struct flash_bank_s *bank);
return ERROR_FLASH_OPERATION_FAILED;
}
-static int aduc702x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
aduc702x_flash_bank_t *aduc702x_info = bank->driver_priv;
target_t *target = bank->target;
};
target_write_buffer(target, aduc702x_info->write_algorithm->address,
- sizeof(aduc702x_flash_write_code), (u8*)aduc702x_flash_write_code);
+ sizeof(aduc702x_flash_write_code), (uint8_t*)aduc702x_flash_write_code);
/* memory buffer */
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
/* All-JTAG, single-access method. Very slow. Used only if there is no
* working area available. */
-static int aduc702x_write_single(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int aduc702x_write_single(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
u32 x;
- u8 b;
+ uint8_t b;
target_t *target = bank->target;
aduc702x_set_write_enable(target, 1);
return ERROR_OK;
}
-int aduc702x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+int aduc702x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
int retval;
* so in some cases may slow things down without a usleep after the first read */
static int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms)
{
- u8 v = 4;
+ uint8_t v = 4;
long long endtime = timeval_ms() + timeout_ms;
while (1) {
static int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int at91sam7_erase(struct flash_bank_s *bank, int first, int last);
static int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int at91sam7_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int at91sam7_probe(struct flash_bank_s *bank);
//static int at91sam7_auto_probe(struct flash_bank_s *bank);
static int at91sam7_erase_check(struct flash_bank_s *bank);
static u32 at91sam7_get_flash_status(target_t *target, int bank_number);
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
static u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
-static int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen);
+static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, u16 pagen);
static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
flash_driver_t at91sam7_flash =
}
/* Send one command to the AT91SAM flash controller */
-static int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen)
+static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, u16 pagen)
{
u32 fcr;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
u16 bnk, sec;
u16 arch;
u32 cidr;
- u8 banks_num = 0;
+ uint8_t banks_num = 0;
u16 num_nvmbits = 0;
u16 sectors_num = 0;
u16 pages_per_sector = 0;
u16 retval;
u32 blank;
u16 fast_check;
- u8 *buffer;
+ uint8_t *buffer;
u16 nSector;
u16 nByte;
static int at91sam7_protect_check(struct flash_bank_s *bank)
{
- u8 lock_pos, gpnvm_pos;
+ uint8_t lock_pos, gpnvm_pos;
u32 status;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
int sec;
u32 nbytes, pos;
- u8 *buffer;
- u8 erase_all;
+ uint8_t *buffer;
+ uint8_t erase_all;
if (at91sam7_info->cidr == 0)
{
{
/* allocate and clean buffer */
nbytes = (last - first + 1) * bank->sectors[first].size;
- buffer = malloc(nbytes * sizeof(u8));
+ buffer = malloc(nbytes * sizeof(uint8_t));
for (pos=0; pos<nbytes; pos++)
{
buffer[pos] = 0xFF;
return ERROR_OK;
}
-static int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int at91sam7_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
int retval;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
{
flash_bank_t *bank;
int bit;
- u8 flashcmd;
+ uint8_t flashcmd;
u32 status;
at91sam7_flash_bank_t *at91sam7_info;
int retval;
char *target_name;
/* flash auto-detection */
- u8 flash_autodetection;
+ uint8_t flash_autodetection;
/* flash geometry */
u16 pages_per_sector;
u16 num_nvmbits;
u16 num_nvmbits_on;
u16 nvmbits;
- u8 securitybit;
+ uint8_t securitybit;
/* 0: not init
* 1: fmcn for nvbits (1uS)
* 2: fmcn for flash (1.5uS) */
- u8 flashmode;
+ uint8_t flashmode;
/* main clock status */
- u8 mck_valid;
+ uint8_t mck_valid;
u32 mck_freq;
/* external clock frequency */
static int avrf_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int avrf_erase(struct flash_bank_s *bank, int first, int last);
static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int avrf_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int avrf_probe(struct flash_bank_s *bank);
static int avrf_auto_probe(struct flash_bank_s *bank);
//static int avrf_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int avrf_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-extern int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out);
+extern int avr_jtag_sendinstr(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out);
extern int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len);
-extern int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti);
-extern int mcu_write_dr(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int dr_len, int rti);
-extern int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti);
-extern int mcu_write_dr_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int dr_len, int rti);
+extern int mcu_write_ir(jtag_tap_t *tap, uint8_t *ir_in, uint8_t *ir_out, int ir_len, int rti);
+extern int mcu_write_dr(jtag_tap_t *tap, uint8_t *ir_in, uint8_t *ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u8(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u8(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out, int dr_len, int rti);
extern int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
extern int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
extern int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
return ERROR_OK;
}
-static int avr_jtagprg_writeflashpage(avr_common_t *avr, u8 *page_buf, u32 buf_size, u32 addr, u32 page_size)
+static int avr_jtagprg_writeflashpage(avr_common_t *avr, uint8_t *page_buf, u32 buf_size, u32 addr, u32 page_size)
{
u32 i, poll_value;
return ERROR_OK;
}
-static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int avrf_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
target_t *target = bank->target;
avr_common_t *avr = target->arch_info;
static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int cfi_erase(struct flash_bank_s *bank, int first, int last);
static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int cfi_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int cfi_probe(struct flash_bank_s *bank);
static int cfi_auto_probe(struct flash_bank_s *bank);
static int cfi_protect_check(struct flash_bank_s *bank);
}
-static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
+static void cfi_command(flash_bank_t *bank, uint8_t cmd, uint8_t *cmd_buf)
{
int i;
* flash banks are expected to be made of similar chips
* the query result should be the same for all
*/
-static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
+static uint8_t cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
{
target_t *target = bank->target;
- u8 data[CFI_MAX_BUS_WIDTH];
+ uint8_t data[CFI_MAX_BUS_WIDTH];
target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
* in case of a bank made of multiple chips,
* the individual values are ORed
*/
-static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
+static uint8_t cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
{
target_t *target = bank->target;
- u8 data[CFI_MAX_BUS_WIDTH];
+ uint8_t data[CFI_MAX_BUS_WIDTH];
int i;
target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
}
else
{
- u8 value = 0;
+ uint8_t value = 0;
for (i = 0; i < bank->bus_width / bank->chip_width; i++)
value |= data[bank->bus_width - 1 - i];
{
target_t *target = bank->target;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- u8 data[CFI_MAX_BUS_WIDTH * 2];
+ uint8_t data[CFI_MAX_BUS_WIDTH * 2];
if(cfi_info->x16_as_x8)
{
- u8 i;
+ uint8_t i;
for(i=0;i<2;i++)
target_read_memory(target, flash_address(bank, sector, offset+i), bank->bus_width, 1,
&data[i*bank->bus_width] );
{
target_t *target = bank->target;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
- u8 data[CFI_MAX_BUS_WIDTH * 4];
+ uint8_t data[CFI_MAX_BUS_WIDTH * 4];
if(cfi_info->x16_as_x8)
{
- u8 i;
+ uint8_t i;
for(i=0;i<4;i++)
target_read_memory(target, flash_address(bank, sector, offset+i), bank->bus_width, 1,
&data[i*bank->bus_width] );
static void cfi_intel_clear_status_register(flash_bank_t *bank)
{
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
if (target->state != TARGET_HALTED)
{
target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
-u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
+uint8_t cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
{
- u8 status;
+ uint8_t status;
while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
{
int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
{
- u8 status, oldstatus;
+ uint8_t status, oldstatus;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
oldstatus = cfi_get_u8(bank, 0, 0x0);
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
cfi_info->pri_ext = pri_ext;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
cfi_info->pri_ext = pri_ext;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
/* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
* but a different primary extended query table.
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
int i;
cfi_intel_clear_status_register(bank);
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
int i;
for (i = first; i <= last; i++)
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
int retry = 0;
int i;
}
else
{
- u8 block_status;
+ uint8_t block_status;
/* read block lock bit, to verify status */
cfi_command(bank, 0x90, command);
if((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
}
/* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
-static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
+static void cfi_add_byte(struct flash_bank_s *bank, uint8_t *word, uint8_t byte)
{
/* target_t *target = bank->target; */
/* Convert code image to target endian */
/* FIXME create general block conversion fcts in target.c?) */
-static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
+static void cfi_fix_code_endian(target_t *target, uint8_t *dest, const u32 *src, u32 count)
{
u32 i;
for (i=0; i< count; i++)
}
}
-static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
+static u32 cfi_command_val(flash_bank_t *bank, uint8_t cmd)
{
target_t *target = bank->target;
- u8 buf[CFI_MAX_BUS_WIDTH];
+ uint8_t buf[CFI_MAX_BUS_WIDTH];
cfi_command(bank, cmd, buf);
switch (bank->bus_width)
{
}
}
-static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
+static int cfi_intel_write_block(struct flash_bank_s *bank, uint8_t *buffer, u32 address, u32 count)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
0xeafffff2, /* b loop */
0xeafffffe /* done: b -2 */
};
- u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
+ uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
const u32 *target_code_src;
u32 target_code_size;
int retval = ERROR_OK;
return retval;
}
-static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
+static int cfi_spansion_write_block(struct flash_bank_s *bank, uint8_t *buffer, u32 address, u32 count)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
/* flash write code */
if (!cfi_info->write_algorithm)
{
- u8 *target_code;
+ uint8_t *target_code;
int target_code_size;
const u32 *src;
return exit_code;
}
-static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
+static int cfi_intel_write_word(struct flash_bank_s *bank, uint8_t *word, u32 address)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x40, command);
return ERROR_OK;
}
-static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
+static int cfi_intel_write_words(struct flash_bank_s *bank, uint8_t *word, u32 wordcount, u32 address)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
/* Calculate buffer size and boundary mask */
u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
return ERROR_OK;
}
-static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
+static int cfi_spansion_write_word(struct flash_bank_s *bank, uint8_t *word, u32 address)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
cfi_command(bank, 0xaa, command);
if((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
return ERROR_OK;
}
-static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
+static int cfi_spansion_write_words(struct flash_bank_s *bank, uint8_t *word, u32 wordcount, u32 address)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
/* Calculate buffer size and boundary mask */
return ERROR_OK;
}
-static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
+static int cfi_write_word(struct flash_bank_s *bank, uint8_t *word, u32 address)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
return ERROR_FLASH_OPERATION_FAILED;
}
-static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
+static int cfi_write_words(struct flash_bank_s *bank, uint8_t *word, u32 wordcount, u32 address)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
return ERROR_FLASH_OPERATION_FAILED;
}
-int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+int cfi_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u32 write_p, copy_p;
int align; /* number of unaligned bytes */
int blk_count; /* number of bus_width bytes for block copy */
- u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
+ uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
int i;
int retval;
/* copy bytes before the first write address */
for (i = 0; i < align; ++i, ++copy_p)
{
- u8 byte;
+ uint8_t byte;
if((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
{
return retval;
/* if the buffer is already finished, copy bytes after the last write address */
for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
{
- u8 byte;
+ uint8_t byte;
if((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
{
return retval;
}
for (; i < bank->bus_width; ++i, ++copy_p)
{
- u8 byte;
+ uint8_t byte;
if((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
{
return retval;
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
int num_sectors = 0;
int i;
int sector = 0;
if (bank->chip_width == 1)
{
- u8 manufacturer, device_id;
+ uint8_t manufacturer, device_id;
if((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
{
return retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
- u8 command[CFI_MAX_BUS_WIDTH];
+ uint8_t command[CFI_MAX_BUS_WIDTH];
int i;
/* check if block lock bits are supported on this device */
for (i = 0; i < bank->num_sectors; i++)
{
- u8 block_status = cfi_get_u8(bank, i, 0x2);
+ uint8_t block_status = cfi_get_u8(bank, i, 0x2);
if (block_status & 1)
bank->sectors[i].is_protected = 1;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
- u8 command[8];
+ uint8_t command[8];
int i;
cfi_command(bank, 0xaa, command);
for (i = 0; i < bank->num_sectors; i++)
{
- u8 block_status = cfi_get_u8(bank, i, 0x2);
+ uint8_t block_status = cfi_get_u8(bank, i, 0x2);
if (block_status & 1)
bank->sectors[i].is_protected = 1;
u16 alt_addr;
/* device-system interface */
- u8 vcc_min;
- u8 vcc_max;
- u8 vpp_min;
- u8 vpp_max;
- u8 word_write_timeout_typ;
- u8 buf_write_timeout_typ;
- u8 block_erase_timeout_typ;
- u8 chip_erase_timeout_typ;
- u8 word_write_timeout_max;
- u8 buf_write_timeout_max;
- u8 block_erase_timeout_max;
- u8 chip_erase_timeout_max;
-
- u8 status_poll_mask;
+ uint8_t vcc_min;
+ uint8_t vcc_max;
+ uint8_t vpp_min;
+ uint8_t vpp_max;
+ uint8_t word_write_timeout_typ;
+ uint8_t buf_write_timeout_typ;
+ uint8_t block_erase_timeout_typ;
+ uint8_t chip_erase_timeout_typ;
+ uint8_t word_write_timeout_max;
+ uint8_t buf_write_timeout_max;
+ uint8_t block_erase_timeout_max;
+ uint8_t chip_erase_timeout_max;
+
+ uint8_t status_poll_mask;
/* flash geometry */
u32 dev_size;
u16 interface_desc;
u16 max_buf_write_size;
- u8 num_erase_regions;
+ uint8_t num_erase_regions;
u32 *erase_region_info;
void *pri_ext;
typedef struct cfi_intel_pri_ext_s
{
char pri[3];
- u8 major_version;
- u8 minor_version;
+ uint8_t major_version;
+ uint8_t minor_version;
u32 feature_support;
- u8 suspend_cmd_support;
+ uint8_t suspend_cmd_support;
u16 blk_status_reg_mask;
- u8 vcc_optimal;
- u8 vpp_optimal;
- u8 num_protection_fields;
+ uint8_t vcc_optimal;
+ uint8_t vpp_optimal;
+ uint8_t num_protection_fields;
u16 prot_reg_addr;
- u8 fact_prot_reg_size;
- u8 user_prot_reg_size;
- u8 extra[0];
+ uint8_t fact_prot_reg_size;
+ uint8_t user_prot_reg_size;
+ uint8_t extra[0];
} cfi_intel_pri_ext_t;
/* Spansion primary extended query table as defined for and used by
*/
typedef struct cfi_spansion_pri_ext_s
{
- u8 pri[3];
- u8 major_version;
- u8 minor_version;
- u8 SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
- u8 EraseSuspend;
- u8 BlkProt;
- u8 TmpBlkUnprotect;
- u8 BlkProtUnprot;
- u8 SimultaneousOps;
- u8 BurstMode;
- u8 PageMode;
- u8 VppMin;
- u8 VppMax;
- u8 TopBottom;
+ uint8_t pri[3];
+ uint8_t major_version;
+ uint8_t minor_version;
+ uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
+ uint8_t EraseSuspend;
+ uint8_t BlkProt;
+ uint8_t TmpBlkUnprotect;
+ uint8_t BlkProtUnprot;
+ uint8_t SimultaneousOps;
+ uint8_t BurstMode;
+ uint8_t PageMode;
+ uint8_t VppMin;
+ uint8_t VppMax;
+ uint8_t TopBottom;
int _reversed_geometry;
u32 _unlock1;
u32 _unlock2;
*/
typedef struct cfi_atmel_pri_ext_s
{
- u8 pri[3];
- u8 major_version;
- u8 minor_version;
- u8 features;
- u8 bottom_boot;
- u8 burst_mode;
- u8 page_mode;
+ uint8_t pri[3];
+ uint8_t major_version;
+ uint8_t minor_version;
+ uint8_t features;
+ uint8_t bottom_boot;
+ uint8_t burst_mode;
+ uint8_t page_mode;
} cfi_atmel_pri_ext_t;
enum {
struct davinci_nand {
target_t *target;
- u8 chipsel; /* chipselect 0..3 == CS2..CS5 */
- u8 eccmode;
+ uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
+ uint8_t eccmode;
/* Async EMIF controller base */
u32 aemif;
/* page i/o for the relevant flavor of hardware ECC */
int (*read_page)(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size);
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
int (*write_page)(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size);
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
};
#define NANDFCR 0x60 /* flash control register */
return 0;
}
-static int davinci_command(struct nand_device_s *nand, u8 command)
+static int davinci_command(struct nand_device_s *nand, uint8_t command)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
return ERROR_OK;
}
-static int davinci_address(struct nand_device_s *nand, u8 address)
+static int davinci_address(struct nand_device_s *nand, uint8_t address)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
/* REVISIT a bit of native code should let block I/O be MUCH faster */
static int davinci_read_block_data(struct nand_device_s *nand,
- u8 *data, int data_size)
+ uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
}
static int davinci_write_block_data(struct nand_device_s *nand,
- u8 *data, int data_size)
+ uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
}
static int davinci_write_page(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
struct davinci_nand *info = nand->controller_priv;
- u8 *ooballoc = NULL;
+ uint8_t *ooballoc = NULL;
int status;
if (!nand->device)
}
static int davinci_read_page(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
struct davinci_nand *info = nand->controller_priv;
return info->read_page(nand, page, data, data_size, oob, oob_size);
}
-static void davinci_write_pagecmd(struct nand_device_s *nand, u8 cmd, u32 page)
+static void davinci_write_pagecmd(struct nand_device_s *nand, uint8_t cmd, u32 page)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
}
static int davinci_writepage_tail(struct nand_device_s *nand,
- u8 *oob, u32 oob_size)
+ uint8_t *oob, u32 oob_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
- u8 status;
+ uint8_t status;
if (oob_size)
davinci_write_block_data(nand, oob, oob_size);
* All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
*/
static int davinci_write_page_ecc1(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
unsigned oob_offset;
struct davinci_nand *info = nand->controller_priv;
ecc1 = ~ecc1;
/* save correct ECC code into oob data */
- oob[oob_offset++] = (u8)(ecc1);
- oob[oob_offset++] = (u8)(ecc1 >> 8);
- oob[oob_offset++] = (u8)(ecc1 >> 16);
+ oob[oob_offset++] = (uint8_t)(ecc1);
+ oob[oob_offset++] = (uint8_t)(ecc1 >> 8);
+ oob[oob_offset++] = (uint8_t)(ecc1 >> 16);
} while (data_size);
* manufacturer bad block markers are safe. Contrast: old "infix" style.
*/
static int davinci_write_page_ecc4(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
- static const u8 ecc512[] = {
+ static const uint8_t ecc512[] = {
0, 1, 2, 3, 4, /* 5== mfr badblock */
6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
};
- static const u8 ecc2048[] = {
+ static const uint8_t ecc2048[] = {
24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
};
- static const u8 ecc4096[] = {
+ static const uint8_t ecc4096[] = {
48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
};
struct davinci_nand *info = nand->controller_priv;
- const u8 *l;
+ const uint8_t *l;
target_t *target = info->target;
const u32 fcr_addr = info->aemif + NANDFCR;
const u32 ecc4_addr = info->aemif + NAND4BITECC;
* (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
*/
static int davinci_write_page_ecc4infix(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
do {
u32 raw_ecc[4], *p;
- u8 *l;
+ uint8_t *l;
int i;
/* start 4bit ecc on csX */
}
static int davinci_read_page_ecc4infix(struct nand_device_s *nand, u32 page,
- u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+ uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
static int ecosflash_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int ecosflash_erase(struct flash_bank_s *bank, int first, int last);
static int ecosflash_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int ecosflash_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int ecosflash_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int ecosflash_probe(struct flash_bank_s *bank);
static int ecosflash_protect_check(struct flash_bank_s *bank);
static int ecosflash_info(struct flash_bank_s *bank, char *buf, int buf_size);
}
int retval;
- retval=target_write_buffer(target, buffer, t, ((u8 *)data)+i);
+ retval=target_write_buffer(target, buffer, t, ((uint8_t *)data)+i);
if (retval != ERROR_OK)
return retval;
}
#if 0
-static void command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
+static void command(flash_bank_t *bank, uint8_t cmd, uint8_t *cmd_buf)
{
ecosflash_flash_bank_t *info = bank->driver_priv;
int i;
return ERROR_OK;
}
-static int ecosflash_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int ecosflash_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
ecosflash_flash_bank_t *info = bank->driver_priv;
struct flash_bank_s *c=bank;
static command_t *flash_cmd;
/* wafer thin wrapper for invoking the flash driver */
-static int flash_driver_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int flash_driver_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
int retval;
u32 address;
u32 pattern;
u32 count;
- u8 chunk[1024];
- u8 readback[1024];
+ uint8_t chunk[1024];
+ uint8_t readback[1024];
u32 wrote = 0;
u32 cur_size = 0;
u32 chunk_count;
static int handle_flash_write_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
u32 offset;
- u8 *buffer;
+ uint8_t *buffer;
u32 buf_cnt;
fileio_t fileio;
while (section < image->num_sections)
{
u32 buffer_size;
- u8 *buffer;
+ uint8_t *buffer;
int section_first;
int section_last;
u32 run_address = image->sections[section].base_address + section_offset;
int default_flash_mem_blank_check(struct flash_bank_s *bank)
{
target_t *target = bank->target;
- u8 buffer[1024];
+ uint8_t buffer[1024];
int buffer_size = sizeof(buffer);
int i;
u32 nBytes;
* @param count The number of bytes to write.
* @returns ERROR_OK if successful; otherwise, an error code.
*/
- int (*write)(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+ int (*write)(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
/**
* Probe to determine what kind of flash is present.
static int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int lpc2000_erase(struct flash_bank_s *bank, int first, int last);
static int lpc2000_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int lpc2000_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int lpc2000_probe(struct flash_bank_s *bank);
static int lpc2000_erase_check(struct flash_bank_s *bank);
static int lpc2000_protect_check(struct flash_bank_s *bank);
/* regrab previously allocated working_area, or allocate a new one */
if (!lpc2000_info->iap_working_area)
{
- u8 jump_gate[8];
+ uint8_t jump_gate[8];
/* make sure we have a working area */
if (target_alloc_working_area(target, 172, &lpc2000_info->iap_working_area) != ERROR_OK)
return ERROR_OK;
}
-static int lpc2000_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int lpc2000_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
target_t *target = bank->target;
}
else
{
- u8 *last_buffer = malloc(thisrun_bytes);
+ uint8_t *last_buffer = malloc(thisrun_bytes);
u32 i;
memcpy(last_buffer, buffer + bytes_written, bytes_remaining);
for (i = bytes_remaining; i < thisrun_bytes; i++)
static int lpc288x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int lpc288x_erase(struct flash_bank_s *bank, int first, int last);
static int lpc288x_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int lpc288x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int lpc288x_probe(struct flash_bank_s *bank);
static int lpc288x_erase_check(struct flash_bank_s *bank);
static int lpc288x_protect_check(struct flash_bank_s *bank);
return ERROR_OK;
}
-static int lpc288x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int lpc288x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
- u8 page_buffer[FLASH_PAGE_SIZE];
+ uint8_t page_buffer[FLASH_PAGE_SIZE];
u32 status, source_offset,dest_offset;
target_t *target = bank->target;
u32 bytes_remaining = count;
static int lpc3180_register_commands(struct command_context_s *cmd_ctx);
static int lpc3180_init(struct nand_device_s *device);
static int lpc3180_reset(struct nand_device_s *device);
-static int lpc3180_command(struct nand_device_s *device, u8 command);
-static int lpc3180_address(struct nand_device_s *device, u8 address);
+static int lpc3180_command(struct nand_device_s *device, uint8_t command);
+static int lpc3180_address(struct nand_device_s *device, uint8_t address);
static int lpc3180_write_data(struct nand_device_s *device, u16 data);
static int lpc3180_read_data(struct nand_device_s *device, void *data);
-static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
-static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
+static int lpc3180_write_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
+static int lpc3180_read_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
static int lpc3180_controller_ready(struct nand_device_s *device, int timeout);
static int lpc3180_nand_ready(struct nand_device_s *device, int timeout);
return ERROR_OK;
}
-static int lpc3180_command(struct nand_device_s *device, u8 command)
+static int lpc3180_command(struct nand_device_s *device, uint8_t command)
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
return ERROR_OK;
}
-static int lpc3180_address(struct nand_device_s *device, u8 address)
+static int lpc3180_address(struct nand_device_s *device, uint8_t address)
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
/* data = MLC_DATA, use sized access */
if (device->bus_width == 8)
{
- u8 *data8 = data;
+ uint8_t *data8 = data;
target_read_u8(target, 0x200b0000, data8);
}
else if (device->bus_width == 16)
if (device->bus_width == 8)
{
- u8 *data8 = data;
+ uint8_t *data8 = data;
*data8 = data32 & 0xff;
}
else if (device->bus_width == 16)
return ERROR_OK;
}
-static int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+static int lpc3180_write_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
int retval;
- u8 status;
+ uint8_t status;
if (target->state != TARGET_HALTED)
{
}
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
{
- u8 *page_buffer;
- u8 *oob_buffer;
+ uint8_t *page_buffer;
+ uint8_t *oob_buffer;
int quarter, num_quarters;
if (!data && oob)
return ERROR_OK;
}
-static int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+static int lpc3180_read_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
}
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
{
- u8 *page_buffer;
- u8 *oob_buffer;
+ uint8_t *page_buffer;
+ uint8_t *oob_buffer;
u32 page_bytes_done = 0;
u32 oob_bytes_done = 0;
u32 mlc_isr;
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
- u8 status = 0x0;
+ uint8_t status = 0x0;
if (target->state != TARGET_HALTED)
{
{
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
{
- u8 status = 0x0;
+ uint8_t status = 0x0;
/* Read MLC_ISR, wait for NAND flash device to become ready */
target_read_u8(target, 0x200b8048, &status);
static int s3c2440_set_gpio_to_output (mflash_gpio_num_t gpio);
-static int s3c2440_set_gpio_output_val (mflash_gpio_num_t gpio, u8 val);
+static int s3c2440_set_gpio_output_val (mflash_gpio_num_t gpio, uint8_t val);
static int pxa270_set_gpio_to_output (mflash_gpio_num_t gpio);
-static int pxa270_set_gpio_output_val (mflash_gpio_num_t gpio, u8 val);
+static int pxa270_set_gpio_output_val (mflash_gpio_num_t gpio, uint8_t val);
static command_t *mflash_cmd;
return ret;
}
-static int pxa270_set_gpio_output_val (mflash_gpio_num_t gpio, u8 val)
+static int pxa270_set_gpio_output_val (mflash_gpio_num_t gpio, uint8_t val)
{
u32 addr, value, mask;
target_t *target = mflash_bank->target;
return ret;
}
-static int s3c2440_set_gpio_output_val (mflash_gpio_num_t gpio, u8 val)
+static int s3c2440_set_gpio_output_val (mflash_gpio_num_t gpio, uint8_t val)
{
u32 data, mask, gpio_dat;
target_t *target = mflash_bank->target;
return ret;
}
-static int mg_hdrst(u8 level)
+static int mg_hdrst(uint8_t level)
{
return mflash_bank->gpio_drv->set_gpio_output_val(mflash_bank->rst_pin, level);
}
static int mg_dsk_wait(mg_io_type_wait wait, u32 time)
{
- u8 status, error;
+ uint8_t status, error;
target_t *target = mflash_bank->target;
u32 mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
duration_t duration;
return ERROR_MG_TIMEOUT;
}
-static int mg_dsk_srst(u8 on)
+static int mg_dsk_srst(uint8_t on)
{
target_t *target = mflash_bank->target;
u32 mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
- u8 value;
+ uint8_t value;
int ret;
if ((ret = target_read_u8(target, mg_task_reg + MG_REG_DRV_CTRL, &value)) != ERROR_OK)
return ret;
}
-static int mg_dsk_io_cmd(u32 sect_num, u32 cnt, u8 cmd)
+static int mg_dsk_io_cmd(u32 sect_num, u32 cnt, uint8_t cmd)
{
target_t *target = mflash_bank->target;
u32 mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
- u8 value;
+ uint8_t value;
int ret;
ret = mg_dsk_wait(mg_io_wait_rdy_noerr, MG_OEM_DISK_WAIT_TIME_NORMAL);
value = mg_io_rval_dev_drv_master | mg_io_rval_dev_lba_mode |((sect_num >> 24) & 0xf);
ret = target_write_u8(target, mg_task_reg + MG_REG_DRV_HEAD, value);
- ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_CNT, (u8)cnt);
- ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_NUM, (u8)sect_num);
- ret |= target_write_u8(target, mg_task_reg + MG_REG_CYL_LOW, (u8)(sect_num >> 8));
- ret |= target_write_u8(target, mg_task_reg + MG_REG_CYL_HIGH, (u8)(sect_num >> 16));
+ ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_CNT, (uint8_t)cnt);
+ ret |= target_write_u8(target, mg_task_reg + MG_REG_SECT_NUM, (uint8_t)sect_num);
+ ret |= target_write_u8(target, mg_task_reg + MG_REG_CYL_LOW, (uint8_t)(sect_num >> 8));
+ ret |= target_write_u8(target, mg_task_reg + MG_REG_CYL_HIGH, (uint8_t)(sect_num >> 16));
if (ret != ERROR_OK)
return ret;
mflash_bank->drv_info = malloc(sizeof(mg_drv_info_t));
target_read_memory(target, mg_buff, 2, sizeof(mg_io_type_drv_info) >> 1,
- (u8 *)&mflash_bank->drv_info->drv_id);
+ (uint8_t *)&mflash_bank->drv_info->drv_id);
if (ret != ERROR_OK)
return ret;
u32 i, address;
int ret;
target_t *target = mflash_bank->target;
- u8 *buff_ptr = buff;
+ uint8_t *buff_ptr = buff;
duration_t duration;
if ((ret = mg_dsk_io_cmd(sect_num, sect_cnt, mg_io_cmd_read)) != ERROR_OK )
static int mg_mflash_read_sects(void *buff, u32 sect_num, u32 sect_cnt)
{
u32 quotient, residue, i;
- u8 *buff_ptr = buff;
+ uint8_t *buff_ptr = buff;
int ret = ERROR_OK;
quotient = sect_cnt >> 8;
u32 i, address;
int ret;
target_t *target = mflash_bank->target;
- u8 *buff_ptr = buff;
+ uint8_t *buff_ptr = buff;
duration_t duration;
if ((ret = mg_dsk_io_cmd(sect_num, sect_cnt, cmd)) != ERROR_OK )
static int mg_mflash_write_sects(void *buff, u32 sect_num, u32 sect_cnt)
{
u32 quotient, residue, i;
- u8 *buff_ptr = buff;
+ uint8_t *buff_ptr = buff;
int ret = ERROR_OK;
quotient = sect_cnt >> 8;
return ret;
}
-static int mg_mflash_read (u32 addr, u8 *buff, u32 len)
+static int mg_mflash_read (u32 addr, uint8_t *buff, u32 len)
{
- u8 *buff_ptr = buff;
- u8 sect_buff[MG_MFLASH_SECTOR_SIZE];
+ uint8_t *buff_ptr = buff;
+ uint8_t sect_buff[MG_MFLASH_SECTOR_SIZE];
u32 cur_addr, next_sec_addr, end_addr, cnt, sect_num;
int ret = ERROR_OK;
return ret;
}
-static int mg_mflash_write(u32 addr, u8 *buff, u32 len)
+static int mg_mflash_write(u32 addr, uint8_t *buff, u32 len)
{
- u8 *buff_ptr = buff;
- u8 sect_buff[MG_MFLASH_SECTOR_SIZE];
+ uint8_t *buff_ptr = buff;
+ uint8_t sect_buff[MG_MFLASH_SECTOR_SIZE];
u32 cur_addr, next_sec_addr, end_addr, cnt, sect_num;
int ret = ERROR_OK;
static int mg_write_cmd(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
u32 address, buf_cnt, cnt, res, i;
- u8 *buffer;
+ uint8_t *buffer;
fileio_t fileio;
duration_t duration;
char *duration_text;
static int mg_dump_cmd(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
u32 address, size_written, size, cnt, res, i;
- u8 *buffer;
+ uint8_t *buffer;
fileio_t fileio;
duration_t duration;
char *duration_text;
buff[i] = i;
ret = target_write_memory(target, address, 2,
- MG_MFLASH_SECTOR_SIZE / 2, (u8 *)buff);
+ MG_MFLASH_SECTOR_SIZE / 2, (uint8_t *)buff);
if (ret != ERROR_OK)
return ret;
memset(buff, 0xff, MG_MFLASH_SECTOR_SIZE);
ret = target_read_memory(target, address, 2,
- MG_MFLASH_SECTOR_SIZE / 2, (u8 *)buff);
+ MG_MFLASH_SECTOR_SIZE / 2, (uint8_t *)buff);
if (ret != ERROR_OK)
return ret;
static int mg_storage_config(void)
{
- u8 buff[512];
+ uint8_t buff[512];
int ret;
if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
static int mg_boot_config(void)
{
- u8 buff[512];
+ uint8_t buff[512];
int ret;
if ((ret = mg_set_feature(mg_feature_id_transmode, mg_feature_val_trans_vcmd))
static int mg_set_pll(mg_pll_t *pll)
{
- u8 buff[512];
+ uint8_t buff[512];
int ret;
memset(buff, 0xff, 512);
{
char *name;
int (*set_gpio_to_output) (mflash_gpio_num_t gpio);
- int (*set_gpio_output_val) (mflash_gpio_num_t gpio, u8 val);
+ int (*set_gpio_output_val) (mflash_gpio_num_t gpio, uint8_t val);
} mflash_gpio_drv_t;
typedef struct _mg_io_type_drv_info {
static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
-//static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
+static int nand_read_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
+//static int nand_read_plain(struct nand_device_s *device, u32 address, uint8_t *data, u32 data_size);
-static int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
+static int nand_write_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
/* NAND flash controller
*/
{
u32 page = 0x0;
int i;
- u8 oob[6];
+ uint8_t oob[6];
if ((first < 0) || (first >= device->num_blocks))
first = 0;
return ERROR_OK;
}
-int nand_read_status(struct nand_device_s *device, u8 *status)
+int nand_read_status(struct nand_device_s *device, uint8_t *status)
{
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
static int nand_poll_ready(struct nand_device_s *device, int timeout)
{
- u8 status;
+ uint8_t status;
device->controller->command(device, NAND_CMD_STATUS);
do {
int nand_probe(struct nand_device_s *device)
{
- u8 manufacturer_id, device_id;
- u8 id_buff[6];
+ uint8_t manufacturer_id, device_id;
+ uint8_t id_buff[6];
int retval;
int i;
{
int i;
u32 page;
- u8 status;
+ uint8_t status;
int retval;
if (!device->device)
}
#if 0
-static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
+static int nand_read_plain(struct nand_device_s *device, u32 address, uint8_t *data, u32 data_size)
{
- u8 *page;
+ uint8_t *page;
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
return ERROR_OK;
}
-static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
+static int nand_write_plain(struct nand_device_s *device, u32 address, uint8_t *data, u32 data_size)
{
- u8 *page;
+ uint8_t *page;
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
}
#endif
-int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+int nand_write_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
u32 block;
return device->controller->write_page(device, page, data, data_size, oob, oob_size);
}
-static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+static int nand_read_page(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
return device->controller->read_page(device, page, data, data_size, oob, oob_size);
}
-int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+int nand_read_page_raw(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
u32 i;
return ERROR_OK;
}
-int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
+int nand_write_page_raw(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size)
{
u32 i;
int retval;
- u8 status;
+ uint8_t status;
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (p)
{
- u8 *page = NULL;
+ uint8_t *page = NULL;
u32 page_size = 0;
- u8 *oob = NULL;
+ uint8_t *oob = NULL;
u32 oob_size = 0;
const int *eccpos = NULL;
if (oob_format & NAND_OOB_SW_ECC)
{
u32 i, j;
- u8 ecc[3];
+ uint8_t ecc[3];
memset(oob, 0xff, oob_size);
for (i = 0, j = 0; i < page_size; i += 256) {
nand_calculate_ecc(p, page+i, ecc);
* of 10 bytes per 512-byte data block.
*/
u32 i;
- u8 *ecc = oob + oob_size - page_size/512 * 10;
+ uint8_t *ecc = oob + oob_size - page_size/512 * 10;
memset(oob, 0xff, oob_size);
for (i = 0; i < page_size; i += 512) {
nand_calculate_ecc_kw(p, page+i, ecc);
char *duration_text;
int retval;
- u8 *page = NULL;
+ uint8_t *page = NULL;
u32 page_size = 0;
- u8 *oob = NULL;
+ uint8_t *oob = NULL;
u32 oob_size = 0;
u32 address = strtoul(args[2], NULL, 0);
u32 size = strtoul(args[3], NULL, 0);
int (*register_commands)(struct command_context_s *cmd_ctx);
int (*init)(struct nand_device_s *device);
int (*reset)(struct nand_device_s *device);
- int (*command)(struct nand_device_s *device, u8 command);
- int (*address)(struct nand_device_s *device, u8 address);
+ int (*command)(struct nand_device_s *device, uint8_t command);
+ int (*address)(struct nand_device_s *device, uint8_t address);
int (*write_data)(struct nand_device_s *device, u16 data);
int (*read_data)(struct nand_device_s *device, void *data);
- int (*write_block_data)(struct nand_device_s *device, u8 *data, int size);
- int (*read_block_data)(struct nand_device_s *device, u8 *data, int size);
- int (*write_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
- int (*read_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
+ int (*write_block_data)(struct nand_device_s *device, uint8_t *data, int size);
+ int (*read_block_data)(struct nand_device_s *device, uint8_t *data, int size);
+ int (*write_page)(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
+ int (*read_page)(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
int (*controller_ready)(struct nand_device_s *device, int timeout);
int (*nand_ready)(struct nand_device_s *device, int timeout);
} nand_flash_controller_t;
/* Function prototypes */
extern nand_device_t *get_nand_device_by_num(int num);
-extern int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
-extern int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
-extern int nand_read_status(struct nand_device_s *device, u8 *status);
-extern int nand_calculate_ecc(struct nand_device_s *device, const u8 *dat, u8 *ecc_code);
-extern int nand_calculate_ecc_kw(struct nand_device_s *device, const u8 *dat, u8 *ecc_code);
+extern int nand_read_page_raw(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
+extern int nand_write_page_raw(struct nand_device_s *device, u32 page, uint8_t *data, u32 data_size, uint8_t *oob, u32 oob_size);
+extern int nand_read_status(struct nand_device_s *device, uint8_t *status);
+extern int nand_calculate_ecc(struct nand_device_s *device, const uint8_t *dat, uint8_t *ecc_code);
+extern int nand_calculate_ecc_kw(struct nand_device_s *device, const uint8_t *dat, uint8_t *ecc_code);
extern int nand_register_commands(struct command_context_s *cmd_ctx);
extern int nand_init(struct command_context_s *cmd_ctx);
/*
* Pre-calculated 256-way 1 byte column parity
*/
-static const u8 nand_ecc_precalc_table[] = {
+static const uint8_t nand_ecc_precalc_table[] = {
0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
/*
* nand_calculate_ecc - Calculate 3-byte ECC for 256-byte block
*/
-int nand_calculate_ecc(struct nand_device_s *device, const u8 *dat, u8 *ecc_code)
+int nand_calculate_ecc(struct nand_device_s *device, const uint8_t *dat, uint8_t *ecc_code)
{
- u8 idx, reg1, reg2, reg3, tmp1, tmp2;
+ uint8_t idx, reg1, reg2, reg3, tmp1, tmp2;
int i;
/* Initialize variables */
/* All bit XOR = 1 ? */
if (idx & 0x40) {
- reg3 ^= (u8) i;
- reg2 ^= ~((u8) i);
+ reg3 ^= (uint8_t) i;
+ reg2 ^= ~((uint8_t) i);
}
}
* expects the ECC to be computed backward, i.e. from the last byte down
* to the first one.
*/
-int nand_calculate_ecc_kw(struct nand_device_s *device, const u8 *data, u8 *ecc)
+int nand_calculate_ecc_kw(struct nand_device_s *device, const uint8_t *data, uint8_t *ecc)
{
unsigned int r7, r6, r5, r4, r3, r2, r1, r0;
int i;
u32 dev_size;
u16 interface_desc;
u16 max_buf_write_size;
- u8 num_erase_regions;
+ uint8_t num_erase_regions;
u32 erase_region_info[6];
- u8 status_poll_mask;
+ uint8_t status_poll_mask;
} non_cfi_t;
extern non_cfi_t non_cfi_flashes[];
static int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int ocl_erase(struct flash_bank_s *bank, int first, int last);
static int ocl_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int ocl_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int ocl_probe(struct flash_bank_s *bank);
static int ocl_erase_check(struct flash_bank_s *bank);
static int ocl_protect_check(struct flash_bank_s *bank);
return ERROR_OK;
}
-static int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int ocl_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
ocl_priv_t *ocl = bank->driver_priv;
int retval;
} \
} while (0)
-static int orion_nand_command(struct nand_device_s *device, u8 command)
+static int orion_nand_command(struct nand_device_s *device, uint8_t command)
{
orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target;
return ERROR_OK;
}
-static int orion_nand_address(struct nand_device_s *device, u8 address)
+static int orion_nand_address(struct nand_device_s *device, uint8_t address)
{
orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target;
return ERROR_OK;
}
-static int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
+static int orion_nand_slow_block_write(struct nand_device_s *device, uint8_t *data, int size)
{
while (size--)
orion_nand_write(device, *data++);
return ERROR_OK;
}
-static int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
+static int orion_nand_fast_block_write(struct nand_device_s *device, uint8_t *data, int size)
{
orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target;
int code_size = sizeof(code);
if (!hw->copy_area) {
- u8 code_buf[code_size];
+ uint8_t code_buf[code_size];
int i;
/* make sure we have a working area */
{
orion_nand_controller_t *hw;
u32 base;
- u8 ale, cle;
+ uint8_t ale, cle;
if (argc != 3) {
LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
static
struct pic32mx_devs_s {
- u8 devid;
+ uint8_t devid;
char *name;
u32 pfm_size;
} pic32mx_devs[] = {
static int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int pic32mx_erase(struct flash_bank_s *bank, int first, int last);
static int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int pic32mx_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int pic32mx_write_row(struct flash_bank_s *bank, u32 address, u32 srcaddr);
static int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word);
static int pic32mx_probe(struct flash_bank_s *bank);
#endif
}
-static int pic32mx_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int pic32mx_write_block(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
target_t *target = bank->target;
u32 buffer_size = 512;
pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
armv7m_algorithm_t armv7m_info;
- u8 pic32mx_flash_write_code[] = {
+ uint8_t pic32mx_flash_write_code[] = {
/* write: */
0xDF, 0xF8, 0x24, 0x40, /* ldr r4, PIC32MX_FLASH_CR */
0x09, 0x4D, /* ldr r5, PIC32MX_FLASH_SR */
return pic32mx_nvm_exec(bank, NVMCON_OP_ROW_PROG, 100);
}
-static int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int pic32mx_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
u32 words_remaining = (count / 4);
u32 bytes_remaining = (count & 0x00000003);
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
- u8 status;
+ uint8_t status;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
- u8 status;
+ uint8_t status;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
/* use the fact we can read/write 4 bytes in one go via a single 32bit op */
-int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_size)
+int s3c2440_read_block_data(struct nand_device_s *device, uint8_t *data, int data_size)
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
return ERROR_OK;
}
-int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_size)
+int s3c2440_write_block_data(struct nand_device_s *device, uint8_t *data, int data_size)
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
return ERROR_OK;
}
-int s3c24xx_command(struct nand_device_s *device, u8 command)
+int s3c24xx_command(struct nand_device_s *device, uint8_t command)
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
}
-int s3c24xx_address(struct nand_device_s *device, u8 address)
+int s3c24xx_address(struct nand_device_s *device, uint8_t address)
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
extern int s3c24xx_register_commands(struct command_context_s *cmd_ctx);
extern int s3c24xx_reset(struct nand_device_s *device);
-extern int s3c24xx_command(struct nand_device_s *device, u8 command);
-extern int s3c24xx_address(struct nand_device_s *device, u8 address);
+extern int s3c24xx_command(struct nand_device_s *device, uint8_t command);
+extern int s3c24xx_address(struct nand_device_s *device, uint8_t address);
extern int s3c24xx_write_data(struct nand_device_s *device, u16 data);
extern int s3c24xx_read_data(struct nand_device_s *device, void *data);
extern int s3c24xx_controller_ready(struct nand_device_s *device, int tout);
extern int s3c2440_nand_ready(struct nand_device_s *device, int timeout);
-extern int s3c2440_read_block_data(struct nand_device_s *, u8 *data, int data_size);
-extern int s3c2440_write_block_data(struct nand_device_s *, u8 *data, int data_size);
+extern int s3c2440_read_block_data(struct nand_device_s *, uint8_t *data, int data_size);
+extern int s3c2440_write_block_data(struct nand_device_s *, uint8_t *data, int data_size);
static int stellaris_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int stellaris_erase(struct flash_bank_s *bank, int first, int last);
static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int stellaris_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int stellaris_auto_probe(struct flash_bank_s *bank);
static int stellaris_probe(struct flash_bank_s *bank);
static int stellaris_protect_check(struct flash_bank_s *bank);
}
/* Send one command to the flash controller */
-static int stellaris_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
+static int stellaris_flash_command(struct flash_bank_s *bank,uint8_t cmd,u16 pagen)
{
u32 fmc;
target_t *target = bank->target;
return ERROR_OK;
}
-static u8 stellaris_write_code[] =
+static uint8_t stellaris_write_code[] =
{
/*
Call with :
0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
};
-static int stellaris_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 wcount)
+static int stellaris_write_block(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 wcount)
{
target_t *target = bank->target;
u32 buffer_size = 8192;
return retval;
}
-static int stellaris_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int stellaris_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
target_t *target = bank->target;
if (bytes_remaining)
{
- u8 last_word[4] = {0xff, 0xff, 0xff, 0xff};
+ uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff};
int i = 0;
while(bytes_remaining > 0)
/* main clock status */
u32 rcc;
- u8 mck_valid;
+ uint8_t mck_valid;
u32 mck_freq;
} stellaris_flash_bank_t;
static int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int stm32x_erase(struct flash_bank_s *bank, int first, int last);
static int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int stm32x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int stm32x_probe(struct flash_bank_s *bank);
static int stm32x_auto_probe(struct flash_bank_s *bank);
//static int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
return stm32x_write_options(bank);
}
-static int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int stm32x_write_block(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
target_t *target = bank->target;
armv7m_algorithm_t armv7m_info;
int retval = ERROR_OK;
- u8 stm32x_flash_write_code[] = {
+ uint8_t stm32x_flash_write_code[] = {
/* write: */
0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
return retval;
}
-static int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int stm32x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
target_t *target = bank->target;
u32 words_remaining = (count / 2);
u32 bytes_remaining = (count & 0x00000001);
u32 address = bank->base + offset;
u32 bytes_written = 0;
- u8 status;
+ uint8_t status;
int retval;
if (bank->target->state != TARGET_HALTED)
target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
- if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
+ if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
command_print(cmd_ctx, "Option Byte Complement Error");
- if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
+ if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
command_print(cmd_ctx, "Readout Protection On");
else
command_print(cmd_ctx, "Readout Protection Off");
- if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
+ if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
command_print(cmd_ctx, "Software Watchdog");
else
command_print(cmd_ctx, "Hardware Watchdog");
- if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
+ if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
command_print(cmd_ctx, "Stop: No reset generated");
else
command_print(cmd_ctx, "Stop: Reset generated");
- if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
+ if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
command_print(cmd_ctx, "Standby: No reset generated");
else
command_print(cmd_ctx, "Standby: Reset generated");
static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int str7x_erase(struct flash_bank_s *bank, int first, int last);
static int str7x_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int str7x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int str7x_probe(struct flash_bank_s *bank);
//static int str7x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int str7x_protect_check(struct flash_bank_s *bank);
return ERROR_OK;
}
-static int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int str7x_write_block(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
str7x_flash_bank_t *str7x_info = bank->driver_priv;
target_t *target = bank->target;
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
- target_write_buffer(target, str7x_info->write_algorithm->address, 20 * 4, (u8*)str7x_flash_write_code);
+ target_write_buffer(target, str7x_info->write_algorithm->address, 20 * 4, (uint8_t*)str7x_flash_write_code);
/* memory buffer */
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
return retval;
}
-static int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int str7x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
target_t *target = bank->target;
str7x_flash_bank_t *str7x_info = bank->driver_priv;
if (bytes_remaining)
{
- u8 last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+ uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
int i = 0;
while(bytes_remaining > 0)
static int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int str9x_erase(struct flash_bank_s *bank, int first, int last);
static int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int str9x_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int str9x_probe(struct flash_bank_s *bank);
//static int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int str9x_protect_check(struct flash_bank_s *bank);
target_t *target = bank->target;
int i;
u32 adr;
- u8 status;
- u8 erase_cmd;
+ uint8_t status;
+ uint8_t erase_cmd;
if (bank->target->state != TARGET_HALTED)
{
target_t *target = bank->target;
int i;
u32 adr;
- u8 status;
+ uint8_t status;
if (bank->target->state != TARGET_HALTED)
{
}
static int str9x_write_block(struct flash_bank_s *bank,
- u8 *buffer, u32 offset, u32 count)
+ uint8_t *buffer, u32 offset, u32 count)
{
str9x_flash_bank_t *str9x_info = bank->driver_priv;
target_t *target = bank->target;
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
- target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (u8*)str9x_flash_write_code);
+ target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (uint8_t*)str9x_flash_write_code);
/* memory buffer */
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
}
static int str9x_write(struct flash_bank_s *bank,
- u8 *buffer, u32 offset, u32 count)
+ uint8_t *buffer, u32 offset, u32 count)
{
target_t *target = bank->target;
u32 words_remaining = (count / 2);
u32 bytes_remaining = (count & 0x00000001);
u32 address = bank->base + offset;
u32 bytes_written = 0;
- u8 status;
+ uint8_t status;
int retval;
u32 check_address = offset;
u32 bank_adr;
if (bytes_remaining)
{
- u8 last_halfword[2] = {0xff, 0xff};
+ uint8_t last_halfword[2] = {0xff, 0xff};
int i = 0;
while(bytes_remaining > 0)
static int str9xpec_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int str9xpec_erase(struct flash_bank_s *bank, int first, int last);
static int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int str9xpec_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count);
static int str9xpec_probe(struct flash_bank_s *bank);
static int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int str9xpec_protect_check(struct flash_bank_s *bank);
static int str9xpec_info(struct flash_bank_s *bank, char *buf, int buf_size);
static int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last);
-static int str9xpec_set_address(struct flash_bank_s *bank, u8 sector);
+static int str9xpec_set_address(struct flash_bank_s *bank, uint8_t sector);
static int str9xpec_write_options(struct flash_bank_s *bank);
static int str9xpec_handle_flash_options_cmap_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
return ERROR_OK;
}
-static u8 str9xpec_isc_status(jtag_tap_t *tap)
+static uint8_t str9xpec_isc_status(jtag_tap_t *tap)
{
scan_field_t field;
- u8 status;
+ uint8_t status;
if (str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE) != ERROR_OK)
return ISC_STATUS_ERROR;
static int str9xpec_isc_enable(struct flash_bank_s *bank)
{
- u8 status;
+ uint8_t status;
jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
static int str9xpec_isc_disable(struct flash_bank_s *bank)
{
- u8 status;
+ uint8_t status;
jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
static int str9xpec_read_config(struct flash_bank_s *bank)
{
scan_field_t field;
- u8 status;
+ uint8_t status;
jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
static int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
{
scan_field_t field;
- u8 status;
+ uint8_t status;
jtag_tap_t *tap;
int i;
- u8 *buffer = NULL;
+ uint8_t *buffer = NULL;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
static int str9xpec_protect_check(struct flash_bank_s *bank)
{
- u8 status;
+ uint8_t status;
int i;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
static int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
{
scan_field_t field;
- u8 status;
+ uint8_t status;
jtag_tap_t *tap;
int i;
- u8 *buffer = NULL;
+ uint8_t *buffer = NULL;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
static int str9xpec_lock_device(struct flash_bank_s *bank)
{
scan_field_t field;
- u8 status;
+ uint8_t status;
jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = NULL;
static int str9xpec_unlock_device(struct flash_bank_s *bank)
{
- u8 status;
+ uint8_t status;
status = str9xpec_erase_area(bank, 0, 255);
static int str9xpec_protect(struct flash_bank_s *bank, int set, int first, int last)
{
- u8 status;
+ uint8_t status;
int i;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
return ERROR_OK;
}
-static int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
+static int str9xpec_set_address(struct flash_bank_s *bank, uint8_t sector)
{
jtag_tap_t *tap;
scan_field_t field;
return ERROR_OK;
}
-static int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int str9xpec_write(struct flash_bank_s *bank, uint8_t *buffer, u32 offset, u32 count)
{
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
u32 dwords_remaining = (count / 8);
u32 bytes_remaining = (count & 0x00000007);
u32 bytes_written = 0;
- u8 status;
+ uint8_t status;
u32 check_address = offset;
jtag_tap_t *tap;
scan_field_t field;
- u8 *scanbuf;
+ uint8_t *scanbuf;
int i;
int first_sector = 0;
int last_sector = 0;
if (bytes_remaining)
{
- u8 last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+ uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
int i = 0;
while(bytes_remaining > 0)
{
flash_bank_t *bank;
scan_field_t field;
- u8 *buffer = NULL;
+ uint8_t *buffer = NULL;
jtag_tap_t *tap;
u32 idcode;
str9xpec_flash_controller_t *str9xpec_info = NULL;
static int str9xpec_handle_flash_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
flash_bank_t *bank;
- u8 status;
+ uint8_t status;
str9xpec_flash_controller_t *str9xpec_info = NULL;
if (argc < 1)
static int str9xpec_write_options(struct flash_bank_s *bank)
{
scan_field_t field;
- u8 status;
+ uint8_t status;
jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = NULL;
static int str9xpec_handle_flash_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
flash_bank_t *bank;
- u8 status;
+ uint8_t status;
if (argc < 1)
{
static int str9xpec_handle_flash_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- u8 status;
+ uint8_t status;
flash_bank_t *bank;
if (argc < 1)
static int str9xpec_handle_flash_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- u8 status;
+ uint8_t status;
flash_bank_t *bank;
if (argc < 1)
u32 *sector_bits;
int chain_pos;
int isc_enable;
- u8 options[8];
+ uint8_t options[8];
} str9xpec_flash_controller_t;
enum str9xpec_status_codes
static int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int tms470_erase(struct flash_bank_s *bank, int first, int last);
static int tms470_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count);
+static int tms470_write(struct flash_bank_s *bank, uint8_t * buffer, u32 offset, u32 count);
static int tms470_probe(struct flash_bank_s *bank);
static int tms470_auto_probe(struct flash_bank_s *bank);
static int tms470_erase_check(struct flash_bank_s *bank);
/* ---------------------------------------------------------------------- */
-static int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count)
+static int tms470_write(struct flash_bank_s *bank, uint8_t * buffer, u32 offset, u32 count)
{
target_t *target = bank->target;
u32 glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
tms470_flash_bank_t *tms470_info = bank->driver_priv;
int sector, result = ERROR_OK;
u32 fmmac2, fmbac2, glbctrl, orig_fmregopt;
- static u8 buffer[64 * 1024];
+ static uint8_t buffer[64 * 1024];
if (target->state != TARGET_HALTED)
{
Code Review / openocd.git / commitdiff