set _DAP_TAPID 0x5ba00477
}
-jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+set _CPUS 8
-target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1
-
-set _CPU_BASE 0x81000000
-set _CPU_STRIDE 0x100000
-set _CPU_DBGOFF 0x10000
-set _CPU_CTIOFF 0x20000
-
-set _TARGETS {}
-for {set i 0} {$i < 8} {incr i} {
- set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
- cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \
- -baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
- target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
- -cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
- {*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }]
- lappend _TARGETS $_CHIPNAME.cpu$i
-}
-
-target smp {*}$_TARGETS
-
-# Service processor
-target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
-
-# Normally you will not need to call this, but if you are using the hard-coded
-# Reset Configuration Word (RCW) you will need to call this manually. The CPU's
-# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
-# instructions. This will cause the CPU to almost immediately execute an
-# illegal instruction.
-#
-# This code is idempotent; releasing a released CPU has no effect, although it
-# will halt/resume the service processor.
-add_help_text release_cpu "Release a cpu which is held off"
-proc release_cpu {cpu} {
- set RST_BRRL 0x1e60060
-
- set old [target current]
- targets $::_CHIPNAME.sp
- set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
- if {$not_halted} {
- halt
- }
-
- # Release the cpu; it will start executing something bogus
- mem2array regs 32 $RST_BRRL 1
- mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
-
- if {$not_halted} {
- resume
- }
- targets $old
-}
-
-targets $_CHIPNAME.cpu0
+source [find target/lsch3_common.cfg]
# Seems to work OK in testing
adapter speed 10000
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This contains common configuration for NXP Layerscape chassis generation 3
+
+if { ![info exists _CPUS] } {
+ error "_CPUS must be set to the number of cores"
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1
+
+set _CPU_BASE 0x81000000
+set _CPU_STRIDE 0x100000
+set _CPU_DBGOFF 0x10000
+set _CPU_CTIOFF 0x20000
+
+set _TARGETS {}
+for {set i 0} {$i < $_CPUS} {incr i} {
+ set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
+ cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \
+ -baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
+ target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
+ -cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
+ {*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }]
+ lappend _TARGETS $_CHIPNAME.cpu$i
+}
+
+target smp {*}$_TARGETS
+
+# Service processor
+target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
+
+# Normally you will not need to call this, but if you are using the hard-coded
+# Reset Configuration Word (RCW) you will need to call this manually. The CPU's
+# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
+# instructions. This will cause the CPU to almost immediately execute an
+# illegal instruction.
+#
+# This code is idempotent; releasing a released CPU has no effect, although it
+# will halt/resume the service processor.
+add_help_text release_cpu "Release a cpu which is held off"
+proc release_cpu {cpu} {
+ set RST_BRRL 0x1e60060
+
+ set old [target current]
+ targets $::_CHIPNAME.sp
+ set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
+ if {$not_halted} {
+ halt
+ }
+
+ # Release the cpu; it will start executing something bogus
+ mem2array regs 32 $RST_BRRL 1
+ mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
+
+ if {$not_halted} {
+ resume
+ }
+ targets $old
+}
+
+targets $_CHIPNAME.cpu0