ARM: misc generic cleanup
authorDavid Brownell <dbrownell@users.sourceforge.net>
Sat, 5 Dec 2009 04:14:46 +0000 (20:14 -0800)
committerDavid Brownell <dbrownell@users.sourceforge.net>
Sat, 5 Dec 2009 04:14:46 +0000 (20:14 -0800)
Remove an undesirable use of the CPSR symbol ... it needs to vanish.
Flag mode-to-number stuff as obsolete; say why ... should also vanish.

Get rid of no-longer-used mode and state typedefs.

Comment a few of the implicit ties to "classic ARM".

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
src/target/arm_semihosting.c
src/target/armv4_5.h
src/target/etm.h
src/target/xscale.h

index d71fbaef02bd0544f6ad0cceec5021604507ec1d..39625f61bcaccc5f7726358112021d749c0af7af 100644 (file)
@@ -379,15 +379,22 @@ static int do_semihosting(struct target *target)
        }
 
        /* resume execution to the original mode */
+
+       /* return value in R0 */
        buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
        armv4_5->core_cache->reg_list[0].dirty = 1;
+
+       /* LR --> PC */
        buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
        armv4_5->core_cache->reg_list[15].dirty = 1;
-       buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
-       armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
+
+       /* saved PSR --> current PSR */
+       buf_set_u32(armv4_5->cpsr->value, 0, 32, spsr);
+       armv4_5->cpsr->dirty = 1;
        armv4_5->core_mode = spsr & 0x1f;
        if (spsr & 0x20)
                armv4_5->core_state = ARM_STATE_THUMB;
+
        return target_resume(target, 1, 0, 0, 0);
 }
 
index 6a082a57dd36f73718723dba7ee247a65c088414..b56a1f16eb2d57ef310ee55d8f03a365b8af3fde 100644 (file)
 #include <helper/command.h>
 
 
-typedef enum arm_mode
-{
+/* These numbers match the five low bits of the *PSR registers on
+ * "classic ARM" processors, which build on the ARMv4 processor
+ * modes and register set.
+ */
+enum arm_mode {
        ARM_MODE_USR = 16,
        ARM_MODE_FIQ = 17,
        ARM_MODE_IRQ = 18,
@@ -41,24 +44,29 @@ typedef enum arm_mode
        ARM_MODE_UND = 27,
        ARM_MODE_SYS = 31,
        ARM_MODE_ANY = -1
-} arm_mode_t;
+};
 
 const char *arm_mode_name(unsigned psr_mode);
 bool is_arm_mode(unsigned psr_mode);
 
-int arm_mode_to_number(enum arm_mode mode);
-enum arm_mode armv4_5_number_to_mode(int number);
-
-typedef enum arm_state
-{
+/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
+enum arm_state {
        ARM_STATE_ARM,
        ARM_STATE_THUMB,
        ARM_STATE_JAZELLE,
        ARM_STATE_THUMB_EE,
-} arm_state_t;
+};
 
 extern const char *arm_state_strings[];
 
+/* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
+ * index into the armv4_5_core_reg_map array.  Its remaining users are
+ * remnants which could as easily walk * the register cache directly as
+ * use the expensive ARMV4_5_CORE_REG_MODE() macro.
+ */
+int arm_mode_to_number(enum arm_mode mode);
+enum arm_mode armv4_5_number_to_mode(int number);
+
 extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
index 92df0bf318ee3eec7851bf4d22026517f1c9042e..5aea65714134648d860e0f15daac1d012dfa90ae 100644 (file)
@@ -164,7 +164,7 @@ struct etm_context
        uint32_t trace_depth;           /* number of cycles to be analyzed, 0 if no data available */
        etm_portmode_t portmode;        /* normal, multiplexed or demultiplexed */
        etmv1_tracemode_t tracemode;    /* type of info trace contains */
-       int /*arm_state_t*/ core_state; /* current core state */
+       int /*arm_state*/ core_state;   /* current core state */
        struct image *image;            /* source for target opcodes */
        uint32_t pipe_index;            /* current trace cycle */
        uint32_t data_index;            /* cycle holding next data packet */
index 2bb2ba5ea14dee84dd66456bdc7ad747511c4543..43edeecd0cacd45afa00e35af916f34befa99a83 100644 (file)
@@ -79,7 +79,7 @@ struct xscale_trace
        int buffer_fill;                                /* maximum number of trace runs to read (-1 for wrap-around) */
        int pc_ok;
        uint32_t current_pc;
-       arm_state_t core_state;         /* current core state (ARM, Thumb, Jazelle) */
+       enum arm_state core_state;      /* current core state (ARM, Thumb) */
 };
 
 struct xscale_common

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