- u32 fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
- target_t *target = bank->target;
- tms470_flash_bank_t * tms470_info = bank->driver_priv;
- int result = ERROR_OK;
-
- /*
- * Select the desired bank to be programmed by writing BANK[2:0] of
- * FMMAC2.
- */
- target_read_u32( target, 0xFFE8BC04, &fmmac2 );
- fmmac2 &= ~0x0007;
- fmmac2 |= (tms470_info->ordinal & 7);
- target_write_u32( target, 0xFFE8BC04, fmmac2 );
- DEBUG( "set fmmac2=0x%04x", fmmac2 );
-
- /*
- * Disable level 1 sector protection by setting bit 15 of FMMAC1.
- */
- target_read_u32( target, 0xFFE8BC00, &fmmac1 );
- fmmac1 |= 0x8000;
- target_write_u32( target, 0xFFE8BC00, fmmac1 );
- DEBUG( "set fmmac1=0x%04x", fmmac1 );
-
- /*
- * FMTCREG=0x2fc0;
- */
- target_write_u32( target, 0xFFE8BC10, 0x2fc0 );
- DEBUG( "set fmtcreg=0x2fc0" );
-
- /*
- * MAXPP=50
- */
- target_write_u32( target, 0xFFE8A07C, 50 );
- DEBUG( "set fmmaxpp=50" );
-
- /*
- * MAXCP=0xf000+2000
- */
- target_write_u32( target, 0xFFE8A084, 0xf000+2000 );
- DEBUG( "set fmmaxcp=0x%04x", 0xf000+2000 );
-
- /*
- * configure VHV
- */
- target_read_u32( target, 0xFFE8A080, &fmmaxep );
- if (fmmaxep == 0xf000)
- {
- fmmaxep = 0xf000+4095;
- target_write_u32( target, 0xFFE8A80C, 0x9964 );
- DEBUG( "set fmptr3=0x9964" );
- }
- else
- {
- fmmaxep = 0xa000+4095;
- target_write_u32( target, 0xFFE8A80C, 0x9b64 );
- DEBUG( "set fmptr3=0x9b64" );
- }
- target_write_u32( target, 0xFFE8A080, fmmaxep );
- DEBUG( "set fmmaxep=0x%04x", fmmaxep );
-
- /*
- * FMPTR4=0xa000
- */
- target_write_u32( target, 0xFFE8A810, 0xa000 );
- DEBUG( "set fmptr4=0xa000" );
-
- /*
- * FMPESETUP, delay parameter selected based on clock frequency.
- *
- * According to the TI App Note SPNU257 and flashing code, delay is
- * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
- * clock is usually derived from the ZPLL module, and selected by
- * the plldis global.
- */
- target_read_u32( target, 0xFFFFFFDC, &glbctrl );
- sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8 ) * oscMHz / (1 + (glbctrl & 7));
- delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
- target_write_u32( target, 0xFFE8A018, (delay<<4)|(delay<<8) );
- DEBUG( "set fmpsetup=0x%04x", (delay<<4)|(delay<<8) );
-
- /*
- * FMPVEVACCESS, based on delay.
- */
- k = delay|(delay<<8);
- target_write_u32( target, 0xFFE8A05C, k );
- DEBUG( "set fmpvevaccess=0x%04x", k );
-
- /*
- * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
- */
- k <<= 1;
- target_write_u32( target, 0xFFE8A034, k );
- DEBUG( "set fmpchold=0x%04x", k );
- target_write_u32( target, 0xFFE8A040, k );
- DEBUG( "set fmpvevhold=0x%04x", k );
- target_write_u32( target, 0xFFE8A024, k );
- DEBUG( "set fmpvevsetup=0x%04x", k );
-
- /*
- * FMCVACCESS, based on delay.
- */
- k = delay*16;
- target_write_u32( target, 0xFFE8A060, k );
- DEBUG( "set fmcvaccess=0x%04x", k );
-
- /*
- * FMCSETUP, based on delay.
- */
- k = 0x3000 | delay*20;
- target_write_u32( target, 0xFFE8A020, k );
- DEBUG( "set fmcsetup=0x%04x", k );
-
- /*
- * FMEHOLD, based on delay.
- */
- k = (delay*20) << 2;
- target_write_u32( target, 0xFFE8A038, k );
- DEBUG( "set fmehold=0x%04x", k );
-
- /*
- * PWIDTH, CWIDTH, EWIDTH, based on delay.
- */
- target_write_u32( target, 0xFFE8A050, delay*8 );
- DEBUG( "set fmpwidth=0x%04x", delay*8 );
- target_write_u32( target, 0xFFE8A058, delay*1000 );
- DEBUG( "set fmcwidth=0x%04x", delay*1000 );
- target_write_u32( target, 0xFFE8A054, delay*5400 );
- DEBUG( "set fmewidth=0x%04x", delay*5400 );
-
- return result;
+ u32 fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
+ target_t *target = bank->target;
+ tms470_flash_bank_t *tms470_info = bank->driver_priv;
+ int result = ERROR_OK;
+
+ /*
+ * Select the desired bank to be programmed by writing BANK[2:0] of
+ * FMMAC2.
+ */
+ target_read_u32(target, 0xFFE8BC04, &fmmac2);
+ fmmac2 &= ~0x0007;
+ fmmac2 |= (tms470_info->ordinal & 7);
+ target_write_u32(target, 0xFFE8BC04, fmmac2);
+ DEBUG("set fmmac2=0x%04x", fmmac2);
+
+ /*
+ * Disable level 1 sector protection by setting bit 15 of FMMAC1.
+ */
+ target_read_u32(target, 0xFFE8BC00, &fmmac1);
+ fmmac1 |= 0x8000;
+ target_write_u32(target, 0xFFE8BC00, fmmac1);
+ DEBUG("set fmmac1=0x%04x", fmmac1);
+
+ /*
+ * FMTCREG=0x2fc0;
+ */
+ target_write_u32(target, 0xFFE8BC10, 0x2fc0);
+ DEBUG("set fmtcreg=0x2fc0");
+
+ /*
+ * MAXPP=50
+ */
+ target_write_u32(target, 0xFFE8A07C, 50);
+ DEBUG("set fmmaxpp=50");
+
+ /*
+ * MAXCP=0xf000+2000
+ */
+ target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
+ DEBUG("set fmmaxcp=0x%04x", 0xf000 + 2000);
+
+ /*
+ * configure VHV
+ */
+ target_read_u32(target, 0xFFE8A080, &fmmaxep);
+ if (fmmaxep == 0xf000)
+ {
+ fmmaxep = 0xf000 + 4095;
+ target_write_u32(target, 0xFFE8A80C, 0x9964);
+ DEBUG("set fmptr3=0x9964");
+ }
+ else
+ {
+ fmmaxep = 0xa000 + 4095;
+ target_write_u32(target, 0xFFE8A80C, 0x9b64);
+ DEBUG("set fmptr3=0x9b64");
+ }
+ target_write_u32(target, 0xFFE8A080, fmmaxep);
+ DEBUG("set fmmaxep=0x%04x", fmmaxep);
+
+ /*
+ * FMPTR4=0xa000
+ */
+ target_write_u32(target, 0xFFE8A810, 0xa000);
+ DEBUG("set fmptr4=0xa000");
+
+ /*
+ * FMPESETUP, delay parameter selected based on clock frequency.
+ *
+ * According to the TI App Note SPNU257 and flashing code, delay is
+ * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
+ * clock is usually derived from the ZPLL module, and selected by
+ * the plldis global.
+ */
+ target_read_u32(target, 0xFFFFFFDC, &glbctrl);
+ sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
+ delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
+ target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
+ DEBUG("set fmpsetup=0x%04x", (delay << 4) | (delay << 8));
+
+ /*
+ * FMPVEVACCESS, based on delay.
+ */
+ k = delay | (delay << 8);
+ target_write_u32(target, 0xFFE8A05C, k);
+ DEBUG("set fmpvevaccess=0x%04x", k);
+
+ /*
+ * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
+ */
+ k <<= 1;
+ target_write_u32(target, 0xFFE8A034, k);
+ DEBUG("set fmpchold=0x%04x", k);
+ target_write_u32(target, 0xFFE8A040, k);
+ DEBUG("set fmpvevhold=0x%04x", k);
+ target_write_u32(target, 0xFFE8A024, k);
+ DEBUG("set fmpvevsetup=0x%04x", k);
+
+ /*
+ * FMCVACCESS, based on delay.
+ */
+ k = delay * 16;
+ target_write_u32(target, 0xFFE8A060, k);
+ DEBUG("set fmcvaccess=0x%04x", k);
+
+ /*
+ * FMCSETUP, based on delay.
+ */
+ k = 0x3000 | delay * 20;
+ target_write_u32(target, 0xFFE8A020, k);
+ DEBUG("set fmcsetup=0x%04x", k);
+
+ /*
+ * FMEHOLD, based on delay.
+ */
+ k = (delay * 20) << 2;
+ target_write_u32(target, 0xFFE8A038, k);
+ DEBUG("set fmehold=0x%04x", k);
+
+ /*
+ * PWIDTH, CWIDTH, EWIDTH, based on delay.
+ */
+ target_write_u32(target, 0xFFE8A050, delay * 8);
+ DEBUG("set fmpwidth=0x%04x", delay * 8);
+ target_write_u32(target, 0xFFE8A058, delay * 1000);
+ DEBUG("set fmcwidth=0x%04x", delay * 1000);
+ target_write_u32(target, 0xFFE8A054, delay * 5400);
+ DEBUG("set fmewidth=0x%04x", delay * 5400);
+
+ return result;