Each driver is almost self-contained, with no cross dependency.
Changing symbol names in one drive does not impact the other.
Change-Id: Ic09f844f922a35cf0a9dc23fcd61d035b38308b3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6299
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
#include "imp.h"
#include "arm_io.h"
-#define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
-#define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
-#define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
-#define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
-#define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
-#define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
-#define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
+#define AT91C_PIOX_SODR (0x30) /**< Offset to PIO SODR. */
+#define AT91C_PIOX_CODR (0x34) /**< Offset to PIO CODR. */
+#define AT91C_PIOX_PDSR (0x3C) /**< Offset to PIO PDSR. */
+#define AT91C_ECCX_CR (0x00) /**< Offset to ECC CR. */
+#define AT91C_ECCX_SR (0x08) /**< Offset to ECC SR. */
+#define AT91C_ECCX_PR (0x0C) /**< Offset to ECC PR. */
+#define AT91C_ECCX_NPR (0x10) /**< Offset to ECC NPR. */
/**
* Representation of a pin on an AT91SAM9 chip.
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- return target_write_u32(target, info->ce.pioc + AT91C_PIOx_CODR, 1 << info->ce.num);
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOX_CODR, 1 << info->ce.num);
}
/**
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOX_SODR, 1 << info->ce.num);
}
/**
return 0;
do {
- target_read_u32(target, info->busy.pioc + AT91C_PIOx_PDSR, &status);
+ target_read_u32(target, info->busy.pioc + AT91C_PIOX_PDSR, &status);
if (status & (1 << info->busy.num))
return 1;
}
/* reset ECC parity registers */
- return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
+ return target_write_u32(target, info->ecc + AT91C_ECCX_CR, 1);
}
/**
oob_data = at91sam9_oob_init(nand, oob, &oob_size);
retval = nand_read_data_page(nand, oob_data, oob_size);
if (ERROR_OK == retval && data) {
- target_read_u32(target, info->ecc + AT91C_ECCx_SR, &status);
+ target_read_u32(target, info->ecc + AT91C_ECCX_SR, &status);
if (status & 1) {
LOG_ERROR("Error detected!");
if (status & 4)
uint32_t parity;
target_read_u32(target,
- info->ecc + AT91C_ECCx_PR,
+ info->ecc + AT91C_ECCX_PR,
&parity);
uint32_t word = (parity & 0x0000FFF0) >> 4;
uint32_t bit = parity & 0x0F;
if (!oob) {
/* no OOB given, so read in the ECC parity from the ECC controller */
- target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
- target_read_u32(target, info->ecc + AT91C_ECCx_NPR, &nparity);
+ target_read_u32(target, info->ecc + AT91C_ECCX_PR, &parity);
+ target_read_u32(target, info->ecc + AT91C_ECCX_NPR, &nparity);
oob_data[0] = (uint8_t) parity;
oob_data[1] = (uint8_t) (parity >> 8);
"1000 and 20000 kHz, was %i",
lpc32xx_info->osc_freq);
- lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
+ lpc32xx_info->selected_controller = LPC32XX_NO_CONTROLLER;
lpc32xx_info->sw_write_protection = 0;
lpc32xx_info->sw_wp_lower_bound = 0x0;
lpc32xx_info->sw_wp_upper_bound = 0x0;
}
/* select MLC controller if none is currently selected */
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_DEBUG("no LPC32xx NAND flash controller selected, "
"using default 'slc'");
- lpc32xx_info->selected_controller = LPC32xx_SLC_CONTROLLER;
+ lpc32xx_info->selected_controller = LPC32XX_SLC_CONTROLLER;
}
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint32_t mlc_icr_value = 0x0;
float cycle;
int twp, twh, trp, treh, trhz, trbwb, tcea;
retval = lpc32xx_reset(nand);
if (ERROR_OK != retval)
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
float cycle;
int r_setup, r_hold, r_width, r_rdy;
int w_setup, w_hold, w_width, w_rdy;
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = 0xff (reset controller and NAND device) */
retval = target_write_u32(target, 0x200b8000, 0xff);
if (ERROR_OK != retval) {
"after reset");
return ERROR_NAND_OPERATION_TIMEOUT;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
retval = target_write_u32(target, 0x20020010, 0x6);
if (ERROR_OK != retval) {
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = command */
retval = target_write_u32(target, 0x200b8000, command);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CMD = command */
retval = target_write_u32(target, 0x20020008, command);
if (ERROR_OK != retval) {
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_ADDR = address */
retval = target_write_u32(target, 0x200b8004, address);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_ADDR = address */
retval = target_write_u32(target, 0x20020004, address);
if (ERROR_OK != retval) {
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_DATA = data */
retval = target_write_u32(target, 0x200b0000, data);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_DATA = data */
retval = target_write_u32(target, 0x20020000, data);
if (ERROR_OK != retval) {
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* data = MLC_DATA, use sized access */
if (nand->bus_width == 8) {
uint8_t *data8 = data;
LOG_ERROR("could not read MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t data32;
/* data = SLC_DATA, must use 32-bit access */
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (!data && oob) {
LOG_ERROR("LPC32xx MLC controller can't write "
"OOB data only");
retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
oob, oob_size);
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;
if (!data && oob) {
/*
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (data_size > (uint32_t)nand->page_size) {
LOG_ERROR("data size exceeds page size");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
oob, oob_size);
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;
retval = target_alloc_working_area(target,
LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
do {
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status;
/* Read MLC_ISR, wait for controller to become ready */
timeout);
return 1;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status;
/* Read SLC_STAT and check READY bit */
LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
do {
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status = 0x0;
/* Read MLC_ISR, wait for NAND flash device to
timeout);
return 1;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status = 0x0;
/* Read SLC_STAT and check READY bit */
if (CMD_ARGC >= 2) {
if (strcmp(CMD_ARGV[1], "mlc") == 0) {
lpc32xx_info->selected_controller =
- LPC32xx_MLC_CONTROLLER;
+ LPC32XX_MLC_CONTROLLER;
} else if (strcmp(CMD_ARGV[1], "slc") == 0) {
lpc32xx_info->selected_controller =
- LPC32xx_SLC_CONTROLLER;
+ LPC32XX_SLC_CONTROLLER;
} else
return ERROR_COMMAND_SYNTAX_ERROR;
}
#define OPENOCD_FLASH_NAND_LPC32XX_H
enum lpc32xx_selected_controller {
- LPC32xx_NO_CONTROLLER,
- LPC32xx_MLC_CONTROLLER,
- LPC32xx_SLC_CONTROLLER,
+ LPC32XX_NO_CONTROLLER,
+ LPC32XX_MLC_CONTROLLER,
+ LPC32XX_SLC_CONTROLLER,
};
struct lpc32xx_nand_controller {
#define S3C2410_NFCONF_512BYTE (1 << 14)
#define S3C2410_NFCONF_4STEP (1 << 13)
#define S3C2410_NFCONF_INITECC (1 << 12)
-#define S3C2410_NFCONF_nFCE (1 << 11)
+#define S3C2410_NFCONF_NFCE (1 << 11)
#define S3C2410_NFCONF_TACLS(x) ((x) << 8)
#define S3C2410_NFCONF_TWRPH0(x) ((x) << 4)
#define S3C2410_NFCONF_TWRPH1(x) ((x) << 0)
#define S3C2440_NFCONT_SPARE_ECCLOCK (1 << 6)
#define S3C2440_NFCONT_MAIN_ECCLOCK (1 << 5)
#define S3C2440_NFCONT_INITECC (1 << 4)
-#define S3C2440_NFCONT_nFCE (1 << 1)
+#define S3C2440_NFCONT_NFCE (1 << 1)
#define S3C2440_NFCONT_ENABLE (1 << 0)
#define S3C2440_NFSTAT_READY (1 << 0)
-#define S3C2440_NFSTAT_nCE (1 << 1)
-#define S3C2440_NFSTAT_RnB_CHANGE (1 << 2)
+#define S3C2440_NFSTAT_NCE (1 << 1)
+#define S3C2440_NFSTAT_RNB_CHANGE (1 << 2)
#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1 << 3)
#define S3C2412_NFCONF_NANDBOOT (1 << 31)
#define S3C2412_NFCONT_ECC4_DECINT (1 << 12)
#define S3C2412_NFCONT_MAIN_ECC_LOCK (1 << 7)
#define S3C2412_NFCONT_INIT_MAIN_ECC (1 << 5)
-#define S3C2412_NFCONT_nFCE1 (1 << 2)
-#define S3C2412_NFCONT_nFCE0 (1 << 1)
+#define S3C2412_NFCONT_NFCE1 (1 << 2)
+#define S3C2412_NFCONT_NFCE0 (1 << 1)
#define S3C2412_NFSTAT_ECC_ENCDONE (1 << 7)
#define S3C2412_NFSTAT_ECC_DECDONE (1 << 6)
#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1 << 5)
-#define S3C2412_NFSTAT_RnB_CHANGE (1 << 4)
-#define S3C2412_NFSTAT_nFCE1 (1 << 3)
-#define S3C2412_NFSTAT_nFCE0 (1 << 2)
-#define S3C2412_NFSTAT_Res1 (1 << 1)
+#define S3C2412_NFSTAT_RNB_CHANGE (1 << 4)
+#define S3C2412_NFSTAT_NFCE1 (1 << 3)
+#define S3C2412_NFSTAT_NFCE0 (1 << 2)
+#define S3C2412_NFSTAT_RES1 (1 << 1)
#define S3C2412_NFSTAT_READY (1 << 0)
#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms);
static int aduc702x_set_write_enable(struct target *target, int enable);
-#define ADUC702x_FLASH 0xfffff800
-#define ADUC702x_FLASH_FEESTA (0*4)
-#define ADUC702x_FLASH_FEEMOD (1*4)
-#define ADUC702x_FLASH_FEECON (2*4)
-#define ADUC702x_FLASH_FEEDAT (3*4)
-#define ADUC702x_FLASH_FEEADR (4*4)
-#define ADUC702x_FLASH_FEESIGN (5*4)
-#define ADUC702x_FLASH_FEEPRO (6*4)
-#define ADUC702x_FLASH_FEEHIDE (7*4)
+#define ADUC702X_FLASH 0xfffff800
+#define ADUC702X_FLASH_FEESTA (0*4)
+#define ADUC702X_FLASH_FEEMOD (1*4)
+#define ADUC702X_FLASH_FEECON (2*4)
+#define ADUC702X_FLASH_FEEDAT (3*4)
+#define ADUC702X_FLASH_FEEADR (4*4)
+#define ADUC702X_FLASH_FEESIGN (5*4)
+#define ADUC702X_FLASH_FEEPRO (6*4)
+#define ADUC702X_FLASH_FEEHIDE (7*4)
/* flash bank aduc702x 0 0 0 0 <target#>
* The ADC7019-28 devices all have the same flash layout */
/* mass erase */
if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
LOG_DEBUG("performing mass erase.");
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, 0x3cff);
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, 0xffc3);
- target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x06);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEDAT, 0x3cff);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, 0xffc3);
+ target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x06);
if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK) {
LOG_ERROR("mass erase failed");
for (x = 0; x < count; ++x) {
adr = bank->base + ((first + x) * 512);
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
- target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, adr);
+ target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x05);
if (aduc702x_check_flash_completion(target, 50) != ERROR_OK) {
LOG_ERROR("failed to erase sector at address 0x%08lX", adr);
for (x = 0; x < count; x += 2) {
/* FEEADR = address */
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, offset + x);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, offset + x);
/* set up data */
if ((x + 1) == count) {
} else
b = buffer[x + 1];
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEDAT, buffer[x] | (b << 8));
/* do single-write command */
- target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x02);
+ target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x02);
if (aduc702x_check_flash_completion(target, 1) != ERROR_OK) {
LOG_ERROR("single write failed for address 0x%08lX",
static int aduc702x_set_write_enable(struct target *target, int enable)
{
/* don't bother to preserve int enable bit here */
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEMOD, enable ? 8 : 0);
return ERROR_OK;
}
int64_t endtime = timeval_ms() + timeout_ms;
while (1) {
- target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
+ target_read_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEESTA, &v);
if ((v & 4) == 0)
break;
alive_sleep(1);
uint8_t class;
uint8_t partno;
const char *partname;
-} ambiqmicroParts[6] = {
+} ambiqmicro_parts[6] = {
{0xFF, 0x00, "Unknown"},
{0x01, 0x00, "Apollo"},
{0x02, 0x00, "Apollo2"},
{0x05, 0x00, "Apollo"},
};
-static char *ambiqmicroClassname[6] = {
+static char *ambiqmicro_classname[6] = {
"Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
};
}
/* Check class name in range. */
- if (ambiqmicro_info->target_class < sizeof(ambiqmicroClassname))
- classname = ambiqmicroClassname[ambiqmicro_info->target_class];
+ if (ambiqmicro_info->target_class < sizeof(ambiqmicro_classname))
+ classname = ambiqmicro_classname[ambiqmicro_info->target_class];
else
- classname = ambiqmicroClassname[0];
+ classname = ambiqmicro_classname[0];
command_print_sameline(cmd, "\nAmbiq Micro information: Chip is "
"class %d (%s) %s\n",
{
struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
struct target *target = bank->target;
- uint32_t PartNum = 0;
+ uint32_t part_num = 0;
int retval;
/*
* Read Part Number.
*/
- retval = target_read_u32(target, 0x40020000, &PartNum);
+ retval = target_read_u32(target, 0x40020000, &part_num);
if (retval != ERROR_OK) {
- LOG_ERROR("status(0x%x):Could not read PartNum.\n", retval);
- /* Set PartNum to default device */
- PartNum = 0;
+ LOG_ERROR("status(0x%x):Could not read part_num.\n", retval);
+ /* Set part_num to default device */
+ part_num = 0;
}
- LOG_DEBUG("Part number: 0x%" PRIx32, PartNum);
+ LOG_DEBUG("Part number: 0x%" PRIx32, part_num);
/*
* Determine device class.
*/
- ambiqmicro_info->target_class = (PartNum & 0xFF000000) >> 24;
+ ambiqmicro_info->target_class = (part_num & 0xFF000000) >> 24;
switch (ambiqmicro_info->target_class) {
case 1: /* 1 - Apollo */
bank->base = bank->bank_number * 0x40000;
ambiqmicro_info->pagesize = 2048;
ambiqmicro_info->flshsiz =
- apollo_flash_size[(PartNum & 0x00F00000) >> 20];
+ apollo_flash_size[(part_num & 0x00F00000) >> 20];
ambiqmicro_info->sramsiz =
- apollo_sram_size[(PartNum & 0x000F0000) >> 16];
+ apollo_sram_size[(part_num & 0x000F0000) >> 16];
ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
ambiqmicro_info->pagesize;
if (ambiqmicro_info->num_pages > 128) {
}
- if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicroParts))
+ if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicro_parts))
ambiqmicro_info->target_name =
- ambiqmicroParts[ambiqmicro_info->target_class].partname;
+ ambiqmicro_parts[ambiqmicro_info->target_class].partname;
else
ambiqmicro_info->target_name =
- ambiqmicroParts[0].partname;
+ ambiqmicro_parts[0].partname;
LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
ambiqmicro_info->num_pages,
#define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
#define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
-#define offset_EFC_FMR 0
-#define offset_EFC_FCR 4
-#define offset_EFC_FSR 8
-#define offset_EFC_FRR 12
+#define OFFSET_EFC_FMR 0
+#define OFFSET_EFC_FCR 4
+#define OFFSET_EFC_FSR 8
+#define OFFSET_EFC_FRR 12
extern const struct flash_driver at91sam3_flash;
/* DANGER: THERE ARE DRAGONS HERE.. */
/* NOTE: If you add more 'ghost' pointers */
/* be aware that you must *manually* update */
- /* these pointers in the function sam3_GetDetails() */
+ /* these pointers in the function sam3_get_details() */
/* See the comment "Here there be dragons" */
/* so we can find the chip we belong to */
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
/* so we can find the original bank pointer */
- struct flash_bank *pBank;
+ struct flash_bank *bank;
unsigned bank_number;
uint32_t controller_address;
uint32_t base_address;
/* note: If you add pointers here */
/* be careful about them as they */
/* may need to be updated inside */
- /* the function: "sam3_GetDetails() */
+ /* the function: "sam3_get_details() */
/* which copy/overwrites the */
/* 'runtime' copy of this structure */
uint32_t chipid_cidr;
struct sam3_reg_list {
uint32_t address; size_t struct_offset; const char *name;
- void (*explain_func)(struct sam3_chip *pInfo);
+ void (*explain_func)(struct sam3_chip *chip);
};
static struct sam3_chip *all_sam3_chips;
return NULL;
}
-/* these are used to *initialize* the "pChip->details" structure. */
+/* these are used to *initialize* the "chip->details" structure. */
static const struct sam3_chip_details all_sam3_details[] = {
/* Start at91sam3u* series */
{
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
{
/* .bank[0] = { */
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
/**
* Get the current status of the EEFC and
* the value of some status bits (LOCKE, PROGE).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
{
int r;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FSR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FSR,
v);
LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
(unsigned int)(*v),
/**
* Get the result of the last executed command.
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
{
int r;
uint32_t rv;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FRR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FRR,
&rv);
if (v)
*v = rv;
return r;
}
-static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
+static int efc_start_command(struct sam3_bank_private *private,
unsigned command, unsigned argument)
{
uint32_t n, v;
/* case AT91C_EFC_FCMD_EPA: */
case AT91C_EFC_FCMD_SLB:
case AT91C_EFC_FCMD_CLB:
- n = (pPrivate->size_bytes / pPrivate->page_size);
+ n = (private->size_bytes / private->page_size);
if (argument >= n)
LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
break;
case AT91C_EFC_FCMD_SFB:
case AT91C_EFC_FCMD_CFB:
- if (argument >= pPrivate->pChip->details.n_gpnvms) {
+ if (argument >= private->chip->details.n_gpnvms) {
LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
- pPrivate->pChip->details.n_gpnvms);
+ private->chip->details.n_gpnvms);
}
break;
/* Situation (2) - normal, finished reading unique id */
} else {
/* it should be "ready" */
- EFC_GetStatus(pPrivate, &v);
+ efc_get_status(private, &v);
if (v & 1) {
/* then it is ready */
/* we go on */
/* we have done this before */
/* the controller is not responding. */
LOG_ERROR("flash controller(%d) is not ready! Error",
- pPrivate->bank_number);
+ private->bank_number);
return ERROR_FAIL;
} else {
retry++;
LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
- pPrivate->bank_number);
+ private->bank_number);
/* we do that by issuing the *STOP* command */
- EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
+ efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
/* above is recursive, and further recursion is blocked by */
/* if (command == AT91C_EFC_FCMD_SPUI) above */
goto do_retry;
v = (0x5A << 24) | (argument << 8) | command;
LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
- r = target_write_u32(pPrivate->pBank->target,
- pPrivate->controller_address + offset_EFC_FCR, v);
+ r = target_write_u32(private->bank->target,
+ private->controller_address + OFFSET_EFC_FCR, v);
if (r != ERROR_OK)
LOG_DEBUG("Error Write failed");
return r;
/**
* Performs the given command and wait until its completion (or an error).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param command - Command to perform.
* @param argument - Optional command argument.
* @param status - put command status bits here
*/
-static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
+static int efc_perform_command(struct sam3_bank_private *private,
unsigned command,
unsigned argument,
uint32_t *status)
if (status)
*status = 0;
- r = EFC_StartCommand(pPrivate, command, argument);
+ r = efc_start_command(private, command, argument);
if (r != ERROR_OK)
return r;
ms_end = 500 + timeval_ms();
do {
- r = EFC_GetStatus(pPrivate, &v);
+ r = efc_get_status(private, &v);
if (r != ERROR_OK)
return r;
ms_now = timeval_ms();
/**
* Read the unique ID.
- * @param pPrivate - info about the bank
- * The unique ID is stored in the 'pPrivate' structure.
+ * @param private - info about the bank
+ * The unique ID is stored in the 'private' structure.
*/
-static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
+static int flashd_read_uid(struct sam3_bank_private *private)
{
int r;
uint32_t v;
int x;
/* assume 0 */
- pPrivate->pChip->cfg.unique_id[0] = 0;
- pPrivate->pChip->cfg.unique_id[1] = 0;
- pPrivate->pChip->cfg.unique_id[2] = 0;
- pPrivate->pChip->cfg.unique_id[3] = 0;
+ private->chip->cfg.unique_id[0] = 0;
+ private->chip->cfg.unique_id[1] = 0;
+ private->chip->cfg.unique_id[2] = 0;
+ private->chip->cfg.unique_id[3] = 0;
LOG_DEBUG("Begin");
- r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
+ r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
if (r < 0)
return r;
for (x = 0; x < 4; x++) {
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->pBank->base + (x * 4),
+ r = target_read_u32(private->chip->target,
+ private->bank->base + (x * 4),
&v);
if (r < 0)
return r;
- pPrivate->pChip->cfg.unique_id[x] = v;
+ private->chip->cfg.unique_id[x] = v;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
r,
- (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
+ (unsigned int)(private->chip->cfg.unique_id[0]),
+ (unsigned int)(private->chip->cfg.unique_id[1]),
+ (unsigned int)(private->chip->cfg.unique_id[2]),
+ (unsigned int)(private->chip->cfg.unique_id[3]));
return r;
}
/**
* Erases the entire flash.
- * @param pPrivate - the info about the bank.
+ * @param private - the info about the bank.
*/
-static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
+static int flashd_erase_entire_bank(struct sam3_bank_private *private)
{
LOG_DEBUG("Here");
- return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
+ return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
}
/**
* Gets current GPNVM state.
- * @param pPrivate - info about the bank.
+ * @param private - info about the bank.
* @param gpnvm - GPNVM bit index.
* @param puthere - result stored here.
*/
/* ------------------------------------------------------------------------------ */
-static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
+static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned gpnvm, unsigned *puthere)
{
uint32_t v;
int r;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
/* Get GPNVMs status */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
if (r != ERROR_OK) {
LOG_ERROR("Failed");
return r;
}
- r = EFC_GetResult(pPrivate, &v);
+ r = efc_get_result(private, &v);
if (puthere) {
/* Check if GPNVM is set */
/**
* Clears the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
* @returns 0 if successful; otherwise returns an error code.
*/
-static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK) {
LOG_DEBUG("Failed: %d", r);
return r;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
LOG_DEBUG("End: %d", r);
return r;
}
/**
* Sets the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
*/
-static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK)
return r;
if (v) {
r = ERROR_OK;
} else {
/* set it */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
}
return r;
}
/**
* Returns a bit field (at most 64) of locked regions within a page.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param v where to store locked bits
*/
-static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
{
int r;
LOG_DEBUG("Here");
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
if (r == ERROR_OK)
- r = EFC_GetResult(pPrivate, v);
+ r = efc_get_result(private, v);
LOG_DEBUG("End: %d", r);
return r;
}
/**
* Unlocks all the regions in the given address range.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param start_sector first sector to unlock
* @param end_sector last (inclusive) to unlock
*/
-static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
+static int flashd_unlock(struct sam3_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
uint32_t pg;
uint32_t pages_per_sector;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Unlock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
/**
* Locks regions
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param start_sector - first sector to lock
* @param end_sector - last sector (inclusive) to lock
*/
-static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
+static int flashd_lock(struct sam3_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
uint32_t pages_per_sector;
int r;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Lock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
/* begin helpful debug code */
/* print the fieldname, the field value, in dec & hex, and return field value */
-static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
+static uint32_t sam3_reg_fieldname(struct sam3_chip *chip,
const char *regname,
uint32_t value,
unsigned shift,
"4 MHz", "8 MHz", "12 MHz", "reserved"
};
-static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
{
uint32_t v;
uint32_t rcen;
- v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
+ v = sam3_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
- v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
+ v = sam3_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
- rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
+ rcen = sam3_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
- v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
+ v = sam3_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
if (rcen) {
switch (v) {
default:
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
break;
case 0:
- pChip->cfg.rc_freq = 4 * 1000 * 1000;
+ chip->cfg.rc_freq = 4 * 1000 * 1000;
break;
case 1:
- pChip->cfg.rc_freq = 8 * 1000 * 1000;
+ chip->cfg.rc_freq = 8 * 1000 * 1000;
break;
case 2:
- pChip->cfg.rc_freq = 12 * 1000 * 1000;
+ chip->cfg.rc_freq = 12 * 1000 * 1000;
break;
}
}
- v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
+ v = sam3_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
LOG_USER("(startup clks, time= %f uSecs)",
- ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
- v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
+ ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
+ v = sam3_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
LOG_USER("(mainosc source: %s)",
v ? "external xtal" : "internal RC");
- v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
+ v = sam3_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
LOG_USER("(clock failure enabled: %s)",
_yes_or_no(v));
}
-static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
+static void sam3_explain_chipid_cidr(struct sam3_chip *chip)
{
int x;
uint32_t v;
const char *cp;
- sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
+ sam3_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
LOG_USER_N("\n");
- v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
+ v = sam3_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
LOG_USER("%s", eproc_names[v]);
- v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
+ v = sam3_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
LOG_USER("%s", nvpsize[v]);
- v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
+ v = sam3_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
LOG_USER("%s", nvpsize2[v]);
- v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
+ v = sam3_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
LOG_USER("%s", sramsize[v]);
- v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
+ v = sam3_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
cp = _unknown;
for (x = 0; archnames[x].name; x++) {
if (v == archnames[x].value) {
LOG_USER("%s", cp);
- v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
+ v = sam3_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
LOG_USER("%s", nvptype[v]);
- v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
+ v = sam3_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
LOG_USER("(exists: %s)", _yes_or_no(v));
}
-static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_mcfr(struct sam3_chip *chip)
{
uint32_t v;
- v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
+ v = sam3_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
LOG_USER("(main ready: %s)", _yes_or_no(v));
- v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
+ v = sam3_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
- v = (v * pChip->cfg.slow_freq) / 16;
- pChip->cfg.mainosc_freq = v;
+ v = (v * chip->cfg.slow_freq) / 16;
+ chip->cfg.mainosc_freq = v;
LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
_tomhz(v),
- (uint32_t)(pChip->cfg.slow_freq / 1000),
- (uint32_t)(pChip->cfg.slow_freq % 1000));
+ (uint32_t)(chip->cfg.slow_freq / 1000),
+ (uint32_t)(chip->cfg.slow_freq % 1000));
}
-static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_plla(struct sam3_chip *chip)
{
uint32_t mula, diva;
- diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
+ diva = sam3_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
LOG_USER_N("\n");
- mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
+ mula = sam3_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
LOG_USER_N("\n");
- pChip->cfg.plla_freq = 0;
+ chip->cfg.plla_freq = 0;
if (mula == 0)
LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
else if (diva == 0)
LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
else if (diva >= 1) {
- pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
+ chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
LOG_USER("\tPLLA Freq: %3.03f MHz",
- _tomhz(pChip->cfg.plla_freq));
+ _tomhz(chip->cfg.plla_freq));
}
}
-static void sam3_explain_mckr(struct sam3_chip *pChip)
+static void sam3_explain_mckr(struct sam3_chip *chip)
{
uint32_t css, pres, fin = 0;
int pdiv = 0;
const char *cp = NULL;
- css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
+ css = sam3_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
switch (css & 3) {
case 0:
- fin = pChip->cfg.slow_freq;
+ fin = chip->cfg.slow_freq;
cp = "slowclk";
break;
case 1:
- fin = pChip->cfg.mainosc_freq;
+ fin = chip->cfg.mainosc_freq;
cp = "mainosc";
break;
case 2:
- fin = pChip->cfg.plla_freq;
+ fin = chip->cfg.plla_freq;
cp = "plla";
break;
case 3:
- if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
+ if (chip->cfg.CKGR_UCKR & (1 << 16)) {
fin = 480 * 1000 * 1000;
cp = "upll";
} else {
LOG_USER("%s (%3.03f Mhz)",
cp,
_tomhz(fin));
- pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
+ pres = sam3_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
switch (pres & 0x07) {
case 0:
pdiv = 1;
fin = fin / pdiv;
/* sam3 has a *SINGLE* clock - */
/* other at91 series parts have divisors for these. */
- pChip->cfg.cpu_freq = fin;
- pChip->cfg.mclk_freq = fin;
- pChip->cfg.fclk_freq = fin;
+ chip->cfg.cpu_freq = fin;
+ chip->cfg.mclk_freq = fin;
+ chip->cfg.fclk_freq = fin;
LOG_USER("\t\tResult CPU Freq: %3.03f",
_tomhz(fin));
}
#if 0
-static struct sam3_chip *target2sam3(struct target *pTarget)
+static struct sam3_chip *target2sam3(struct target *target)
{
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
- if (pTarget == NULL)
+ if (target == NULL)
return NULL;
- pChip = all_sam3_chips;
- while (pChip) {
- if (pChip->target == pTarget)
+ chip = all_sam3_chips;
+ while (chip) {
+ if (chip->target == target)
break; /* return below */
else
- pChip = pChip->next;
+ chip = chip->next;
}
- return pChip;
+ return chip;
}
#endif
-static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
+static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *cfg, const struct sam3_reg_list *list)
{
/* this function exists to help */
/* keep funky offsetof() errors */
/* By using prototypes - we can detect what would */
/* be casting errors. */
- return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
+ return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
}
* Given a pointer to where it goes in the structure,
* determine the register name, address from the all registers table.
*/
-static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
+static const struct sam3_reg_list *sam3_get_reg(struct sam3_chip *chip, uint32_t *goes_here)
{
- const struct sam3_reg_list *pReg;
+ const struct sam3_reg_list *reg;
- pReg = &(sam3_all_regs[0]);
- while (pReg->name) {
- uint32_t *pPossible;
+ reg = &(sam3_all_regs[0]);
+ while (reg->name) {
+ uint32_t *possible;
/* calculate where this one go.. */
/* it is "possibly" this register. */
- pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
+ possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
/* well? Is it this register */
- if (pPossible == goes_here) {
+ if (possible == goes_here) {
/* Jump for joy! */
- return pReg;
+ return reg;
}
/* next... */
- pReg++;
+ reg++;
}
/* This is *TOTAL*PANIC* - we are totally screwed. */
LOG_ERROR("INVALID SAM3 REGISTER");
return NULL;
}
-static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
+static int sam3_read_this_reg(struct sam3_chip *chip, uint32_t *goes_here)
{
- const struct sam3_reg_list *pReg;
+ const struct sam3_reg_list *reg;
int r;
- pReg = sam3_GetReg(pChip, goes_here);
- if (!pReg)
+ reg = sam3_get_reg(chip, goes_here);
+ if (!reg)
return ERROR_FAIL;
- r = target_read_u32(pChip->target, pReg->address, goes_here);
+ r = target_read_u32(chip->target, reg->address, goes_here);
if (r != ERROR_OK) {
LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
- pReg->name, (unsigned)(pReg->address), r);
+ reg->name, (unsigned)(reg->address), r);
}
return r;
}
-static int sam3_ReadAllRegs(struct sam3_chip *pChip)
+static int sam3_read_all_regs(struct sam3_chip *chip)
{
int r;
- const struct sam3_reg_list *pReg;
+ const struct sam3_reg_list *reg;
- pReg = &(sam3_all_regs[0]);
- while (pReg->name) {
- r = sam3_ReadThisReg(pChip,
- sam3_get_reg_ptr(&(pChip->cfg), pReg));
+ reg = &(sam3_all_regs[0]);
+ while (reg->name) {
+ r = sam3_read_this_reg(chip,
+ sam3_get_reg_ptr(&(chip->cfg), reg));
if (r != ERROR_OK) {
LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
- pReg->name, ((unsigned)(pReg->address)), r);
+ reg->name, ((unsigned)(reg->address)), r);
return r;
}
- pReg++;
+ reg++;
}
/* Chip identification register
* located in the memory map of the Power Management Controller
* (PMC). Furthermore, the address is not used by the PMC.
* So when read, the memory controller returns zero.*/
- if (pChip->cfg.CHIPID_CIDR == 0) {
- /*Put the correct CIDR and EXID values in the pChip structure */
- pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
- pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
+ if (chip->cfg.CHIPID_CIDR == 0) {
+ /*Put the correct CIDR and EXID values in the chip structure */
+ chip->cfg.CHIPID_CIDR = chip->cfg.CHIPID_CIDR2;
+ chip->cfg.CHIPID_EXID = chip->cfg.CHIPID_EXID2;
}
return ERROR_OK;
}
-static int sam3_GetInfo(struct sam3_chip *pChip)
+static int sam3_get_info(struct sam3_chip *chip)
{
- const struct sam3_reg_list *pReg;
+ const struct sam3_reg_list *reg;
uint32_t regval;
- pReg = &(sam3_all_regs[0]);
- while (pReg->name) {
+ reg = &(sam3_all_regs[0]);
+ while (reg->name) {
/* display all regs */
- LOG_DEBUG("Start: %s", pReg->name);
- regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
+ LOG_DEBUG("Start: %s", reg->name);
+ regval = *sam3_get_reg_ptr(&(chip->cfg), reg);
LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
REG_NAME_WIDTH,
- pReg->name,
- pReg->address,
+ reg->name,
+ reg->address,
regval);
- if (pReg->explain_func)
- (*(pReg->explain_func))(pChip);
- LOG_DEBUG("End: %s", pReg->name);
- pReg++;
+ if (reg->explain_func)
+ (*(reg->explain_func))(chip);
+ LOG_DEBUG("End: %s", reg->name);
+ reg++;
}
- LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
- LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
- LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
- LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
- LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
+ LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
+ LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
+ LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
+ LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
+ LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
- pChip->cfg.unique_id[0],
- pChip->cfg.unique_id[1],
- pChip->cfg.unique_id[2],
- pChip->cfg.unique_id[3]);
+ chip->cfg.unique_id[0],
+ chip->cfg.unique_id[1],
+ chip->cfg.unique_id[2],
+ chip->cfg.unique_id[3]);
return ERROR_OK;
}
int r;
uint32_t v = 0;
unsigned x;
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
LOG_DEBUG("Begin");
if (bank->target->state != TARGET_HALTED) {
return ERROR_TARGET_NOT_HALTED;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!pPrivate) {
+ private = get_sam3_bank_private(bank);
+ if (!private) {
LOG_ERROR("no private for this bank?");
return ERROR_FAIL;
}
- if (!(pPrivate->probed))
+ if (!(private->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
- r = FLASHD_GetLockBits(pPrivate, &v);
+ r = flashd_get_lock_bits(private, &v);
if (r != ERROR_OK) {
LOG_DEBUG("Failed: %d", r);
return r;
}
- for (x = 0; x < pPrivate->nsectors; x++)
+ for (x = 0; x < private->nsectors; x++)
bank->sectors[x].is_protected = (!!(v & (1 << x)));
LOG_DEBUG("Done");
return ERROR_OK;
FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
{
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
- pChip = all_sam3_chips;
+ chip = all_sam3_chips;
/* is this an existing chip? */
- while (pChip) {
- if (pChip->target == bank->target)
+ while (chip) {
+ if (chip->target == bank->target)
break;
- pChip = pChip->next;
+ chip = chip->next;
}
- if (!pChip) {
+ if (!chip) {
/* this is a *NEW* chip */
- pChip = calloc(1, sizeof(struct sam3_chip));
- if (!pChip) {
+ chip = calloc(1, sizeof(struct sam3_chip));
+ if (!chip) {
LOG_ERROR("NO RAM!");
return ERROR_FAIL;
}
- pChip->target = bank->target;
+ chip->target = bank->target;
/* insert at head */
- pChip->next = all_sam3_chips;
- all_sam3_chips = pChip;
- pChip->target = bank->target;
+ chip->next = all_sam3_chips;
+ all_sam3_chips = chip;
+ chip->target = bank->target;
/* assumption is this runs at 32khz */
- pChip->cfg.slow_freq = 32768;
- pChip->probed = false;
+ chip->cfg.slow_freq = 32768;
+ chip->probed = false;
}
switch (bank->base) {
/* at91sam3u and at91sam3ax series has the same address for bank 0*/
case FLASH_BANK_BASE_S:
case FLASH_BANK0_BASE_U:
- bank->driver_priv = &(pChip->details.bank[0]);
+ bank->driver_priv = &(chip->details.bank[0]);
bank->bank_number = 0;
- pChip->details.bank[0].pChip = pChip;
- pChip->details.bank[0].pBank = bank;
+ chip->details.bank[0].chip = chip;
+ chip->details.bank[0].bank = bank;
break;
/* Bank 1 of at91sam3u or at91sam3ax series */
case FLASH_BANK1_BASE_U:
case FLASH_BANK1_BASE_256K_AX:
case FLASH_BANK1_BASE_512K_AX:
- bank->driver_priv = &(pChip->details.bank[1]);
+ bank->driver_priv = &(chip->details.bank[1]);
bank->bank_number = 1;
- pChip->details.bank[1].pChip = pChip;
- pChip->details.bank[1].pBank = bank;
+ chip->details.bank[1].chip = chip;
+ chip->details.bank[1].bank = bank;
break;
}
all_sam3_chips = NULL;
}
-static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
+static int sam3_get_details(struct sam3_bank_private *private)
{
- const struct sam3_chip_details *pDetails;
- struct sam3_chip *pChip;
+ const struct sam3_chip_details *details;
+ struct sam3_chip *chip;
struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
unsigned x;
LOG_DEBUG("Begin");
- pDetails = all_sam3_details;
- while (pDetails->name) {
+ details = all_sam3_details;
+ while (details->name) {
/* Compare cidr without version bits */
- if (((pDetails->chipid_cidr ^ pPrivate->pChip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
+ if (((details->chipid_cidr ^ private->chip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
break;
else
- pDetails++;
+ details++;
}
- if (pDetails->name == NULL) {
+ if (details->name == NULL) {
LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
- (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
+ (unsigned int)(private->chip->cfg.CHIPID_CIDR));
/* Help the victim, print details about the chip */
LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
- pPrivate->pChip->cfg.CHIPID_CIDR);
- sam3_explain_chipid_cidr(pPrivate->pChip);
+ private->chip->cfg.CHIPID_CIDR);
+ sam3_explain_chipid_cidr(private->chip);
return ERROR_FAIL;
}
/* DANGER: THERE ARE DRAGONS HERE */
- /* get our pChip - it is going */
+ /* get our chip - it is going */
/* to be over-written shortly */
- pChip = pPrivate->pChip;
+ chip = private->chip;
/* Note that, in reality: */
/* */
- /* pPrivate = &(pChip->details.bank[0]) */
- /* or pPrivate = &(pChip->details.bank[1]) */
+ /* private = &(chip->details.bank[0]) */
+ /* or private = &(chip->details.bank[1]) */
/* */
/* save the "bank" pointers */
for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
- saved_banks[x] = pChip->details.bank[x].pBank;
+ saved_banks[x] = chip->details.bank[x].bank;
/* Overwrite the "details" structure. */
- memcpy(&(pPrivate->pChip->details),
- pDetails,
- sizeof(pPrivate->pChip->details));
+ memcpy(&(private->chip->details),
+ details,
+ sizeof(private->chip->details));
/* now fix the ghosted pointers */
for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
- pChip->details.bank[x].pChip = pChip;
- pChip->details.bank[x].pBank = saved_banks[x];
+ chip->details.bank[x].chip = chip;
+ chip->details.bank[x].bank = saved_banks[x];
}
/* update the *BANK*SIZE* */
static int _sam3_probe(struct flash_bank *bank, int noise)
{
int r;
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank->bank_number, noise);
return ERROR_TARGET_NOT_HALTED;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!pPrivate) {
+ private = get_sam3_bank_private(bank);
+ if (!private) {
LOG_ERROR("Invalid/unknown bank number");
return ERROR_FAIL;
}
- r = sam3_ReadAllRegs(pPrivate->pChip);
+ r = sam3_read_all_regs(private->chip);
if (r != ERROR_OK)
return r;
LOG_DEBUG("Here");
- if (pPrivate->pChip->probed)
- r = sam3_GetInfo(pPrivate->pChip);
+ if (private->chip->probed)
+ r = sam3_get_info(private->chip);
else
- r = sam3_GetDetails(pPrivate);
+ r = sam3_get_details(private);
if (r != ERROR_OK)
return r;
/* update the flash bank size */
for (unsigned int x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
- if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
- bank->size = pPrivate->pChip->details.bank[x].size_bytes;
+ if (bank->base == private->chip->details.bank[x].base_address) {
+ bank->size = private->chip->details.bank[x].size_bytes;
break;
}
}
if (bank->sectors == NULL) {
- bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
+ bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
if (bank->sectors == NULL) {
LOG_ERROR("No memory!");
return ERROR_FAIL;
}
- bank->num_sectors = pPrivate->nsectors;
+ bank->num_sectors = private->nsectors;
for (unsigned int x = 0; x < bank->num_sectors; x++) {
- bank->sectors[x].size = pPrivate->sector_size;
- bank->sectors[x].offset = x * (pPrivate->sector_size);
+ bank->sectors[x].size = private->sector_size;
+ bank->sectors[x].offset = x * (private->sector_size);
/* mark as unknown */
bank->sectors[x].is_erased = -1;
bank->sectors[x].is_protected = -1;
}
}
- pPrivate->probed = true;
+ private->probed = true;
r = sam3_protect_check(bank);
if (r != ERROR_OK)
return r;
LOG_DEBUG("Bank = %d, nbanks = %d",
- pPrivate->bank_number, pPrivate->pChip->details.n_banks);
- if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
+ private->bank_number, private->chip->details.n_banks);
+ if ((private->bank_number + 1) == private->chip->details.n_banks) {
/* read unique id, */
/* it appears to be associated with the *last* flash bank. */
- FLASHD_ReadUniqueID(pPrivate);
+ flashd_read_uid(private);
}
return r;
static int sam3_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
{
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
int r;
LOG_DEBUG("Here");
return r;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!(pPrivate->probed))
+ private = get_sam3_bank_private(bank);
+ if (!(private->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
- if ((first == 0) && ((last + 1) == pPrivate->nsectors)) {
+ if ((first == 0) && ((last + 1) == private->nsectors)) {
/* whole chip */
LOG_DEBUG("Here");
- return FLASHD_EraseEntireBank(pPrivate);
+ return flashd_erase_entire_bank(private);
}
LOG_INFO("sam3 auto-erases while programming (request ignored)");
return ERROR_OK;
static int sam3_protect(struct flash_bank *bank, int set, unsigned int first,
unsigned int last)
{
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
int r;
LOG_DEBUG("Here");
return ERROR_TARGET_NOT_HALTED;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!(pPrivate->probed))
+ private = get_sam3_bank_private(bank);
+ if (!(private->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
if (set)
- r = FLASHD_Lock(pPrivate, first, last);
+ r = flashd_lock(private, first, last);
else
- r = FLASHD_Unlock(pPrivate, first, last);
+ r = flashd_unlock(private, first, last);
LOG_DEBUG("End: r=%d", r);
return r;
}
-static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
+static int sam3_page_read(struct sam3_bank_private *private, unsigned pagenum, uint8_t *buf)
{
uint32_t adr;
int r;
- adr = pagenum * pPrivate->page_size;
- adr += pPrivate->base_address;
+ adr = pagenum * private->page_size;
+ adr += private->base_address;
- r = target_read_memory(pPrivate->pChip->target,
+ r = target_read_memory(private->chip->target,
adr,
4, /* THIS*MUST*BE* in 32bit values */
- pPrivate->page_size / 4,
+ private->page_size / 4,
buf);
if (r != ERROR_OK)
LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
return r;
}
-static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
+static int sam3_page_write(struct sam3_bank_private *private, unsigned pagenum, const uint8_t *buf)
{
uint32_t adr;
uint32_t status;
uint32_t fmr; /* EEFC Flash Mode Register */
int r;
- adr = pagenum * pPrivate->page_size;
- adr += pPrivate->base_address;
+ adr = pagenum * private->page_size;
+ adr += private->base_address;
/* Get flash mode register value */
- r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
+ r = target_read_u32(private->chip->target, private->controller_address, &fmr);
if (r != ERROR_OK)
LOG_DEBUG("Error Read failed: read flash mode register");
fmr &= 0xfffff0ff;
/* set FWS (flash wait states) field in the FMR (flash mode register) */
- fmr |= (pPrivate->flash_wait_states << 8);
+ fmr |= (private->flash_wait_states << 8);
LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
- r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
+ r = target_write_u32(private->bank->target, private->controller_address, fmr);
if (r != ERROR_OK)
LOG_DEBUG("Error Write failed: set flash mode register");
LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
- r = target_write_memory(pPrivate->pChip->target,
+ r = target_write_memory(private->chip->target,
adr,
4, /* THIS*MUST*BE* in 32bit values */
- pPrivate->page_size / 4,
+ private->page_size / 4,
buf);
if (r != ERROR_OK) {
LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
return r;
}
- r = EFC_PerformCommand(pPrivate,
+ r = efc_perform_command(private,
/* send Erase & Write Page */
AT91C_EFC_FCMD_EWP,
pagenum,
unsigned page_end;
int r;
unsigned page_offset;
- struct sam3_bank_private *pPrivate;
+ struct sam3_bank_private *private;
uint8_t *pagebuffer;
/* in case we bail further below, set this to null */
goto done;
}
- pPrivate = get_sam3_bank_private(bank);
- if (!(pPrivate->probed)) {
+ private = get_sam3_bank_private(bank);
+ if (!(private->probed)) {
r = ERROR_FLASH_BANK_NOT_PROBED;
goto done;
}
- if ((offset + count) > pPrivate->size_bytes) {
+ if ((offset + count) > private->size_bytes) {
LOG_ERROR("Flash write error - past end of bank");
LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
(unsigned int)(offset),
(unsigned int)(count),
- (unsigned int)(pPrivate->size_bytes));
+ (unsigned int)(private->size_bytes));
r = ERROR_FAIL;
goto done;
}
- pagebuffer = malloc(pPrivate->page_size);
+ pagebuffer = malloc(private->page_size);
if (!pagebuffer) {
- LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
+ LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
r = ERROR_FAIL;
goto done;
}
/* what page do we start & end in? */
- page_cur = offset / pPrivate->page_size;
- page_end = (offset + count - 1) / pPrivate->page_size;
+ page_cur = offset / private->page_size;
+ page_end = (offset + count - 1) / private->page_size;
LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
/* Handle special case - all one page. */
if (page_cur == page_end) {
LOG_DEBUG("Special case, all in one page");
- r = sam3_page_read(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_read(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
- page_offset = (offset & (pPrivate->page_size-1));
+ page_offset = (offset & (private->page_size-1));
memcpy(pagebuffer + page_offset,
buffer,
count);
- r = sam3_page_write(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_write(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
r = ERROR_OK;
}
/* non-aligned start */
- page_offset = offset & (pPrivate->page_size - 1);
+ page_offset = offset & (private->page_size - 1);
if (page_offset) {
LOG_DEBUG("Not-Aligned start");
/* read the partial */
- r = sam3_page_read(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_read(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
/* over-write with new data */
- n = (pPrivate->page_size - page_offset);
+ n = (private->page_size - page_offset);
memcpy(pagebuffer + page_offset,
buffer,
n);
- r = sam3_page_write(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_write(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
/* By checking that offset is correct here, we also
fix a clang warning */
- assert(offset % pPrivate->page_size == 0);
+ assert(offset % private->page_size == 0);
/* intermediate large pages */
/* also - the final *terminal* */
(int)page_cur, (int)page_end, (unsigned int)(count));
while ((page_cur < page_end) &&
- (count >= pPrivate->page_size)) {
- r = sam3_page_write(pPrivate, page_cur, buffer);
+ (count >= private->page_size)) {
+ r = sam3_page_write(private, page_cur, buffer);
if (r != ERROR_OK)
goto done;
- count -= pPrivate->page_size;
- buffer += pPrivate->page_size;
+ count -= private->page_size;
+ buffer += private->page_size;
page_cur += 1;
}
if (count) {
LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
/* we have a partial page */
- r = sam3_page_read(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_read(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
/* data goes at start */
memcpy(pagebuffer, buffer, count);
- r = sam3_page_write(pPrivate, page_cur, pagebuffer);
+ r = sam3_page_write(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
}
COMMAND_HANDLER(sam3_handle_info_command)
{
- struct sam3_chip *pChip;
- pChip = get_current_sam3(CMD);
- if (!pChip)
+ struct sam3_chip *chip;
+ chip = get_current_sam3(CMD);
+ if (!chip)
return ERROR_OK;
unsigned x;
int r;
/* bank0 must exist before we can do anything */
- if (pChip->details.bank[0].pBank == NULL) {
+ if (chip->details.bank[0].bank == NULL) {
x = 0;
need_define:
command_print(CMD,
}
/* if bank 0 is not probed, then probe it */
- if (!(pChip->details.bank[0].probed)) {
- r = sam3_auto_probe(pChip->details.bank[0].pBank);
+ if (!(chip->details.bank[0].probed)) {
+ r = sam3_auto_probe(chip->details.bank[0].bank);
if (r != ERROR_OK)
return ERROR_FAIL;
}
/* auto-probe other banks, 0 done above */
for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
/* skip banks not present */
- if (!(pChip->details.bank[x].present))
+ if (!(chip->details.bank[x].present))
continue;
- if (pChip->details.bank[x].pBank == NULL)
+ if (chip->details.bank[x].bank == NULL)
goto need_define;
- if (pChip->details.bank[x].probed)
+ if (chip->details.bank[x].probed)
continue;
- r = sam3_auto_probe(pChip->details.bank[x].pBank);
+ r = sam3_auto_probe(chip->details.bank[x].bank);
if (r != ERROR_OK)
return r;
}
- r = sam3_GetInfo(pChip);
+ r = sam3_get_info(chip);
if (r != ERROR_OK) {
LOG_DEBUG("Sam3Info, Failed %d", r);
return r;
{
unsigned x, v;
int r, who;
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
- pChip = get_current_sam3(CMD);
- if (!pChip)
+ chip = get_current_sam3(CMD);
+ if (!chip)
return ERROR_OK;
- if (pChip->target->state != TARGET_HALTED) {
+ if (chip->target->state != TARGET_HALTED) {
LOG_ERROR("sam3 - target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (pChip->details.bank[0].pBank == NULL) {
+ if (chip->details.bank[0].bank == NULL) {
command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
at91sam3_flash.name);
return ERROR_FAIL;
}
- if (!pChip->details.bank[0].probed) {
- r = sam3_auto_probe(pChip->details.bank[0].pBank);
+ if (!chip->details.bank[0].probed) {
+ r = sam3_auto_probe(chip->details.bank[0].bank);
if (r != ERROR_OK)
return r;
}
if (who == -1) {
showall:
r = ERROR_OK;
- for (x = 0; x < pChip->details.n_gpnvms; x++) {
- r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
+ for (x = 0; x < chip->details.n_gpnvms; x++) {
+ r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
if (r != ERROR_OK)
break;
command_print(CMD, "sam3-gpnvm%u: %u", x, v);
}
return r;
}
- if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
- r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
+ if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
+ r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
if (r == ERROR_OK)
command_print(CMD, "sam3-gpnvm%u: %u", who, v);
return r;
}
if (0 == strcmp("set", CMD_ARGV[0]))
- r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
+ r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
(0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
- r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
+ r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
else {
command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
r = ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_HANDLER(sam3_handle_slowclk_command)
{
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
- pChip = get_current_sam3(CMD);
- if (!pChip)
+ chip = get_current_sam3(CMD);
+ if (!chip)
return ERROR_OK;
switch (CMD_ARGC) {
command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
return ERROR_COMMAND_SYNTAX_ERROR;
}
- pChip->cfg.slow_freq = v;
+ chip->cfg.slow_freq = v;
break;
}
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
command_print(CMD, "Slowclk freq: %d.%03dkhz",
- (int)(pChip->cfg.slow_freq / 1000),
- (int)(pChip->cfg.slow_freq % 1000));
+ (int)(chip->cfg.slow_freq / 1000),
+ (int)(chip->cfg.slow_freq % 1000));
return ERROR_OK;
}
#define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
#define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
-#define offset_EFC_FMR 0
-#define offset_EFC_FCR 4
-#define offset_EFC_FSR 8
-#define offset_EFC_FRR 12
+#define OFFSET_EFC_FMR 0
+#define OFFSET_EFC_FCR 4
+#define OFFSET_EFC_FSR 8
+#define OFFSET_EFC_FRR 12
extern const struct flash_driver at91sam4_flash;
/* DANGER: THERE ARE DRAGONS HERE.. */
/* NOTE: If you add more 'ghost' pointers */
/* be aware that you must *manually* update */
- /* these pointers in the function sam4_GetDetails() */
+ /* these pointers in the function sam4_get_details() */
/* See the comment "Here there be dragons" */
/* so we can find the chip we belong to */
- struct sam4_chip *pChip;
+ struct sam4_chip *chip;
/* so we can find the original bank pointer */
- struct flash_bank *pBank;
+ struct flash_bank *bank;
unsigned bank_number;
uint32_t controller_address;
uint32_t base_address;
/* note: If you add pointers here */
/* be careful about them as they */
/* may need to be updated inside */
- /* the function: "sam4_GetDetails() */
+ /* the function: "sam4_get_details() */
/* which copy/overwrites the */
/* 'runtime' copy of this structure */
uint32_t chipid_cidr;
struct sam4_reg_list {
uint32_t address; size_t struct_offset; const char *name;
- void (*explain_func)(struct sam4_chip *pInfo);
+ void (*explain_func)(struct sam4_chip *chip);
};
static struct sam4_chip *all_sam4_chips;
/*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
/*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
-/* these are used to *initialize* the "pChip->details" structure. */
+/* these are used to *initialize* the "chip->details" structure. */
static const struct sam4_chip_details all_sam4_details[] = {
/* Start at91sam4c* series */
/* at91sam4c32e - LQFP144 */
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_C32,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_C32,
.controller_address = 0x400e0c00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_C32,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_C32,
.controller_address = 0x400e0c00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_C,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_C,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_C,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = {*/
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_2048K_SD,
.controller_address = 0x400e0c00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_2048K_SD,
.controller_address = 0x400e0c00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_1024K_SD,
.controller_address = 0x400e0c00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_1024K_SD,
.controller_address = 0x400e0c00,
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/* .bank[0] = */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
/**
* Get the current status of the EEFC and
* the value of some status bits (LOCKE, PROGE).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
+static int efc_get_status(struct sam4_bank_private *private, uint32_t *v)
{
int r;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FSR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FSR,
v);
LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
(unsigned int)(*v),
/**
* Get the result of the last executed command.
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
+static int efc_get_result(struct sam4_bank_private *private, uint32_t *v)
{
int r;
uint32_t rv;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FRR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FRR,
&rv);
if (v)
*v = rv;
return r;
}
-static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
+static int efc_start_command(struct sam4_bank_private *private,
unsigned command, unsigned argument)
{
uint32_t n, v;
case AT91C_EFC_FCMD_EPA:
case AT91C_EFC_FCMD_SLB:
case AT91C_EFC_FCMD_CLB:
- n = (pPrivate->size_bytes / pPrivate->page_size);
+ n = (private->size_bytes / private->page_size);
if (argument >= n)
LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
break;
case AT91C_EFC_FCMD_SFB:
case AT91C_EFC_FCMD_CFB:
- if (argument >= pPrivate->pChip->details.n_gpnvms) {
+ if (argument >= private->chip->details.n_gpnvms) {
LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
- pPrivate->pChip->details.n_gpnvms);
+ private->chip->details.n_gpnvms);
}
break;
/* Situation (2) - normal, finished reading unique id */
} else {
/* it should be "ready" */
- EFC_GetStatus(pPrivate, &v);
+ efc_get_status(private, &v);
if (v & 1) {
/* then it is ready */
/* we go on */
/* we have done this before */
/* the controller is not responding. */
LOG_ERROR("flash controller(%d) is not ready! Error",
- pPrivate->bank_number);
+ private->bank_number);
return ERROR_FAIL;
} else {
retry++;
LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
- pPrivate->bank_number);
+ private->bank_number);
/* we do that by issuing the *STOP* command */
- EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
+ efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
/* above is recursive, and further recursion is blocked by */
/* if (command == AT91C_EFC_FCMD_SPUI) above */
goto do_retry;
v = (0x5A << 24) | (argument << 8) | command;
LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
- r = target_write_u32(pPrivate->pBank->target,
- pPrivate->controller_address + offset_EFC_FCR, v);
+ r = target_write_u32(private->bank->target,
+ private->controller_address + OFFSET_EFC_FCR, v);
if (r != ERROR_OK)
LOG_DEBUG("Error Write failed");
return r;
/**
* Performs the given command and wait until its completion (or an error).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param command - Command to perform.
* @param argument - Optional command argument.
* @param status - put command status bits here
*/
-static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
+static int efc_perform_command(struct sam4_bank_private *private,
unsigned command,
unsigned argument,
uint32_t *status)
if (status)
*status = 0;
- r = EFC_StartCommand(pPrivate, command, argument);
+ r = efc_start_command(private, command, argument);
if (r != ERROR_OK)
return r;
ms_end = 10000 + timeval_ms();
do {
- r = EFC_GetStatus(pPrivate, &v);
+ r = efc_get_status(private, &v);
if (r != ERROR_OK)
return r;
ms_now = timeval_ms();
/**
* Read the unique ID.
- * @param pPrivate - info about the bank
- * The unique ID is stored in the 'pPrivate' structure.
+ * @param private - info about the bank
+ * The unique ID is stored in the 'private' structure.
*/
-static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
+static int flashd_read_uid(struct sam4_bank_private *private)
{
int r;
uint32_t v;
int x;
/* assume 0 */
- pPrivate->pChip->cfg.unique_id[0] = 0;
- pPrivate->pChip->cfg.unique_id[1] = 0;
- pPrivate->pChip->cfg.unique_id[2] = 0;
- pPrivate->pChip->cfg.unique_id[3] = 0;
+ private->chip->cfg.unique_id[0] = 0;
+ private->chip->cfg.unique_id[1] = 0;
+ private->chip->cfg.unique_id[2] = 0;
+ private->chip->cfg.unique_id[3] = 0;
LOG_DEBUG("Begin");
- r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
+ r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
if (r < 0)
return r;
for (x = 0; x < 4; x++) {
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->pBank->base + (x * 4),
+ r = target_read_u32(private->chip->target,
+ private->bank->base + (x * 4),
&v);
if (r < 0)
return r;
- pPrivate->pChip->cfg.unique_id[x] = v;
+ private->chip->cfg.unique_id[x] = v;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
r,
- (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
+ (unsigned int)(private->chip->cfg.unique_id[0]),
+ (unsigned int)(private->chip->cfg.unique_id[1]),
+ (unsigned int)(private->chip->cfg.unique_id[2]),
+ (unsigned int)(private->chip->cfg.unique_id[3]));
return r;
}
/**
* Erases the entire flash.
- * @param pPrivate - the info about the bank.
+ * @param private - the info about the bank.
*/
-static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
+static int flashd_erase_entire_bank(struct sam4_bank_private *private)
{
LOG_DEBUG("Here");
- return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
+ return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
}
/**
* Erases the entire flash.
- * @param pPrivate - the info about the bank.
- * @param firstPage
- * @param numPages
+ * @param private - the info about the bank.
+ * @param first_page
+ * @param num_pages
* @param status
*/
-static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
- int firstPage,
- int numPages,
+static int flashd_erase_pages(struct sam4_bank_private *private,
+ int first_page,
+ int num_pages,
uint32_t *status)
{
LOG_DEBUG("Here");
- uint8_t erasePages;
- switch (numPages) {
+ uint8_t erase_pages;
+ switch (num_pages) {
case 4:
- erasePages = 0x00;
+ erase_pages = 0x00;
break;
case 8:
- erasePages = 0x01;
+ erase_pages = 0x01;
break;
case 16:
- erasePages = 0x02;
+ erase_pages = 0x02;
break;
case 32:
- erasePages = 0x03;
+ erase_pages = 0x03;
break;
default:
- erasePages = 0x00;
+ erase_pages = 0x00;
break;
}
* number of pages to be erased. Previously (firstpage << 2) was used
* to conform to this, seems it should not be shifted...
*/
- return EFC_PerformCommand(pPrivate,
+ return efc_perform_command(private,
/* send Erase Page */
AT91C_EFC_FCMD_EPA,
- (firstPage) | erasePages,
+ (first_page) | erase_pages,
status);
}
/**
* Gets current GPNVM state.
- * @param pPrivate - info about the bank.
+ * @param private - info about the bank.
* @param gpnvm - GPNVM bit index.
* @param puthere - result stored here.
*/
/* ------------------------------------------------------------------------------ */
-static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
+static int flashd_get_gpnvm(struct sam4_bank_private *private, unsigned gpnvm, unsigned *puthere)
{
uint32_t v;
int r;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
/* Get GPNVMs status */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
if (r != ERROR_OK) {
LOG_ERROR("Failed");
return r;
}
- r = EFC_GetResult(pPrivate, &v);
+ r = efc_get_result(private, &v);
if (puthere) {
/* Check if GPNVM is set */
/**
* Clears the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
* @returns 0 if successful; otherwise returns an error code.
*/
-static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_clr_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK) {
LOG_DEBUG("Failed: %d", r);
return r;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
LOG_DEBUG("End: %d", r);
return r;
}
/**
* Sets the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
*/
-static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_set_gpnvm(struct sam4_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK)
return r;
if (v) {
r = ERROR_OK;
} else {
/* set it */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
}
return r;
}
/**
* Returns a bit field (at most 64) of locked regions within a page.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param v where to store locked bits
*/
-static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
+static int flashd_get_lock_bits(struct sam4_bank_private *private, uint32_t *v)
{
int r;
LOG_DEBUG("Here");
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
if (r == ERROR_OK) {
- EFC_GetResult(pPrivate, v);
- EFC_GetResult(pPrivate, v);
- EFC_GetResult(pPrivate, v);
- r = EFC_GetResult(pPrivate, v);
+ efc_get_result(private, v);
+ efc_get_result(private, v);
+ efc_get_result(private, v);
+ r = efc_get_result(private, v);
}
LOG_DEBUG("End: %d", r);
return r;
/**
* Unlocks all the regions in the given address range.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param start_sector first sector to unlock
* @param end_sector last (inclusive) to unlock
*/
-static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
+static int flashd_unlock(struct sam4_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
uint32_t pg;
uint32_t pages_per_sector;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Unlock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
/**
* Locks regions
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param start_sector - first sector to lock
* @param end_sector - last sector (inclusive) to lock
*/
-static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
+static int flashd_lock(struct sam4_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
uint32_t pages_per_sector;
int r;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Lock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
/* begin helpful debug code */
/* print the fieldname, the field value, in dec & hex, and return field value */
-static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
+static uint32_t sam4_reg_fieldname(struct sam4_chip *chip,
const char *regname,
uint32_t value,
unsigned shift,
"4 MHz", "8 MHz", "12 MHz", "reserved"
};
-static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
+static void sam4_explain_ckgr_mor(struct sam4_chip *chip)
{
uint32_t v;
uint32_t rcen;
- v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
+ v = sam4_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
- v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
+ v = sam4_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
- rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
+ rcen = sam4_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
- v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
+ v = sam4_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
if (rcen) {
switch (v) {
default:
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
break;
case 0:
- pChip->cfg.rc_freq = 4 * 1000 * 1000;
+ chip->cfg.rc_freq = 4 * 1000 * 1000;
break;
case 1:
- pChip->cfg.rc_freq = 8 * 1000 * 1000;
+ chip->cfg.rc_freq = 8 * 1000 * 1000;
break;
case 2:
- pChip->cfg.rc_freq = 12 * 1000 * 1000;
+ chip->cfg.rc_freq = 12 * 1000 * 1000;
break;
}
}
- v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
+ v = sam4_reg_fieldname(chip, "MOSCXTST", chip->cfg.CKGR_MOR, 8, 8);
LOG_USER("(startup clks, time= %f uSecs)",
- ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
- v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
+ ((float)(v * 1000000)) / ((float)(chip->cfg.slow_freq)));
+ v = sam4_reg_fieldname(chip, "MOSCSEL", chip->cfg.CKGR_MOR, 24, 1);
LOG_USER("(mainosc source: %s)",
v ? "external xtal" : "internal RC");
- v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
+ v = sam4_reg_fieldname(chip, "CFDEN", chip->cfg.CKGR_MOR, 25, 1);
LOG_USER("(clock failure enabled: %s)",
_yes_or_no(v));
}
-static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
+static void sam4_explain_chipid_cidr(struct sam4_chip *chip)
{
int x;
uint32_t v;
const char *cp;
- sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
+ sam4_reg_fieldname(chip, "Version", chip->cfg.CHIPID_CIDR, 0, 5);
LOG_USER_N("\n");
- v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
+ v = sam4_reg_fieldname(chip, "EPROC", chip->cfg.CHIPID_CIDR, 5, 3);
LOG_USER("%s", eproc_names[v]);
- v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
+ v = sam4_reg_fieldname(chip, "NVPSIZE", chip->cfg.CHIPID_CIDR, 8, 4);
LOG_USER("%s", nvpsize[v]);
- v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
+ v = sam4_reg_fieldname(chip, "NVPSIZE2", chip->cfg.CHIPID_CIDR, 12, 4);
LOG_USER("%s", nvpsize2[v]);
- v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
+ v = sam4_reg_fieldname(chip, "SRAMSIZE", chip->cfg.CHIPID_CIDR, 16, 4);
LOG_USER("%s", sramsize[v]);
- v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
+ v = sam4_reg_fieldname(chip, "ARCH", chip->cfg.CHIPID_CIDR, 20, 8);
cp = _unknown;
for (x = 0; archnames[x].name; x++) {
if (v == archnames[x].value) {
LOG_USER("%s", cp);
- v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
+ v = sam4_reg_fieldname(chip, "NVPTYP", chip->cfg.CHIPID_CIDR, 28, 3);
LOG_USER("%s", nvptype[v]);
- v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
+ v = sam4_reg_fieldname(chip, "EXTID", chip->cfg.CHIPID_CIDR, 31, 1);
LOG_USER("(exists: %s)", _yes_or_no(v));
}
-static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
+static void sam4_explain_ckgr_mcfr(struct sam4_chip *chip)
{
uint32_t v;
- v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
+ v = sam4_reg_fieldname(chip, "MAINFRDY", chip->cfg.CKGR_MCFR, 16, 1);
LOG_USER("(main ready: %s)", _yes_or_no(v));
- v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
+ v = sam4_reg_fieldname(chip, "MAINF", chip->cfg.CKGR_MCFR, 0, 16);
- v = (v * pChip->cfg.slow_freq) / 16;
- pChip->cfg.mainosc_freq = v;
+ v = (v * chip->cfg.slow_freq) / 16;
+ chip->cfg.mainosc_freq = v;
LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
_tomhz(v),
- (uint32_t)(pChip->cfg.slow_freq / 1000),
- (uint32_t)(pChip->cfg.slow_freq % 1000));
+ (uint32_t)(chip->cfg.slow_freq / 1000),
+ (uint32_t)(chip->cfg.slow_freq % 1000));
}
-static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
+static void sam4_explain_ckgr_plla(struct sam4_chip *chip)
{
uint32_t mula, diva;
- diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
+ diva = sam4_reg_fieldname(chip, "DIVA", chip->cfg.CKGR_PLLAR, 0, 8);
LOG_USER_N("\n");
- mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
+ mula = sam4_reg_fieldname(chip, "MULA", chip->cfg.CKGR_PLLAR, 16, 11);
LOG_USER_N("\n");
- pChip->cfg.plla_freq = 0;
+ chip->cfg.plla_freq = 0;
if (mula == 0)
LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
else if (diva == 0)
LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
else if (diva >= 1) {
- pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
+ chip->cfg.plla_freq = (chip->cfg.mainosc_freq * (mula + 1) / diva);
LOG_USER("\tPLLA Freq: %3.03f MHz",
- _tomhz(pChip->cfg.plla_freq));
+ _tomhz(chip->cfg.plla_freq));
}
}
-static void sam4_explain_mckr(struct sam4_chip *pChip)
+static void sam4_explain_mckr(struct sam4_chip *chip)
{
uint32_t css, pres, fin = 0;
int pdiv = 0;
const char *cp = NULL;
- css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
+ css = sam4_reg_fieldname(chip, "CSS", chip->cfg.PMC_MCKR, 0, 2);
switch (css & 3) {
case 0:
- fin = pChip->cfg.slow_freq;
+ fin = chip->cfg.slow_freq;
cp = "slowclk";
break;
case 1:
- fin = pChip->cfg.mainosc_freq;
+ fin = chip->cfg.mainosc_freq;
cp = "mainosc";
break;
case 2:
- fin = pChip->cfg.plla_freq;
+ fin = chip->cfg.plla_freq;
cp = "plla";
break;
case 3:
- if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
+ if (chip->cfg.CKGR_UCKR & (1 << 16)) {
fin = 480 * 1000 * 1000;
cp = "upll";
} else {
LOG_USER("%s (%3.03f Mhz)",
cp,
_tomhz(fin));
- pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
+ pres = sam4_reg_fieldname(chip, "PRES", chip->cfg.PMC_MCKR, 4, 3);
switch (pres & 0x07) {
case 0:
pdiv = 1;
fin = fin / pdiv;
/* sam4 has a *SINGLE* clock - */
/* other at91 series parts have divisors for these. */
- pChip->cfg.cpu_freq = fin;
- pChip->cfg.mclk_freq = fin;
- pChip->cfg.fclk_freq = fin;
+ chip->cfg.cpu_freq = fin;
+ chip->cfg.mclk_freq = fin;
+ chip->cfg.fclk_freq = fin;
LOG_USER("\t\tResult CPU Freq: %3.03f",
_tomhz(fin));
}
#if 0
-static struct sam4_chip *target2sam4(struct target *pTarget)
+static struct sam4_chip *target2sam4(struct target *target)
{
- struct sam4_chip *pChip;
+ struct sam4_chip *chip;
- if (pTarget == NULL)
+ if (target == NULL)
return NULL;
- pChip = all_sam4_chips;
- while (pChip) {
- if (pChip->target == pTarget)
+ chip = all_sam4_chips;
+ while (chip) {
+ if (chip->target == target)
break; /* return below */
else
- pChip = pChip->next;
+ chip = chip->next;
}
- return pChip;
+ return chip;
}
#endif
-static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
+static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *cfg, const struct sam4_reg_list *list)
{
/* this function exists to help */
/* keep funky offsetof() errors */
/* By using prototypes - we can detect what would */
/* be casting errors. */
- return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
+ return (uint32_t *)(void *)(((char *)(cfg)) + list->struct_offset);
}
* Given a pointer to where it goes in the structure,
* determine the register name, address from the all registers table.
*/
-static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
+static const struct sam4_reg_list *sam4_get_reg(struct sam4_chip *chip, uint32_t *goes_here)
{
- const struct sam4_reg_list *pReg;
+ const struct sam4_reg_list *reg;
- pReg = &(sam4_all_regs[0]);
- while (pReg->name) {
- uint32_t *pPossible;
+ reg = &(sam4_all_regs[0]);
+ while (reg->name) {
+ uint32_t *possible;
/* calculate where this one go.. */
/* it is "possibly" this register. */
- pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
+ possible = ((uint32_t *)(void *)(((char *)(&(chip->cfg))) + reg->struct_offset));
/* well? Is it this register */
- if (pPossible == goes_here) {
+ if (possible == goes_here) {
/* Jump for joy! */
- return pReg;
+ return reg;
}
/* next... */
- pReg++;
+ reg++;
}
/* This is *TOTAL*PANIC* - we are totally screwed. */
LOG_ERROR("INVALID SAM4 REGISTER");
return NULL;
}
-static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
+static int sam4_read_this_reg(struct sam4_chip *chip, uint32_t *goes_here)
{
- const struct sam4_reg_list *pReg;
+ const struct sam4_reg_list *reg;
int r;
- pReg = sam4_GetReg(pChip, goes_here);
- if (!pReg)
+ reg = sam4_get_reg(chip, goes_here);
+ if (!reg)
return ERROR_FAIL;
- r = target_read_u32(pChip->target, pReg->address, goes_here);
+ r = target_read_u32(chip->target, reg->address, goes_here);
if (r != ERROR_OK) {
LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
- pReg->name, (unsigned)(pReg->address), r);
+ reg->name, (unsigned)(reg->address), r);
}
return r;
}
-static int sam4_ReadAllRegs(struct sam4_chip *pChip)
+static int sam4_read_all_regs(struct sam4_chip *chip)
{
int r;
- const struct sam4_reg_list *pReg;
+ const struct sam4_reg_list *reg;
- pReg = &(sam4_all_regs[0]);
- while (pReg->name) {
- r = sam4_ReadThisReg(pChip,
- sam4_get_reg_ptr(&(pChip->cfg), pReg));
+ reg = &(sam4_all_regs[0]);
+ while (reg->name) {
+ r = sam4_read_this_reg(chip,
+ sam4_get_reg_ptr(&(chip->cfg), reg));
if (r != ERROR_OK) {
LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
- pReg->name, ((unsigned)(pReg->address)), r);
+ reg->name, ((unsigned)(reg->address)), r);
return r;
}
- pReg++;
+ reg++;
}
return ERROR_OK;
}
-static int sam4_GetInfo(struct sam4_chip *pChip)
+static int sam4_get_info(struct sam4_chip *chip)
{
- const struct sam4_reg_list *pReg;
+ const struct sam4_reg_list *reg;
uint32_t regval;
int r;
- r = sam4_ReadAllRegs(pChip);
+ r = sam4_read_all_regs(chip);
if (r != ERROR_OK)
return r;
- pReg = &(sam4_all_regs[0]);
- while (pReg->name) {
+ reg = &(sam4_all_regs[0]);
+ while (reg->name) {
/* display all regs */
- LOG_DEBUG("Start: %s", pReg->name);
- regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
+ LOG_DEBUG("Start: %s", reg->name);
+ regval = *sam4_get_reg_ptr(&(chip->cfg), reg);
LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
REG_NAME_WIDTH,
- pReg->name,
- pReg->address,
+ reg->name,
+ reg->address,
regval);
- if (pReg->explain_func)
- (*(pReg->explain_func))(pChip);
- LOG_DEBUG("End: %s", pReg->name);
- pReg++;
+ if (reg->explain_func)
+ (*(reg->explain_func))(chip);
+ LOG_DEBUG("End: %s", reg->name);
+ reg++;
}
- LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
- LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
- LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
- LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
- LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
+ LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip->cfg.rc_freq));
+ LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip->cfg.mainosc_freq));
+ LOG_USER(" plla: %3.03f MHz", _tomhz(chip->cfg.plla_freq));
+ LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip->cfg.cpu_freq));
+ LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip->cfg.mclk_freq));
LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
- pChip->cfg.unique_id[0],
- pChip->cfg.unique_id[1],
- pChip->cfg.unique_id[2],
- pChip->cfg.unique_id[3]);
+ chip->cfg.unique_id[0],
+ chip->cfg.unique_id[1],
+ chip->cfg.unique_id[2],
+ chip->cfg.unique_id[3]);
return ERROR_OK;
}
int r;
uint32_t v[4] = {0};
unsigned x;
- struct sam4_bank_private *pPrivate;
+ struct sam4_bank_private *private;
LOG_DEBUG("Begin");
if (bank->target->state != TARGET_HALTED) {
return ERROR_TARGET_NOT_HALTED;
}
- pPrivate = get_sam4_bank_private(bank);
- if (!pPrivate) {
+ private = get_sam4_bank_private(bank);
+ if (!private) {
LOG_ERROR("no private for this bank?");
return ERROR_FAIL;
}
- if (!(pPrivate->probed))
+ if (!(private->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
- r = FLASHD_GetLockBits(pPrivate, v);
+ r = flashd_get_lock_bits(private, v);
if (r != ERROR_OK) {
LOG_DEBUG("Failed: %d", r);
return r;
}
- for (x = 0; x < pPrivate->nsectors; x++)
+ for (x = 0; x < private->nsectors; x++)
bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
LOG_DEBUG("Done");
return ERROR_OK;
FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
{
- struct sam4_chip *pChip;
+ struct sam4_chip *chip;
- pChip = all_sam4_chips;
+ chip = all_sam4_chips;
/* is this an existing chip? */
- while (pChip) {
- if (pChip->target == bank->target)
+ while (chip) {
+ if (chip->target == bank->target)
break;
- pChip = pChip->next;
+ chip = chip->next;
}
- if (!pChip) {
+ if (!chip) {
/* this is a *NEW* chip */
- pChip = calloc(1, sizeof(struct sam4_chip));
- if (!pChip) {
+ chip = calloc(1, sizeof(struct sam4_chip));
+ if (!chip) {
LOG_ERROR("NO RAM!");
return ERROR_FAIL;
}
- pChip->target = bank->target;
+ chip->target = bank->target;
/* insert at head */
- pChip->next = all_sam4_chips;
- all_sam4_chips = pChip;
- pChip->target = bank->target;
+ chip->next = all_sam4_chips;
+ all_sam4_chips = chip;
+ chip->target = bank->target;
/* assumption is this runs at 32khz */
- pChip->cfg.slow_freq = 32768;
- pChip->probed = false;
+ chip->cfg.slow_freq = 32768;
+ chip->probed = false;
}
switch (bank->base) {
/* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
case FLASH_BANK_BASE_S:
case FLASH_BANK_BASE_C:
- bank->driver_priv = &(pChip->details.bank[0]);
+ bank->driver_priv = &(chip->details.bank[0]);
bank->bank_number = 0;
- pChip->details.bank[0].pChip = pChip;
- pChip->details.bank[0].pBank = bank;
+ chip->details.bank[0].chip = chip;
+ chip->details.bank[0].bank = bank;
break;
/* Bank 1 of at91sam4sd/at91sam4c32 series */
case FLASH_BANK1_BASE_1024K_SD:
case FLASH_BANK1_BASE_2048K_SD:
case FLASH_BANK1_BASE_C32:
- bank->driver_priv = &(pChip->details.bank[1]);
+ bank->driver_priv = &(chip->details.bank[1]);
bank->bank_number = 1;
- pChip->details.bank[1].pChip = pChip;
- pChip->details.bank[1].pBank = bank;
+ chip->details.bank[1].chip = chip;
+ chip->details.bank[1].bank = bank;
break;
}
all_sam4_chips = NULL;
}
-static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
+static int sam4_get_details(struct sam4_bank_private *private)
{
- const struct sam4_chip_details *pDetails;
- struct sam4_chip *pChip;
+ const struct sam4_chip_details *details;
+ struct sam4_chip *chip;
struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
unsigned x;
LOG_DEBUG("Begin");
- pDetails = all_sam4_details;
- while (pDetails->name) {
+ details = all_sam4_details;
+ while (details->name) {
/* Compare cidr without version bits */
- if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
+ if (details->chipid_cidr == (private->chip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
break;
else
- pDetails++;
+ details++;
}
- if (pDetails->name == NULL) {
+ if (details->name == NULL) {
LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
- (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
+ (unsigned int)(private->chip->cfg.CHIPID_CIDR));
/* Help the victim, print details about the chip */
LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
- pPrivate->pChip->cfg.CHIPID_CIDR);
- sam4_explain_chipid_cidr(pPrivate->pChip);
+ private->chip->cfg.CHIPID_CIDR);
+ sam4_explain_chipid_cidr(private->chip);
return ERROR_FAIL;
} else {
- LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, pDetails->name, pDetails->chipid_cidr);
+ LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, details->name, details->chipid_cidr);
}
/* DANGER: THERE ARE DRAGONS HERE */
- /* get our pChip - it is going */
+ /* get our chip - it is going */
/* to be over-written shortly */
- pChip = pPrivate->pChip;
+ chip = private->chip;
/* Note that, in reality: */
/* */
- /* pPrivate = &(pChip->details.bank[0]) */
- /* or pPrivate = &(pChip->details.bank[1]) */
+ /* private = &(chip->details.bank[0]) */
+ /* or private = &(chip->details.bank[1]) */
/* */
/* save the "bank" pointers */
for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
- saved_banks[x] = pChip->details.bank[x].pBank;
+ saved_banks[x] = chip->details.bank[x].bank;
/* Overwrite the "details" structure. */
- memcpy(&(pPrivate->pChip->details),
- pDetails,
- sizeof(pPrivate->pChip->details));
+ memcpy(&(private->chip->details),
+ details,
+ sizeof(private->chip->details));
/* now fix the ghosted pointers */
for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
- pChip->details.bank[x].pChip = pChip;
- pChip->details.bank[x].pBank = saved_banks[x];
+ chip->details.bank[x].chip = chip;
+ chip->details.bank[x].bank = saved_banks[x];
}
/* update the *BANK*SIZE* */
static int sam4_info(struct flash_bank *bank, struct command_invocation *cmd)
{
- struct sam4_bank_private *pPrivate;
+ struct sam4_bank_private *private;
int k = bank->size / 1024;
- pPrivate = get_sam4_bank_private(bank);
- if (pPrivate == NULL)
+ private = get_sam4_bank_private(bank);
+ if (private == NULL)
return ERROR_FAIL;
command_print_sameline(cmd, "%s bank %d: %d kB at " TARGET_ADDR_FMT,
- pPrivate->pChip->details.name,
- pPrivate->bank_number,
+ private->chip->details.name,
+ private->bank_number,
k,
bank->base);
static int sam4_probe(struct flash_bank *bank)
{
int r;
- struct sam4_bank_private *pPrivate;
+ struct sam4_bank_private *private;
LOG_DEBUG("Begin: Bank: %u", bank->bank_number);
return ERROR_TARGET_NOT_HALTED;
}
- pPrivate = get_sam4_bank_private(bank);
- if (!pPrivate) {
+ private = get_sam4_bank_private(bank);
+ if (!private) {
LOG_ERROR("Invalid/unknown bank number");
return ERROR_FAIL;
}
- r = sam4_ReadAllRegs(pPrivate->pChip);
+ r = sam4_read_all_regs(private->chip);
if (r != ERROR_OK)
return r;
LOG_DEBUG("Here");
- if (pPrivate->pChip->probed)
- r = sam4_GetInfo(pPrivate->pChip);
+ if (private->chip->probed)
+ r = sam4_get_info(private->chip);
else
- r = sam4_GetDetails(pPrivate);
+ r = sam4_get_details(private);
if (r != ERROR_OK)
return r;
/* update the flash bank size */
for (unsigned int x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
- if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
- bank->size = pPrivate->pChip->details.bank[x].size_bytes;
+ if (bank->base == private->chip->details.bank[x].base_address) {
+ bank->size = private->chip->details.bank[x].size_bytes;
LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
TARGET_ADDR_FMT ", idx %d", bank->base,
bank->base + bank->size, x);
}
if (bank->sectors == NULL) {
- bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
+ bank->sectors = calloc(private->nsectors, (sizeof((bank->sectors)[0])));
if (bank->sectors == NULL) {
LOG_ERROR("No memory!");
return ERROR_FAIL;
}
- bank->num_sectors = pPrivate->nsectors;
+ bank->num_sectors = private->nsectors;
for (unsigned int x = 0; x < bank->num_sectors; x++) {
- bank->sectors[x].size = pPrivate->sector_size;
- bank->sectors[x].offset = x * (pPrivate->sector_size);
+ bank->sectors[x].size = private->sector_size;
+ bank->sectors[x].offset = x * (private->sector_size);
/* mark as unknown */
bank->sectors[x].is_erased = -1;
bank->sectors[x].is_protected = -1;
}
}
- pPrivate->probed = true;
+ private->probed = true;
r = sam4_protect_check(bank);
if (r != ERROR_OK)
return r;
LOG_DEBUG("Bank = %d, nbanks = %d",
- pPrivate->bank_number, pPrivate->pChip->details.n_banks);
- if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
+ private->bank_number, private->chip->details.n_banks);
+ if ((private->bank_number + 1) == private->chip->details.n_banks) {
/* read unique id, */
/* it appears to be associated with the *last* flash bank. */
- FLASHD_ReadUniqueID(pPrivate);
+ flashd_read_uid(private);
}
return r;
static int sam4_auto_probe(struct flash_bank *bank)
{
- struct sam4_bank_private *pPrivate;
+ struct sam4_bank_private *private;
- pPrivate = get_sam4_bank_private(bank);
- if (pPrivate && pPrivate->probed)
+ private = get_sam4_bank_private(bank);
+ if (private && private->probed)
return ERROR_OK;
return sam4_probe(bank);
static int sam4_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
{
- struct sam4_bank_private *pPrivate;
+ struct sam4_bank_private *private;
int r;
- int pageCount;
+ int page_count;
/*16 pages equals 8KB - Same size as a lock region*/
- pageCount = 16;
+ page_count = 16;
uint32_t status;
LOG_DEBUG("Here");
return r;
}
- pPrivate = get_sam4_bank_private(bank);
- if (!(pPrivate->probed))
+ private = get_sam4_bank_private(bank);
+ if (!(private->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
- if ((first == 0) && ((last + 1) == pPrivate->nsectors)) {
+ if ((first == 0) && ((last + 1) == private->nsectors)) {
/* whole chip */
LOG_DEBUG("Here");
- return FLASHD_EraseEntireBank(pPrivate);
+ return flashd_erase_entire_bank(private);
}
LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", first, last);
for (unsigned int i = first; i <= last; i++) {
/*16 pages equals 8KB - Same size as a lock region*/
- r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
+ r = flashd_erase_pages(private, (i * page_count), page_count, &status);
LOG_INFO("Erasing sector: 0x%08x", i);
if (r != ERROR_OK)
LOG_ERROR("SAM4: Error performing Erase page @ lock region number %u",
static int sam4_protect(struct flash_bank *bank, int set, unsigned int first,
unsigned int last)
{
- struct sam4_bank_private *pPrivate;
+ struct sam4_bank_private *private;
int r;
LOG_DEBUG("Here");
return ERROR_TARGET_NOT_HALTED;
}
- pPrivate = get_sam4_bank_private(bank);
- if (!(pPrivate->probed))
+ private = get_sam4_bank_private(bank);
+ if (!(private->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
if (set)
- r = FLASHD_Lock(pPrivate, first, last);
+ r = flashd_lock(private, first, last);
else
- r = FLASHD_Unlock(pPrivate, first, last);
+ r = flashd_unlock(private, first, last);
LOG_DEBUG("End: r=%d", r);
return r;
}
-static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
+static int sam4_page_read(struct sam4_bank_private *private, unsigned pagenum, uint8_t *buf)
{
uint32_t adr;
int r;
- adr = pagenum * pPrivate->page_size;
- adr = adr + pPrivate->base_address;
+ adr = pagenum * private->page_size;
+ adr = adr + private->base_address;
- r = target_read_memory(pPrivate->pChip->target,
+ r = target_read_memory(private->chip->target,
adr,
4, /* THIS*MUST*BE* in 32bit values */
- pPrivate->page_size / 4,
+ private->page_size / 4,
buf);
if (r != ERROR_OK)
LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
return r;
}
-static int sam4_set_wait(struct sam4_bank_private *pPrivate)
+static int sam4_set_wait(struct sam4_bank_private *private)
{
uint32_t fmr; /* EEFC Flash Mode Register */
int r;
/* Get flash mode register value */
- r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
+ r = target_read_u32(private->chip->target, private->controller_address, &fmr);
if (r != ERROR_OK) {
LOG_ERROR("Error Read failed: read flash mode register");
return r;
fmr &= 0xfffff0ff;
/* set FWS (flash wait states) field in the FMR (flash mode register) */
- fmr |= (pPrivate->flash_wait_states << 8);
+ fmr |= (private->flash_wait_states << 8);
LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
- r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
+ r = target_write_u32(private->bank->target, private->controller_address, fmr);
if (r != ERROR_OK)
LOG_ERROR("Error Write failed: set flash mode register");
return r;
}
-static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
+static int sam4_page_write(struct sam4_bank_private *private, unsigned pagenum, const uint8_t *buf)
{
uint32_t adr;
uint32_t status;
int r;
- adr = pagenum * pPrivate->page_size;
- adr = (adr + pPrivate->base_address);
+ adr = pagenum * private->page_size;
+ adr = (adr + private->base_address);
/* 1st sector 8kBytes - page 0 - 15*/
/* 2nd sector 8kBytes - page 16 - 30*/
/* 3rd sector 48kBytes - page 31 - 127*/
LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
- r = target_write_memory(pPrivate->pChip->target,
+ r = target_write_memory(private->chip->target,
adr,
4, /* THIS*MUST*BE* in 32bit values */
- pPrivate->page_size / 4,
+ private->page_size / 4,
buf);
if (r != ERROR_OK) {
LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
return r;
}
- r = EFC_PerformCommand(pPrivate,
+ r = efc_perform_command(private,
/* send Erase & Write Page */
AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
pagenum,
unsigned page_end;
int r;
unsigned page_offset;
- struct sam4_bank_private *pPrivate;
+ struct sam4_bank_private *private;
uint8_t *pagebuffer;
/* in case we bail further below, set this to null */
goto done;
}
- pPrivate = get_sam4_bank_private(bank);
- if (!(pPrivate->probed)) {
+ private = get_sam4_bank_private(bank);
+ if (!(private->probed)) {
r = ERROR_FLASH_BANK_NOT_PROBED;
goto done;
}
- if ((offset + count) > pPrivate->size_bytes) {
+ if ((offset + count) > private->size_bytes) {
LOG_ERROR("Flash write error - past end of bank");
LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
(unsigned int)(offset),
(unsigned int)(count),
- (unsigned int)(pPrivate->size_bytes));
+ (unsigned int)(private->size_bytes));
r = ERROR_FAIL;
goto done;
}
- pagebuffer = malloc(pPrivate->page_size);
+ pagebuffer = malloc(private->page_size);
if (!pagebuffer) {
- LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
+ LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size));
r = ERROR_FAIL;
goto done;
}
- r = sam4_set_wait(pPrivate);
+ r = sam4_set_wait(private);
if (r != ERROR_OK)
goto done;
/* what page do we start & end in? */
- page_cur = offset / pPrivate->page_size;
- page_end = (offset + count - 1) / pPrivate->page_size;
+ page_cur = offset / private->page_size;
+ page_end = (offset + count - 1) / private->page_size;
LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
/* Handle special case - all one page. */
if (page_cur == page_end) {
LOG_DEBUG("Special case, all in one page");
- r = sam4_page_read(pPrivate, page_cur, pagebuffer);
+ r = sam4_page_read(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
- page_offset = (offset & (pPrivate->page_size-1));
+ page_offset = (offset & (private->page_size-1));
memcpy(pagebuffer + page_offset,
buffer,
count);
- r = sam4_page_write(pPrivate, page_cur, pagebuffer);
+ r = sam4_page_write(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
r = ERROR_OK;
}
/* non-aligned start */
- page_offset = offset & (pPrivate->page_size - 1);
+ page_offset = offset & (private->page_size - 1);
if (page_offset) {
LOG_DEBUG("Not-Aligned start");
/* read the partial */
- r = sam4_page_read(pPrivate, page_cur, pagebuffer);
+ r = sam4_page_read(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
/* over-write with new data */
- n = (pPrivate->page_size - page_offset);
+ n = (private->page_size - page_offset);
memcpy(pagebuffer + page_offset,
buffer,
n);
- r = sam4_page_write(pPrivate, page_cur, pagebuffer);
+ r = sam4_page_write(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
/* By checking that offset is correct here, we also
fix a clang warning */
- assert(offset % pPrivate->page_size == 0);
+ assert(offset % private->page_size == 0);
/* intermediate large pages */
/* also - the final *terminal* */
(int)page_cur, (int)page_end, (unsigned int)(count));
while ((page_cur < page_end) &&
- (count >= pPrivate->page_size)) {
- r = sam4_page_write(pPrivate, page_cur, buffer);
+ (count >= private->page_size)) {
+ r = sam4_page_write(private, page_cur, buffer);
if (r != ERROR_OK)
goto done;
- count -= pPrivate->page_size;
- buffer += pPrivate->page_size;
+ count -= private->page_size;
+ buffer += private->page_size;
page_cur += 1;
}
if (count) {
LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
/* we have a partial page */
- r = sam4_page_read(pPrivate, page_cur, pagebuffer);
+ r = sam4_page_read(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
/* data goes at start */
memcpy(pagebuffer, buffer, count);
- r = sam4_page_write(pPrivate, page_cur, pagebuffer);
+ r = sam4_page_write(private, page_cur, pagebuffer);
if (r != ERROR_OK)
goto done;
}
COMMAND_HANDLER(sam4_handle_info_command)
{
- struct sam4_chip *pChip;
- pChip = get_current_sam4(CMD);
- if (!pChip)
+ struct sam4_chip *chip;
+ chip = get_current_sam4(CMD);
+ if (!chip)
return ERROR_OK;
unsigned x;
int r;
/* bank0 must exist before we can do anything */
- if (pChip->details.bank[0].pBank == NULL) {
+ if (chip->details.bank[0].bank == NULL) {
x = 0;
need_define:
command_print(CMD,
}
/* if bank 0 is not probed, then probe it */
- if (!(pChip->details.bank[0].probed)) {
- r = sam4_auto_probe(pChip->details.bank[0].pBank);
+ if (!(chip->details.bank[0].probed)) {
+ r = sam4_auto_probe(chip->details.bank[0].bank);
if (r != ERROR_OK)
return ERROR_FAIL;
}
/* auto-probe other banks, 0 done above */
for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
/* skip banks not present */
- if (!(pChip->details.bank[x].present))
+ if (!(chip->details.bank[x].present))
continue;
- if (pChip->details.bank[x].pBank == NULL)
+ if (chip->details.bank[x].bank == NULL)
goto need_define;
- if (pChip->details.bank[x].probed)
+ if (chip->details.bank[x].probed)
continue;
- r = sam4_auto_probe(pChip->details.bank[x].pBank);
+ r = sam4_auto_probe(chip->details.bank[x].bank);
if (r != ERROR_OK)
return r;
}
- r = sam4_GetInfo(pChip);
+ r = sam4_get_info(chip);
if (r != ERROR_OK) {
LOG_DEBUG("Sam4Info, Failed %d", r);
return r;
{
unsigned x, v;
int r, who;
- struct sam4_chip *pChip;
+ struct sam4_chip *chip;
- pChip = get_current_sam4(CMD);
- if (!pChip)
+ chip = get_current_sam4(CMD);
+ if (!chip)
return ERROR_OK;
- if (pChip->target->state != TARGET_HALTED) {
+ if (chip->target->state != TARGET_HALTED) {
LOG_ERROR("sam4 - target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (pChip->details.bank[0].pBank == NULL) {
+ if (chip->details.bank[0].bank == NULL) {
command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
at91sam4_flash.name);
return ERROR_FAIL;
}
- if (!pChip->details.bank[0].probed) {
- r = sam4_auto_probe(pChip->details.bank[0].pBank);
+ if (!chip->details.bank[0].probed) {
+ r = sam4_auto_probe(chip->details.bank[0].bank);
if (r != ERROR_OK)
return r;
}
if (who == -1) {
showall:
r = ERROR_OK;
- for (x = 0; x < pChip->details.n_gpnvms; x++) {
- r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
+ for (x = 0; x < chip->details.n_gpnvms; x++) {
+ r = flashd_get_gpnvm(&(chip->details.bank[0]), x, &v);
if (r != ERROR_OK)
break;
command_print(CMD, "sam4-gpnvm%u: %u", x, v);
}
return r;
}
- if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
- r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
+ if ((who >= 0) && (((unsigned)(who)) < chip->details.n_gpnvms)) {
+ r = flashd_get_gpnvm(&(chip->details.bank[0]), who, &v);
if (r == ERROR_OK)
command_print(CMD, "sam4-gpnvm%u: %u", who, v);
return r;
}
if (0 == strcmp("set", CMD_ARGV[0]))
- r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
+ r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
(0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
- r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
+ r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
else {
command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
r = ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_HANDLER(sam4_handle_slowclk_command)
{
- struct sam4_chip *pChip;
+ struct sam4_chip *chip;
- pChip = get_current_sam4(CMD);
- if (!pChip)
+ chip = get_current_sam4(CMD);
+ if (!chip)
return ERROR_OK;
switch (CMD_ARGC) {
command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
return ERROR_COMMAND_SYNTAX_ERROR;
}
- pChip->cfg.slow_freq = v;
+ chip->cfg.slow_freq = v;
break;
}
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
command_print(CMD, "Slowclk freq: %d.%03dkhz",
- (int)(pChip->cfg.slow_freq / 1000),
- (int)(pChip->cfg.slow_freq % 1000));
+ (int)(chip->cfg.slow_freq / 1000),
+ (int)(chip->cfg.slow_freq % 1000));
return ERROR_OK;
}
#define AVR_JTAG_INS_PROG_PAGEREAD 0x07
/* Data Registers: */
-#define AVR_JTAG_REG_Bypass_Len 1
-#define AVR_JTAG_REG_DeviceID_Len 32
+#define AVR_JTAG_REG_BYPASS_LEN 1
+#define AVR_JTAG_REG_DEVICEID_LEN 32
-#define AVR_JTAG_REG_Reset_Len 1
-#define AVR_JTAG_REG_JTAGID_Len 32
-#define AVR_JTAG_REG_ProgrammingEnable_Len 16
-#define AVR_JTAG_REG_ProgrammingCommand_Len 15
-#define AVR_JTAG_REG_FlashDataByte_Len 16
+#define AVR_JTAG_REG_RESET_LEN 1
+#define AVR_JTAG_REG_JTAGID_LEN 32
+#define AVR_JTAG_REG_PROGRAMMING_ENABLE_LEN 16
+#define AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN 15
+#define AVR_JTAG_REG_FLASH_DATA_BYTE_LEN 16
struct avrf_type {
char name[15];
static int avr_jtag_reset(struct avr_common *avr, uint32_t reset)
{
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_AVR_RESET);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, reset, AVR_JTAG_REG_Reset_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, reset, AVR_JTAG_REG_RESET_LEN);
return ERROR_OK;
}
static int avr_jtag_read_jtagid(struct avr_common *avr, uint32_t *id)
{
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_IDCODE);
- avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_LEN);
return ERROR_OK;
}
avr_jtag_reset(avr, 1);
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_ProgrammingEnable_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_PROGRAMMING_ENABLE_LEN);
return ERROR_OK;
}
static int avr_jtagprg_leaveprogmode(struct avr_common *avr)
{
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_ProgrammingEnable_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_PROGRAMMING_ENABLE_LEN);
avr_jtag_reset(avr, 0);
uint32_t poll_value;
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
do {
poll_value = 0;
avr_jtag_senddat(avr->jtag_info.tap,
&poll_value,
0x3380,
- AVR_JTAG_REG_ProgrammingCommand_Len);
+ AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
if (ERROR_OK != mcu_execute_queue())
return ERROR_FAIL;
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
uint32_t poll_value;
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
/* load extended high byte */
if (ext_addressing)
avr_jtag_senddat(avr->jtag_info.tap,
NULL,
0x0b00 | ((addr >> 17) & 0xFF),
- AVR_JTAG_REG_ProgrammingCommand_Len);
+ AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
/* load addr high byte */
avr_jtag_senddat(avr->jtag_info.tap,
NULL,
0x0700 | ((addr >> 9) & 0xFF),
- AVR_JTAG_REG_ProgrammingCommand_Len);
+ AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
/* load addr low byte */
avr_jtag_senddat(avr->jtag_info.tap,
NULL,
0x0300 | ((addr >> 1) & 0xFF),
- AVR_JTAG_REG_ProgrammingCommand_Len);
+ AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_PAGELOAD);
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
do {
poll_value = 0;
avr_jtag_senddat(avr->jtag_info.tap,
&poll_value,
0x3700,
- AVR_JTAG_REG_ProgrammingCommand_Len);
+ AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
if (ERROR_OK != mcu_execute_queue())
return ERROR_FAIL;
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
{
struct target *target = bank->target;
const int buffer_size = 1024;
- uint32_t nBytes;
+ uint32_t n_bytes;
int retval = ERROR_OK;
if (bank->target->state != TARGET_HALTED) {
if (retval != ERROR_OK)
goto done;
- for (nBytes = 0; nBytes < chunk; nBytes++) {
- if (buffer[nBytes] != bank->erased_value) {
+ for (n_bytes = 0; n_bytes < chunk; n_bytes++) {
+ if (buffer[n_bytes] != bank->erased_value) {
bank->sectors[i].is_erased = 0;
break;
}
uint32_t start_address;
};
-static const int sectorSize = 0x10000;
+static const int sector_size = 0x10000;
/* flash bank faux <base> <size> <chip_width> <bus_width> <target#> <driverPath>
/* Use 0x10000 as a fixed sector size. */
uint32_t offset = 0;
- bank->num_sectors = bank->size/sectorSize;
+ bank->num_sectors = bank->size/sector_size;
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
for (unsigned int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].offset = offset;
- bank->sectors[i].size = sectorSize;
+ bank->sectors[i].size = sector_size;
offset += bank->sectors[i].size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 0;
unsigned int last)
{
struct faux_flash_bank *info = bank->driver_priv;
- memset(info->memory + first*sectorSize, 0xff, sectorSize*(last-first + 1));
+ memset(info->memory + first*sector_size, 0xff, sector_size*(last-first + 1));
return ERROR_OK;
}
struct fm3_flash_bank *fm3_info = bank->driver_priv;
struct target *target = bank->target;
int retval = ERROR_OK;
- uint32_t u32DummyRead;
+ uint32_t u32_dummy_read;
int odd;
- uint32_t u32FlashType;
- uint32_t u32FlashSeqAddress1;
- uint32_t u32FlashSeqAddress2;
+ uint32_t u32_flash_type;
+ uint32_t u32_flash_seq_address1;
+ uint32_t u32_flash_seq_address2;
struct working_area *write_algorithm;
struct reg_param reg_params[3];
struct armv7m_algorithm armv7m_info;
- u32FlashType = (uint32_t) fm3_info->flashtype;
+ u32_flash_type = (uint32_t) fm3_info->flashtype;
- if (u32FlashType == fm3_flash_type1) {
- u32FlashSeqAddress1 = 0x00001550;
- u32FlashSeqAddress2 = 0x00000AA8;
- } else if (u32FlashType == fm3_flash_type2) {
- u32FlashSeqAddress1 = 0x00000AA8;
- u32FlashSeqAddress2 = 0x00000554;
+ if (u32_flash_type == fm3_flash_type1) {
+ u32_flash_seq_address1 = 0x00001550;
+ u32_flash_seq_address2 = 0x00000AA8;
+ } else if (u32_flash_type == fm3_flash_type2) {
+ u32_flash_seq_address1 = 0x00000AA8;
+ u32_flash_seq_address2 = 0x00000554;
} else {
LOG_ERROR("Flash/Device type unknown!");
return ERROR_FLASH_OPERATION_FAILED;
return retval;
/* dummy read of FASZR */
- retval = target_read_u32(target, 0x40000000, &u32DummyRead);
+ retval = target_read_u32(target, 0x40000000, &u32_dummy_read);
if (retval != ERROR_OK)
return retval;
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;
- init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* u32FlashSeqAddress1 */
- init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* u32FlashSeqAddress2 */
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* u32_flash_seq_address1 */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* u32_flash_seq_address2 */
init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* offset */
/* write code buffer and use Flash sector erase code within fm3 */
if (odd)
offset += 4;
- buf_set_u32(reg_params[0].value, 0, 32, u32FlashSeqAddress1);
- buf_set_u32(reg_params[1].value, 0, 32, u32FlashSeqAddress2);
+ buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1);
+ buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2);
buf_set_u32(reg_params[2].value, 0, 32, offset);
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
if (retval != ERROR_OK)
return retval;
- retval = target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
+ retval = target_read_u32(target, 0x40000000, &u32_dummy_read); /* dummy read of FASZR */
return retval;
}
struct reg_param reg_params[6];
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
- uint32_t u32FlashType;
- uint32_t u32FlashSeqAddress1;
- uint32_t u32FlashSeqAddress2;
+ uint32_t u32_flash_type;
+ uint32_t u32_flash_seq_address1;
+ uint32_t u32_flash_seq_address2;
/* Increase buffer_size if needed */
if (buffer_size < (target->working_area_size / 2))
buffer_size = (target->working_area_size / 2);
- u32FlashType = (uint32_t) fm3_info->flashtype;
+ u32_flash_type = (uint32_t) fm3_info->flashtype;
- if (u32FlashType == fm3_flash_type1) {
- u32FlashSeqAddress1 = 0x00001550;
- u32FlashSeqAddress2 = 0x00000AA8;
- } else if (u32FlashType == fm3_flash_type2) {
- u32FlashSeqAddress1 = 0x00000AA8;
- u32FlashSeqAddress2 = 0x00000554;
+ if (u32_flash_type == fm3_flash_type1) {
+ u32_flash_seq_address1 = 0x00001550;
+ u32_flash_seq_address2 = 0x00000AA8;
+ } else if (u32_flash_type == fm3_flash_type2) {
+ u32_flash_seq_address1 = 0x00000AA8;
+ u32_flash_seq_address2 = 0x00000554;
} else {
LOG_ERROR("Flash/Device type unknown!");
return ERROR_FLASH_OPERATION_FAILED;
0x55, 0xF0, 0x01, 0x05, /* ORRS.W R5, R5, #1 */
0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
0x35, 0x60, /* STR R5, [R6] */
- /* u32DummyRead = fm3_FLASH_IF->FASZ; */
- 0x28, 0x4D, /* LDR.N R5, ??u32DummyRead */
+ /* u32_dummy_read = fm3_FLASH_IF->FASZ; */
+ 0x28, 0x4D, /* LDR.N R5, ??u32_dummy_read */
0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
0x36, 0x68, /* LDR R6, [R6] */
0x2E, 0x60, /* STR R6, [R5] */
0x55, 0xF0, 0x02, 0x05, /* ORRS.W R5, R5, #2 */
0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
0x35, 0x60, /* STR R5, [R6] */
- /* u32DummyRead = fm3_FLASH_IF->FASZ; */
- 0x04, 0x4D, /* LDR.N R5, ??u32DummyRead */
+ /* u32_dummy_read = fm3_FLASH_IF->FASZ; */
+ 0x04, 0x4D, /* LDR.N R5, ??u32_dummy_read */
0x5F, 0xF0, 0x80, 0x46, /* MOVS.W R6, #(fm3_FLASH_IF->FASZ) */
0x36, 0x68, /* LDR R6, [R6] */
0x2E, 0x60, /* STR R6, [R5] */
/* SRAM basic-address + 8.These address pointers will be patched, if a */
/* different start address in RAM is used (e.g. for Flash type 2)! */
/* Default SRAM basic-address is 0x20000000. */
- 0x00, 0x00, 0x00, 0x20, /* u32DummyRead address in RAM (0x20000000) */
+ 0x00, 0x00, 0x00, 0x20, /* u32_dummy_read address in RAM (0x20000000) */
0x04, 0x00, 0x00, 0x20 /* u32FlashResult address in RAM (0x20000004) */
};
return retval;
/* Patching 'local variable address' */
- /* Algorithm: u32DummyRead: */
+ /* Algorithm: u32_dummy_read: */
retval = target_write_u32(target, (write_algorithm->address + 8)
+ sizeof(fm3_flash_write_code) - 8, (write_algorithm->address));
if (retval != ERROR_OK)
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
- buf_set_u32(reg_params[3].value, 0, 32, u32FlashSeqAddress1);
- buf_set_u32(reg_params[4].value, 0, 32, u32FlashSeqAddress2);
+ buf_set_u32(reg_params[3].value, 0, 32, u32_flash_seq_address1);
+ buf_set_u32(reg_params[4].value, 0, 32, u32_flash_seq_address2);
retval = target_run_algorithm(target, 0, NULL, 6, reg_params,
(write_algorithm->address + 8), 0, 1000, &armv7m_info);
struct target *target = bank->target;
struct fm3_flash_bank *fm3_info2 = bank->driver_priv;
int retval = ERROR_OK;
- uint32_t u32DummyRead;
- uint32_t u32FlashType;
- uint32_t u32FlashSeqAddress1;
- uint32_t u32FlashSeqAddress2;
+ uint32_t u32_dummy_read;
+ uint32_t u32_flash_type;
+ uint32_t u32_flash_seq_address1;
+ uint32_t u32_flash_seq_address2;
struct working_area *write_algorithm;
struct reg_param reg_params[3];
struct armv7m_algorithm armv7m_info;
- u32FlashType = (uint32_t) fm3_info2->flashtype;
+ u32_flash_type = (uint32_t) fm3_info2->flashtype;
- if (u32FlashType == fm3_flash_type1) {
+ if (u32_flash_type == fm3_flash_type1) {
LOG_INFO("*** Erasing mb9bfxxx type");
- u32FlashSeqAddress1 = 0x00001550;
- u32FlashSeqAddress2 = 0x00000AA8;
- } else if (u32FlashType == fm3_flash_type2) {
+ u32_flash_seq_address1 = 0x00001550;
+ u32_flash_seq_address2 = 0x00000AA8;
+ } else if (u32_flash_type == fm3_flash_type2) {
LOG_INFO("*** Erasing mb9afxxx type");
- u32FlashSeqAddress1 = 0x00000AA8;
- u32FlashSeqAddress2 = 0x00000554;
+ u32_flash_seq_address1 = 0x00000AA8;
+ u32_flash_seq_address2 = 0x00000554;
} else {
LOG_ERROR("Flash/Device type unknown!");
return ERROR_FLASH_OPERATION_FAILED;
return retval;
/* dummy read of FASZR */
- retval = target_read_u32(target, 0x40000000, &u32DummyRead);
+ retval = target_read_u32(target, 0x40000000, &u32_dummy_read);
if (retval != ERROR_OK)
return retval;
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;
- init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* u32FlashSeqAddress1 */
- init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* u32FlashSeqAddress2 */
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* u32_flash_seq_address1 */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* u32_flash_seq_address2 */
- buf_set_u32(reg_params[0].value, 0, 32, u32FlashSeqAddress1);
- buf_set_u32(reg_params[1].value, 0, 32, u32FlashSeqAddress2);
+ buf_set_u32(reg_params[0].value, 0, 32, u32_flash_seq_address1);
+ buf_set_u32(reg_params[1].value, 0, 32, u32_flash_seq_address2);
retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
write_algorithm->address, 0, 100000, &armv7m_info);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
- retval = fm3_busy_wait(target, u32FlashSeqAddress2, 20000); /* 20s timeout */
+ retval = fm3_busy_wait(target, u32_flash_seq_address2, 20000); /* 20s timeout */
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- retval = target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
+ retval = target_read_u32(target, 0x40000000, &u32_dummy_read); /* dummy read of FASZR */
return retval;
}
#define MSCM_OCMDR0 0x40001400
#define FMC_PFB01CR 0x4001f004
-#define FTFx_FSTAT 0x40020000
-#define FTFx_FCNFG 0x40020001
-#define FTFx_FCCOB3 0x40020004
-#define FTFx_FPROT3 0x40020010
-#define FTFx_FDPROT 0x40020017
+#define FTFX_FSTAT 0x40020000
+#define FTFX_FCNFG 0x40020001
+#define FTFX_FCCOB3 0x40020004
+#define FTFX_FPROT3 0x40020010
+#define FTFX_FDPROT 0x40020017
#define SIM_BASE 0x40047000
#define SIM_BASE_KL28 0x40074000
#define SIM_COPC 0x40048100
#define PM_CTRL_RUNM_RUN 0x00
/* Commands */
-#define FTFx_CMD_BLOCKSTAT 0x00
-#define FTFx_CMD_SECTSTAT 0x01
-#define FTFx_CMD_LWORDPROG 0x06
-#define FTFx_CMD_SECTERASE 0x09
-#define FTFx_CMD_SECTWRITE 0x0b
-#define FTFx_CMD_MASSERASE 0x44
-#define FTFx_CMD_PGMPART 0x80
-#define FTFx_CMD_SETFLEXRAM 0x81
+#define FTFX_CMD_BLOCKSTAT 0x00
+#define FTFX_CMD_SECTSTAT 0x01
+#define FTFX_CMD_LWORDPROG 0x06
+#define FTFX_CMD_SECTERASE 0x09
+#define FTFX_CMD_SECTWRITE 0x0b
+#define FTFX_CMD_MASSERASE 0x44
+#define FTFX_CMD_PGMPART 0x80
+#define FTFX_CMD_SETFLEXRAM 0x81
/* The older Kinetis K series uses the following SDID layout :
* Bit 31-16 : 0
/* The field originally named DIEID has new name/meaning on KE1x */
#define KINETIS_SDID_PROJECTID_MASK KINETIS_SDID_DIEID_MASK
-#define KINETIS_SDID_PROJECTID_KE1xF 0x00000080
-#define KINETIS_SDID_PROJECTID_KE1xZ 0x00000100
+#define KINETIS_SDID_PROJECTID_KE1XF 0x00000080
+#define KINETIS_SDID_PROJECTID_KE1XZ 0x00000100
struct kinetis_flash_bank {
struct kinetis_chip *k_chip;
static int kinetis_ftfx_clear_error(struct target *target)
{
/* reset error flags */
- return target_write_u8(target, FTFx_FSTAT, 0x70);
+ return target_write_u8(target, FTFX_FSTAT, 0x70);
}
/* wait until busy */
for (unsigned int i = 0; i < 50; i++) {
- result = target_read_u8(target, FTFx_FSTAT, &fstat);
+ result = target_read_u8(target, FTFX_FSTAT, &fstat);
if (result != ERROR_OK)
return result;
buf_set_u32(reg_params[1].value, 0, 32, wcount);
buf_set_u32(reg_params[2].value, 0, 32, source->address);
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
- buf_set_u32(reg_params[4].value, 0, 32, FTFx_FSTAT);
+ buf_set_u32(reg_params[4].value, 0, 32, FTFX_FSTAT);
retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
0, NULL,
LOG_ERROR("Error writing flash at %08" PRIx32, end_address);
- retval = target_read_u8(target, FTFx_FSTAT, &fstat);
+ retval = target_read_u8(target, FTFX_FSTAT, &fstat);
if (retval == ERROR_OK) {
retval = kinetis_ftfx_decode_error(fstat);
/* reset error flags */
- target_write_u8(target, FTFx_FSTAT, 0x70);
+ target_write_u8(target, FTFX_FSTAT, 0x70);
}
} else if (retval != ERROR_OK)
LOG_ERROR("Error executing kinetis Flash programming algorithm");
if (k_bank->flash_class == FC_PFLASH) {
/* read protection register */
- result = target_read_u32(bank->target, FTFx_FPROT3, &fprot);
+ result = target_read_u32(bank->target, FTFX_FPROT3, &fprot);
if (result != ERROR_OK)
return result;
uint8_t fdprot;
/* read protection register */
- result = target_read_u8(bank->target, FTFx_FDPROT, &fdprot);
+ result = target_read_u8(bank->target, FTFX_FDPROT, &fdprot);
if (result != ERROR_OK)
return result;
uint8_t fstat;
int64_t ms_timeout = timeval_ms() + 250;
- result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
+ result = target_write_memory(target, FTFX_FCCOB3, 4, 3, command);
if (result != ERROR_OK)
return result;
/* start command */
- result = target_write_u8(target, FTFx_FSTAT, 0x80);
+ result = target_write_u8(target, FTFX_FSTAT, 0x80);
if (result != ERROR_OK)
return result;
/* wait for done */
do {
- result = target_read_u8(target, FTFx_FSTAT, &fstat);
+ result = target_read_u8(target, FTFX_FSTAT, &fstat);
if (result != ERROR_OK)
return result;
*/
for (unsigned int i = first; i <= last; i++) {
/* set command and sector address */
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
0, 0, 0, 0, 0, 0, 0, 0, NULL);
if (result != ERROR_OK) {
uint8_t ftfx_fcnfg;
/* check if ram ready */
- result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
+ result = target_read_u8(target, FTFX_FCNFG, &ftfx_fcnfg);
if (result != ERROR_OK)
return result;
return ERROR_OK; /* ram ready */
/* make flex ram available */
- result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
+ result = kinetis_ftfx_command(target, FTFX_CMD_SETFLEXRAM, 0x00ff0000,
0, 0, 0, 0, 0, 0, 0, 0, NULL);
if (result != ERROR_OK)
return ERROR_FLASH_OPERATION_FAILED;
/* check again */
- result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
+ result = target_read_u8(target, FTFX_FCNFG, &ftfx_fcnfg);
if (result != ERROR_OK)
return result;
}
/* execute section-write command */
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTWRITE,
k_bank->prog_base + offset - align_begin,
chunk_count>>8, chunk_count, 0, 0,
0, 0, 0, 0, &ftfx_fstat);
LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, k_bank->prog_base + offset,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_LWORDPROG, k_bank->prog_base + offset,
buffer[3], buffer[2], buffer[1], buffer[0],
0, 0, 0, 0, &ftfx_fstat);
k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
switch (k_chip->sim_sdid &
(KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK | KINETIS_SDID_PROJECTID_MASK)) {
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xZ:
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1xZ:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1XZ:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1XZ:
/* KE1xZ: FTFE, 2kB sectors */
k_chip->pflash_sector_size = 2<<10;
k_chip->nvm_sector_size = 2<<10;
familyid, subfamid, cpu_mhz / 10);
break;
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xF:
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1xF:
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1xF:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1XF:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1XF:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1XF:
/* KE1xF: FTFE, 4kB sectors */
k_chip->pflash_sector_size = 4<<10;
k_chip->nvm_sector_size = 2<<10;
if (use_block_cmd) {
/* check if whole bank is blank */
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, k_bank->prog_base,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_BLOCKSTAT, k_bank->prog_base,
0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
if (result != ERROR_OK)
/* the whole bank is not erased, check sector-by-sector */
for (unsigned int i = 0; i < bank->num_sectors; i++) {
/* normal margin */
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTSTAT,
k_bank->prog_base + bank->sectors[i].offset,
1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
if (result != ERROR_OK)
return result;
- result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
+ result = kinetis_ftfx_command(target, FTFX_CMD_PGMPART, load_flex_ram,
ee_size_code, flex_nvm_partition_code, 0, 0,
0, 0, 0, 0, NULL);
if (result != ERROR_OK)
#define IAP_CODE_LEN 0x34
-#define LPC11xx_REG_SECTORS 24
+#define LPC11XX_REG_SECTORS 24
typedef enum {
lpc2000_v1,
unsigned int large_sectors = 0;
unsigned int normal_sectors = bank->size / 4096;
- if (normal_sectors > LPC11xx_REG_SECTORS) {
- large_sectors = (normal_sectors - LPC11xx_REG_SECTORS) / 8;
- normal_sectors = LPC11xx_REG_SECTORS;
+ if (normal_sectors > LPC11XX_REG_SECTORS) {
+ large_sectors = (normal_sectors - LPC11XX_REG_SECTORS) / 8;
+ normal_sectors = LPC11XX_REG_SECTORS;
}
bank->num_sectors = normal_sectors + large_sectors;
for (unsigned int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].offset = offset;
- bank->sectors[i].size = (i < LPC11xx_REG_SECTORS ? 4 : 32) * 1024;
+ bank->sectors[i].size = (i < LPC11XX_REG_SECTORS ? 4 : 32) * 1024;
offset += bank->sectors[i].size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
{NUMICRO_CONFIG_BASE, 1024} }
-static const struct numicro_cpu_type NuMicroParts[] = {
+static const struct numicro_cpu_type numicro_parts[] = {
/*PART NO*/ /*PART ID*/ /*Banks*/
/* NUC100 Version B */
{"NUC100LD2BN", 0x10010004, NUMICRO_BANKS_NUC100(64*1024)},
LOG_INFO("Device ID: 0x%08" PRIx32 "", part_id);
/* search part numbers */
- for (size_t i = 0; i < ARRAY_SIZE(NuMicroParts); i++) {
- if (part_id == NuMicroParts[i].partid) {
- *cpu = &NuMicroParts[i];
+ for (size_t i = 0; i < ARRAY_SIZE(numicro_parts); i++) {
+ if (part_id == numicro_parts[i].partid) {
+ *cpu = &numicro_parts[i];
LOG_INFO("Device Name: %s", (*cpu)->partname);
return ERROR_OK;
}
* Note: These macros only work for KSEG0/KSEG1 addresses.
*/
-#define Virt2Phys(v) ((v) & 0x1FFFFFFF)
+#define virt2phys(v) ((v) & 0x1FFFFFFF)
/* pic32mx configuration register locations */
-#define PIC32MX_DEVCFG0_1xx_2xx 0xBFC00BFC
+#define PIC32MX_DEVCFG0_1XX_2XX 0xBFC00BFC
#define PIC32MX_DEVCFG0 0xBFC02FFC
#define PIC32MX_DEVCFG1 0xBFC02FF8
#define PIC32MX_DEVCFG2 0xBFC02FF4
#define NVMKEY1 0xAA996655
#define NVMKEY2 0x556699AA
-#define MX_1xx_2xx 1 /* PIC32mx1xx/2xx */
-#define MX_17x_27x 2 /* PIC32mx17x/27x */
+#define MX_1XX_2XX 1 /* PIC32mx1xx/2xx */
+#define MX_17X_27X 2 /* PIC32mx17x/27x */
struct pic32mx_flash_bank {
bool probed;
}
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
- config0_address = PIC32MX_DEVCFG0_1xx_2xx;
+ case MX_1XX_2XX:
+ case MX_17X_27X:
+ config0_address = PIC32MX_DEVCFG0_1XX_2XX;
break;
default:
config0_address = PIC32MX_DEVCFG0;
if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
num_pages = 0xffff; /* All pages protected */
- else if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
+ else if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
if (devcfg0 & (1 << 24))
num_pages = 0; /* All pages unprotected */
else
} else {
/* pgm flash */
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
+ case MX_1XX_2XX:
num_pages = (~devcfg0 >> 10) & 0x7f;
break;
- case MX_17x_27x:
+ case MX_17X_27X:
num_pages = (~devcfg0 >> 10) & 0x1ff;
break;
default:
}
if ((first == 0) && (last == (bank->num_sectors - 1))
- && (Virt2Phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
+ && (virt2phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
/* this will only erase the Program Flash (PFM), not the Boot Flash (BFM)
* we need to use the MTAP to perform a full erase */
LOG_DEBUG("Erasing entire program flash");
}
for (unsigned int i = first; i <= last; i++) {
- target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(bank->base + bank->sectors[i].offset));
+ target_write_u32(target, PIC32MX_NVMADDR, virt2phys(bank->base + bank->sectors[i].offset));
status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
/* Change values for counters and row size, depending on variant */
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
+ case MX_1XX_2XX:
+ case MX_17X_27X:
/* 128 byte row */
pic32mx_flash_write_code[8] = 0x2CD30020;
pic32mx_flash_write_code[14] = 0x24840080;
break;
}
- buf_set_u32(reg_params[0].value, 0, 32, Virt2Phys(source->address));
- buf_set_u32(reg_params[1].value, 0, 32, Virt2Phys(address));
+ buf_set_u32(reg_params[0].value, 0, 32, virt2phys(source->address));
+ buf_set_u32(reg_params[1].value, 0, 32, virt2phys(address));
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count + row_offset / 4);
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
{
struct target *target = bank->target;
- target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(address));
+ target_write_u32(target, PIC32MX_NVMADDR, virt2phys(address));
target_write_u32(target, PIC32MX_NVMDATA, word);
return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
for (i = 0; pic32mx_devs[i].name != NULL; i++) {
if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
if ((pic32mx_devs[i].name[0] == '1') || (pic32mx_devs[i].name[0] == '2'))
- pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17x_27x : MX_1xx_2xx;
+ pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17X_27X : MX_1XX_2XX;
break;
}
}
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
+ case MX_1XX_2XX:
+ case MX_17X_27X:
page_size = 1024;
break;
default:
break;
}
- if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
+ if (virt2phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
/* 0x1FC00000: Boot flash size */
#if 0
/* for some reason this register returns 8k for the boot bank size
#else
/* fixed 12k boot bank - see comments above */
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
+ case MX_1XX_2XX:
+ case MX_17X_27X:
num_pages = (3 * 1024);
break;
default:
/* read the flash size from the device */
if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
switch (pic32mx_info->dev_type) {
- case MX_1xx_2xx:
- case MX_17x_27x:
+ case MX_1XX_2XX:
+ case MX_17X_27X:
LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 32k flash");
num_pages = (32 * 1024);
break;
#define PM_ACT_CFG0_EN_CLK_SPC (1 << 3)
-#define PHUB_CHx_BASIC_CFG_EN (1 << 0)
-#define PHUB_CHx_BASIC_CFG_WORK_SEP (1 << 5)
+#define PHUB_CHX_BASIC_CFG_EN (1 << 0)
+#define PHUB_CHX_BASIC_CFG_WORK_SEP (1 << 5)
-#define PHUB_CHx_ACTION_CPU_REQ (1 << 0)
+#define PHUB_CHX_ACTION_CPU_REQ (1 << 0)
-#define PHUB_CFGMEMx_CFG0 (1 << 7)
+#define PHUB_CFGMEMX_CFG0 (1 << 7)
-#define PHUB_TDMEMx_ORIG_TD0_NEXT_TD_PTR_LAST (0xff << 16)
-#define PHUB_TDMEMx_ORIG_TD0_INC_SRC_ADDR (1 << 24)
+#define PHUB_TDMEMX_ORIG_TD0_NEXT_TD_PTR_LAST (0xff << 16)
+#define PHUB_TDMEMX_ORIG_TD0_INC_SRC_ADDR (1 << 24)
#define NVL_3_ECCEN (1 << 3)
retval = target_write_u32(target,
even_row ? PHUB_CH0_BASIC_CFG : PHUB_CH1_BASIC_CFG,
- PHUB_CHx_BASIC_CFG_WORK_SEP | PHUB_CHx_BASIC_CFG_EN);
+ PHUB_CHX_BASIC_CFG_WORK_SEP | PHUB_CHX_BASIC_CFG_EN);
if (retval != ERROR_OK)
goto err_dma;
retval = target_write_u32(target,
even_row ? PHUB_CFGMEM0_CFG0 : PHUB_CFGMEM1_CFG0,
- PHUB_CFGMEMx_CFG0);
+ PHUB_CFGMEMX_CFG0);
if (retval != ERROR_OK)
goto err_dma;
retval = target_write_u32(target,
even_row ? PHUB_TDMEM0_ORIG_TD0 : PHUB_TDMEM1_ORIG_TD0,
- PHUB_TDMEMx_ORIG_TD0_INC_SRC_ADDR |
- PHUB_TDMEMx_ORIG_TD0_NEXT_TD_PTR_LAST |
+ PHUB_TDMEMX_ORIG_TD0_INC_SRC_ADDR |
+ PHUB_TDMEMX_ORIG_TD0_NEXT_TD_PTR_LAST |
((SPC_OPCODE_LEN + 1 + row_size + 3 + SPC_OPCODE_LEN + 5) & 0xfff));
if (retval != ERROR_OK)
goto err_dma;
retval = target_write_u32(target,
even_row ? PHUB_CH0_ACTION : PHUB_CH1_ACTION,
- PHUB_CHx_ACTION_CPU_REQ);
+ PHUB_CHX_ACTION_CPU_REQ);
if (retval != ERROR_OK)
goto err_dma_action;
}
uint8_t class;
uint8_t partno;
const char *partname;
-} StellarisParts[] = {
+} stellaris_parts[] = {
{0x00, 0x01, "LM3S101"},
{0x00, 0x02, "LM3S102"},
{0x01, 0xBF, "LM3S1110"},
{0xFF, 0x00, "Unknown Part"}
};
-static const char * const StellarisClassname[] = {
+static const char * const stellaris_classname[] = {
"Sandstorm",
"Fury",
"Unknown",
"\nTI/LMI Stellaris information: Chip is "
"class %i (%s) %s rev %c%i\n",
stellaris_info->target_class,
- StellarisClassname[stellaris_info->target_class],
+ stellaris_classname[stellaris_info->target_class],
stellaris_info->target_name,
(int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
(int)((stellaris_info->did0) & 0xFF));
LOG_WARNING("Unknown did0 class");
}
- for (i = 0; StellarisParts[i].partno; i++) {
- if ((StellarisParts[i].partno == ((did1 >> 16) & 0xFF)) &&
- (StellarisParts[i].class == stellaris_info->target_class))
+ for (i = 0; stellaris_parts[i].partno; i++) {
+ if ((stellaris_parts[i].partno == ((did1 >> 16) & 0xFF)) &&
+ (stellaris_parts[i].class == stellaris_info->target_class))
break;
}
- stellaris_info->target_name = StellarisParts[i].partname;
+ stellaris_info->target_name = stellaris_parts[i].partname;
stellaris_info->did0 = did0;
stellaris_info->did1 = did1;
struct str7x_flash_bank *str7x_info = NULL;
uint32_t flash_cmd;
- uint16_t ProtectionLevel = 0;
- uint16_t ProtectionRegs;
+ uint16_t protection_level = 0;
+ uint16_t protection_regs;
if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), ®);
if (!(reg & str7x_info->disable_bit))
- ProtectionLevel = 1;
+ protection_level = 1;
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), ®);
- ProtectionRegs = ~(reg >> 16);
+ protection_regs = ~(reg >> 16);
- while (((ProtectionRegs) != 0) && (ProtectionLevel < 16)) {
- ProtectionRegs >>= 1;
- ProtectionLevel++;
+ while (((protection_regs) != 0) && (protection_level < 16)) {
+ protection_regs >>= 1;
+ protection_level++;
}
- if (ProtectionLevel == 0) {
+ if (protection_level == 0) {
flash_cmd = FLASH_SPR;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0),
- ~(1 << (15 + ProtectionLevel)));
+ ~(1 << (15 + protection_level)));
flash_cmd = FLASH_SPR | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
}
/* ---------------------------------------------------------------------- */
-static uint32_t keysSet;
-static uint32_t flashKeys[4];
+static uint32_t keys_set;
+static uint32_t flash_keys[4];
COMMAND_HANDLER(tms470_handle_flash_keyset_command)
{
for (i = 0; i < 4; i++) {
int start = (0 == strncmp(CMD_ARGV[i], "0x", 2)) ? 2 : 0;
- if (1 != sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flashKeys[i])) {
+ if (1 != sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flash_keys[i])) {
command_print(CMD, "could not process flash key %s",
CMD_ARGV[i]);
LOG_ERROR("could not process flash key %s", CMD_ARGV[i]);
}
}
- keysSet = 1;
+ keys_set = 1;
} else if (CMD_ARGC != 0) {
command_print(CMD, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
return ERROR_COMMAND_SYNTAX_ERROR;
}
- if (keysSet) {
+ if (keys_set) {
command_print(CMD,
"using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
- flashKeys[0],
- flashKeys[1],
- flashKeys[2],
- flashKeys[3]);
+ flash_keys[0],
+ flash_keys[1],
+ flash_keys[2],
+ flash_keys[3]);
} else
command_print(CMD, "flash keys not set");
const uint32_t *p_key_sets[5];
unsigned i, key_set_count;
- if (keysSet) {
+ if (keys_set) {
key_set_count = 5;
- p_key_sets[0] = flashKeys;
+ p_key_sets[0] = flash_keys;
p_key_sets[1] = FLASH_KEYS_ALL_ONES;
p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
p_key_sets[3] = FLASH_KEYS_MIX1;
{
uint32_t glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
struct target *target = bank->target;
- uint32_t flashAddr = bank->base + bank->sectors[sector].offset;
+ uint32_t flash_addr = bank->base + bank->sectors[sector].offset;
int result = ERROR_OK;
/*
/*
* clear status register, sent erase command, kickoff erase
*/
- target_write_u16(target, flashAddr, 0x0040);
- LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
- target_write_u16(target, flashAddr, 0x0020);
- LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flashAddr);
- target_write_u16(target, flashAddr, 0xffff);
- LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flashAddr);
+ target_write_u16(target, flash_addr, 0x0040);
+ LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flash_addr);
+ target_write_u16(target, flash_addr, 0x0020);
+ LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flash_addr);
+ target_write_u16(target, flash_addr, 0xffff);
+ LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flash_addr);
/*
* Monitor FMMSTAT, busy until clear, then check and other flags for
Code Review / openocd.git / commitdiff