misc_config->div_instruction = (value_cr4 >> 5) & 0x1;
misc_config->mac_instruction = (value_cr4 >> 6) & 0x1;
misc_config->audio_isa = (value_cr4 >> 7) & 0x3;
- misc_config->L2_cache = (value_cr4 >> 9) & 0x1;
+ misc_config->l2_cache = (value_cr4 >> 9) & 0x1;
misc_config->reduce_register = (value_cr4 >> 10) & 0x1;
misc_config->addr_24 = (value_cr4 >> 11) & 0x1;
misc_config->interruption_level = (value_cr4 >> 12) & 0x1;
struct target *target = nds32->target;
uint32_t value_mr1;
uint32_t load_address;
- uint32_t L1_page_table_entry;
- uint32_t L2_page_table_entry;
+ uint32_t l1_page_table_entry;
+ uint32_t l2_page_table_entry;
uint32_t page_size_index = nds32->mmu_config.default_min_page_size;
struct page_table_walker_info_s *page_table_info_p =
&(page_table_info[page_size_index]);
/* Read L1 Physical Page Table */
nds32_get_mapped_reg(nds32, MR1, &value_mr1);
- load_address = (value_mr1 & page_table_info_p->L1_base_mask) |
- ((virtual_address & page_table_info_p->L1_offset_mask) >>
- page_table_info_p->L1_offset_shift);
+ load_address = (value_mr1 & page_table_info_p->l1_base_mask) |
+ ((virtual_address & page_table_info_p->l1_offset_mask) >>
+ page_table_info_p->l1_offset_shift);
/* load_address is physical address */
- nds32_read_buffer(target, load_address, 4, (uint8_t *)&L1_page_table_entry);
+ nds32_read_buffer(target, load_address, 4, (uint8_t *)&l1_page_table_entry);
/* Read L2 Physical Page Table */
- if (L1_page_table_entry & 0x1) /* L1_PTE not present */
+ if (l1_page_table_entry & 0x1) /* L1_PTE not present */
return ERROR_FAIL;
- load_address = (L1_page_table_entry & page_table_info_p->L2_base_mask) |
- ((virtual_address & page_table_info_p->L2_offset_mask) >>
- page_table_info_p->L2_offset_shift);
+ load_address = (l1_page_table_entry & page_table_info_p->l2_base_mask) |
+ ((virtual_address & page_table_info_p->l2_offset_mask) >>
+ page_table_info_p->l2_offset_shift);
/* load_address is physical address */
- nds32_read_buffer(target, load_address, 4, (uint8_t *)&L2_page_table_entry);
+ nds32_read_buffer(target, load_address, 4, (uint8_t *)&l2_page_table_entry);
- if ((L2_page_table_entry & 0x1) != 0x1) /* L2_PTE not valid */
+ if ((l2_page_table_entry & 0x1) != 0x1) /* L2_PTE not valid */
return ERROR_FAIL;
- *physical_address = (L2_page_table_entry & page_table_info_p->ppn_mask) |
+ *physical_address = (l2_page_table_entry & page_table_info_p->ppn_mask) |
(virtual_address & page_table_info_p->va_offset_mask);
return ERROR_OK;
struct page_table_walker_info_s {
- uint32_t L1_offset_mask;
- uint32_t L1_offset_shift;
- uint32_t L2_offset_mask;
- uint32_t L2_offset_shift;
+ uint32_t l1_offset_mask;
+ uint32_t l1_offset_shift;
+ uint32_t l2_offset_mask;
+ uint32_t l2_offset_shift;
uint32_t va_offset_mask;
- uint32_t L1_base_mask;
- uint32_t L2_base_mask;
+ uint32_t l1_base_mask;
+ uint32_t l2_base_mask;
uint32_t ppn_mask;
};