cortex_a: force cache and tlb bypass when cpu is in debug state

for minimal impact on the hardware state, force all memory accesses to
bypass the caches and tlbs. This may actually be the default, but ARM
recommends in DDI0406C to set proper default values on debug init.

Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3079
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 3f2bdd34c71dea7400461522ffe2151daf12b521..8d7bece11724e2d135738756f3658f1ed62271fc 100644 (file)
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -172,6 +172,7 @@ target_to_armv7a(struct target *target)
 
 /* See ARMv7a arch spec section C10.7 */
 #define CPUDBG_DSCCR           0x028
+#define CPUDBG_DSMCR           0x02C
 
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS      0xFB8

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 5268cf2164586ed7888cb8b7ccf47c55c62b3695..61a5df38918b426447994d07bb8c71fba71004ce 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -243,6 +243,18 @@ static int cortex_a_init_debug_access(struct target *target)
        if (retval != ERROR_OK)
                return retval;
 
+       /* Disable cacheline fills and force cache write-through in debug state */
+       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+                       armv7a->debug_base + CPUDBG_DSCCR, 0);
+       if (retval != ERROR_OK)
+               return retval;
+
+       /* Disable TLB lookup and refill/eviction in debug state */
+       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+                       armv7a->debug_base + CPUDBG_DSMCR, 0);
+       if (retval != ERROR_OK)
+               return retval;
+
        /* Enabling of instruction execution in debug mode is done in debug_entry code */
 
        /* Resync breakpoint registers */