int validate_target_result;
uint16_t buffsize_register_content;
uint32_t sreg_content;
- uint32_t SREG = MX2_FMCR;
- uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
- uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
+ uint32_t sreg = MX2_FMCR;
+ uint32_t sel_16bit = MX2_FMCR_NF_16BIT_SEL;
+ uint32_t sel_fms = MX2_FMCR_NF_FMS;
int retval;
uint16_t nand_status_content;
/*
mxc_nf_info->flags.one_kb_sram = 0;
if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
- SREG = MX3_PCSR;
- SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
- SEL_FMS = MX3_PCSR_NF_FMS;
+ sreg = MX3_PCSR;
+ sel_16bit = MX3_PCSR_NF_16BIT_SEL;
+ sel_fms = MX3_PCSR_NF_FMS;
} else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
- SREG = MX25_RCSR;
- SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
- SEL_FMS = MX25_RCSR_NF_FMS;
+ sreg = MX25_RCSR;
+ sel_16bit = MX25_RCSR_NF_16BIT_SEL;
+ sel_fms = MX25_RCSR_NF_FMS;
} else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
- SREG = MX35_RCSR;
- SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
- SEL_FMS = MX35_RCSR_NF_FMS;
+ sreg = MX35_RCSR;
+ sel_16bit = MX35_RCSR_NF_16BIT_SEL;
+ sel_fms = MX35_RCSR_NF_FMS;
}
- target_read_u32(target, SREG, &sreg_content);
+ target_read_u32(target, sreg, &sreg_content);
if (!nand->bus_width) {
/* bus_width not yet defined. Read it from MXC_FMCR */
- nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
+ nand->bus_width = (sreg_content & sel_16bit) ? 16 : 8;
} else {
/* bus_width forced in soft. Sync it to MXC_FMCR */
- sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
- target_write_u32(target, SREG, sreg_content);
+ sreg_content |= ((nand->bus_width == 16) ? sel_16bit : 0x00000000);
+ target_write_u32(target, sreg, sreg_content);
}
if (nand->bus_width == 16)
LOG_DEBUG("MXC_NF : bus is 16-bit width");
LOG_DEBUG("MXC_NF : bus is 8-bit width");
if (!nand->page_size)
- nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
+ nand->page_size = (sreg_content & sel_fms) ? 2048 : 512;
else {
- sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
- target_write_u32(target, SREG, sreg_content);
+ sreg_content |= ((nand->page_size == 2048) ? sel_fms : 0x00000000);
+ target_write_u32(target, sreg, sreg_content);
}
if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
LOG_ERROR("NAND controller have only 1 kb SRAM, so "
}
if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
- uint32_t SPARE_BUFFER3;
+ uint32_t spare_buffer3;
/* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
if (nfc_is_v1())
- SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
+ spare_buffer3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
else
- SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
- target_read_u16(target, SPARE_BUFFER3, &swap2);
+ spare_buffer3 = MXC_NF_V2_SPARE_BUFFER3;
+ target_read_u16(target, spare_buffer3, &swap2);
new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
swap2 = (swap1 << 8) | (swap2 & 0xFF);
target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
- target_write_u16(target, SPARE_BUFFER3, swap2);
+ target_write_u16(target, spare_buffer3, swap2);
}
if (data)
static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout);
static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen);
-static const uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
-static const uint32_t MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
-static const uint32_t MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
+static const uint32_t mc_fmr[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
+static const uint32_t mc_fcr[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
+static const uint32_t mc_fsr[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
-static const char *EPROC[8] = {
+static const char *eproc[8] = {
"Unknown", "ARM946-E", "ARM7TDMI", "Unknown", "ARM920T", "ARM926EJ-S", "Unknown", "Unknown"
};
static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number)
{
uint32_t fsr;
- target_read_u32(target, MC_FSR[bank_number], &fsr);
+ target_read_u32(target, mc_fsr[bank_number], &fsr);
return fsr;
}
LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn));
fmr = fmcn << 16 | fws << 8;
- target_write_u32(target, MC_FMR[bank->bank_number], fmr);
+ target_write_u32(target, mc_fmr[bank->bank_number], fmr);
}
at91sam7_info->flashmode = mode;
struct target *target = bank->target;
fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
- target_write_u32(target, MC_FCR[bank->bank_number], fcr);
+ target_write_u32(target, mc_fcr[bank->bank_number], fcr);
LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u",
fcr,
bank->bank_number + 1,
"Flashsize: 0x%8.8" PRIx32 "\n",
at91sam7_info->cidr,
at91sam7_info->cidr_arch,
- EPROC[at91sam7_info->cidr_eproc],
+ eproc[at91sam7_info->cidr_eproc],
at91sam7_info->cidr_version,
bank->size);
int retval;
/* try reading possible IDCODE registers, in the following order */
- uint32_t DBGMCU_IDCODE[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
+ uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
- for (unsigned int i = 0; i < ARRAY_SIZE(DBGMCU_IDCODE); i++) {
- retval = target_read_u32(bank->target, DBGMCU_IDCODE[i], id);
+ for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
+ retval = target_read_u32(bank->target, dbgmcu_idcode[i], id);
if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
return ERROR_OK;
}
};
-static const struct flash_sector TMS470R1A256_SECTORS[] = {
+static const struct flash_sector tms470r1a256_sectors[] = {
{0x00000000, 0x00002000, -1, -1},
{0x00002000, 0x00002000, -1, -1},
{0x00004000, 0x00002000, -1, -1},
};
#define TMS470R1A256_NUM_SECTORS \
- ARRAY_SIZE(TMS470R1A256_SECTORS)
+ ARRAY_SIZE(tms470r1a256_sectors)
-static const struct flash_sector TMS470R1A288_BANK0_SECTORS[] = {
+static const struct flash_sector tms470r1a288_bank0_sectors[] = {
{0x00000000, 0x00002000, -1, -1},
{0x00002000, 0x00002000, -1, -1},
{0x00004000, 0x00002000, -1, -1},
};
#define TMS470R1A288_BANK0_NUM_SECTORS \
- ARRAY_SIZE(TMS470R1A288_BANK0_SECTORS)
+ ARRAY_SIZE(tms470r1a288_bank0_sectors)
-static const struct flash_sector TMS470R1A288_BANK1_SECTORS[] = {
+static const struct flash_sector tms470r1a288_bank1_sectors[] = {
{0x00040000, 0x00010000, -1, -1},
{0x00050000, 0x00010000, -1, -1},
{0x00060000, 0x00010000, -1, -1},
};
#define TMS470R1A288_BANK1_NUM_SECTORS \
- ARRAY_SIZE(TMS470R1A288_BANK1_SECTORS)
+ ARRAY_SIZE(tms470r1a288_bank1_sectors)
-static const struct flash_sector TMS470R1A384_BANK0_SECTORS[] = {
+static const struct flash_sector tms470r1a384_bank0_sectors[] = {
{0x00000000, 0x00002000, -1, -1},
{0x00002000, 0x00002000, -1, -1},
{0x00004000, 0x00004000, -1, -1},
};
#define TMS470R1A384_BANK0_NUM_SECTORS \
- ARRAY_SIZE(TMS470R1A384_BANK0_SECTORS)
+ ARRAY_SIZE(tms470r1a384_bank0_sectors)
-static const struct flash_sector TMS470R1A384_BANK1_SECTORS[] = {
+static const struct flash_sector tms470r1a384_bank1_sectors[] = {
{0x00020000, 0x00008000, -1, -1},
{0x00028000, 0x00008000, -1, -1},
{0x00030000, 0x00008000, -1, -1},
};
#define TMS470R1A384_BANK1_NUM_SECTORS \
- ARRAY_SIZE(TMS470R1A384_BANK1_SECTORS)
+ ARRAY_SIZE(tms470r1a384_bank1_sectors)
-static const struct flash_sector TMS470R1A384_BANK2_SECTORS[] = {
+static const struct flash_sector tms470r1a384_bank2_sectors[] = {
{0x00040000, 0x00008000, -1, -1},
{0x00048000, 0x00008000, -1, -1},
{0x00050000, 0x00008000, -1, -1},
};
#define TMS470R1A384_BANK2_NUM_SECTORS \
- ARRAY_SIZE(TMS470R1A384_BANK2_SECTORS)
+ ARRAY_SIZE(tms470r1a384_bank2_sectors)
/* ---------------------------------------------------------------------- */
bank->base = 0x00000000;
bank->size = 256 * 1024;
bank->num_sectors = TMS470R1A256_NUM_SECTORS;
- bank->sectors = malloc(sizeof(TMS470R1A256_SECTORS));
+ bank->sectors = malloc(sizeof(tms470r1a256_sectors));
if (!bank->sectors)
return ERROR_FLASH_OPERATION_FAILED;
- (void)memcpy(bank->sectors, TMS470R1A256_SECTORS, sizeof(TMS470R1A256_SECTORS));
+ (void)memcpy(bank->sectors, tms470r1a256_sectors, sizeof(tms470r1a256_sectors));
break;
case 0x2b:
bank->base = 0x00000000;
bank->size = 32 * 1024;
bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
- bank->sectors = malloc(sizeof(TMS470R1A288_BANK0_SECTORS));
+ bank->sectors = malloc(sizeof(tms470r1a288_bank0_sectors));
if (!bank->sectors)
return ERROR_FLASH_OPERATION_FAILED;
- (void)memcpy(bank->sectors, TMS470R1A288_BANK0_SECTORS,
- sizeof(TMS470R1A288_BANK0_SECTORS));
+ (void)memcpy(bank->sectors, tms470r1a288_bank0_sectors,
+ sizeof(tms470r1a288_bank0_sectors));
} else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000)) {
tms470_info->ordinal = 1;
bank->base = 0x00040000;
bank->size = 256 * 1024;
bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
- bank->sectors = malloc(sizeof(TMS470R1A288_BANK1_SECTORS));
+ bank->sectors = malloc(sizeof(tms470r1a288_bank1_sectors));
if (!bank->sectors)
return ERROR_FLASH_OPERATION_FAILED;
- (void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS,
- sizeof(TMS470R1A288_BANK1_SECTORS));
+ (void)memcpy(bank->sectors, tms470r1a288_bank1_sectors,
+ sizeof(tms470r1a288_bank1_sectors));
} else {
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
bank->base = 0x00000000;
bank->size = 128 * 1024;
bank->num_sectors = TMS470R1A384_BANK0_NUM_SECTORS;
- bank->sectors = malloc(sizeof(TMS470R1A384_BANK0_SECTORS));
+ bank->sectors = malloc(sizeof(tms470r1a384_bank0_sectors));
if (!bank->sectors)
return ERROR_FLASH_OPERATION_FAILED;
- (void)memcpy(bank->sectors, TMS470R1A384_BANK0_SECTORS,
- sizeof(TMS470R1A384_BANK0_SECTORS));
+ (void)memcpy(bank->sectors, tms470r1a384_bank0_sectors,
+ sizeof(tms470r1a384_bank0_sectors));
} else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000)) {
tms470_info->ordinal = 1;
bank->base = 0x00020000;
bank->size = 128 * 1024;
bank->num_sectors = TMS470R1A384_BANK1_NUM_SECTORS;
- bank->sectors = malloc(sizeof(TMS470R1A384_BANK1_SECTORS));
+ bank->sectors = malloc(sizeof(tms470r1a384_bank1_sectors));
if (!bank->sectors)
return ERROR_FLASH_OPERATION_FAILED;
- (void)memcpy(bank->sectors, TMS470R1A384_BANK1_SECTORS,
- sizeof(TMS470R1A384_BANK1_SECTORS));
+ (void)memcpy(bank->sectors, tms470r1a384_bank1_sectors,
+ sizeof(tms470r1a384_bank1_sectors));
} else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000)) {
tms470_info->ordinal = 2;
bank->base = 0x00040000;
bank->size = 128 * 1024;
bank->num_sectors = TMS470R1A384_BANK2_NUM_SECTORS;
- bank->sectors = malloc(sizeof(TMS470R1A384_BANK2_SECTORS));
+ bank->sectors = malloc(sizeof(tms470r1a384_bank2_sectors));
if (!bank->sectors)
return ERROR_FLASH_OPERATION_FAILED;
- (void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS,
- sizeof(TMS470R1A384_BANK2_SECTORS));
+ (void)memcpy(bank->sectors, tms470r1a384_bank2_sectors,
+ sizeof(tms470r1a384_bank2_sectors));
} else {
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_OK;
}
-static const uint32_t FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
+static const uint32_t flash_keys_all_ones[] = { 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF,};
-static const uint32_t FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
+static const uint32_t flash_keys_all_zeros[] = { 0x00000000, 0x00000000,
0x00000000, 0x00000000,};
-static const uint32_t FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
+static const uint32_t flash_keys_mix1[] = { 0xf0fff0ff, 0xf0fff0ff,
0xf0fff0ff, 0xf0fff0ff};
-static const uint32_t FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
+static const uint32_t flash_keys_mix2[] = { 0x0000ffff, 0x0000ffff,
0x0000ffff, 0x0000ffff};
/* ---------------------------------------------------------------------- */
-static int oscMHz = 12;
+static int osc_mhz = 12;
COMMAND_HANDLER(tms470_handle_osc_megahertz_command)
{
if (CMD_ARGC > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
else if (CMD_ARGC == 1)
- sscanf(CMD_ARGV[0], "%d", &oscMHz);
+ sscanf(CMD_ARGV[0], "%d", &osc_mhz);
- if (oscMHz <= 0) {
+ if (osc_mhz <= 0) {
LOG_ERROR("osc_megahertz must be positive and non-zero!");
command_print(CMD, "osc_megahertz must be positive and non-zero!");
- oscMHz = 12;
+ osc_mhz = 12;
return ERROR_COMMAND_SYNTAX_ERROR;
}
- command_print(CMD, "osc_megahertz=%d", oscMHz);
+ command_print(CMD, "osc_megahertz=%d", osc_mhz);
return ERROR_OK;
}
if (keys_set) {
key_set_count = 5;
p_key_sets[0] = flash_keys;
- p_key_sets[1] = FLASH_KEYS_ALL_ONES;
- p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
- p_key_sets[3] = FLASH_KEYS_MIX1;
- p_key_sets[4] = FLASH_KEYS_MIX2;
+ p_key_sets[1] = flash_keys_all_ones;
+ p_key_sets[2] = flash_keys_all_zeros;
+ p_key_sets[3] = flash_keys_mix1;
+ p_key_sets[4] = flash_keys_mix2;
} else {
key_set_count = 4;
- p_key_sets[0] = FLASH_KEYS_ALL_ONES;
- p_key_sets[1] = FLASH_KEYS_ALL_ZEROS;
- p_key_sets[2] = FLASH_KEYS_MIX1;
- p_key_sets[3] = FLASH_KEYS_MIX2;
+ p_key_sets[0] = flash_keys_all_ones;
+ p_key_sets[1] = flash_keys_all_zeros;
+ p_key_sets[2] = flash_keys_mix1;
+ p_key_sets[3] = flash_keys_mix2;
}
for (i = 0; i < key_set_count; i++) {
* the plldis global.
*/
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
- sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
+ sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * osc_mhz / (1 + (glbctrl & 7));
delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
* GLOBAL VARIABLES
******************************************************************************
*/
-static const uint8_t CMD_BYPASS[2] = {0xFF, 0xFF};
-
-static const uint8_t CMD_ISC_ADDRESS_SHIFT[2] = {0xEB, 0x00};
-static const uint8_t CMD_ISC_DATA_SHIFT[2] = {0xED, 0x00};
-static const uint8_t CMD_ISC_DISABLE[2] = {0xF0, 0x00};
-static const uint8_t CMD_ISC_ENABLE[2] = {0xE8, 0x00};
-static const uint8_t CMD_ISC_ERASE[2] = {0xEC, 0x00};
-static const uint8_t CMD_ISC_PROGRAM[2] = {0xEA, 0x00};
-
-static const uint8_t CMD_XSC_BLANK_CHECK[2] = {0x0D, 0x00};
-static const uint8_t CMD_XSC_CONFIG[2] = {0xEE, 0x00};
-static const uint8_t CMD_XSC_DATA_BTC[2] = {0xF2, 0x00};
-static const uint8_t CMD_XSC_DATA_CCB[2] = {0x0C, 0x00};
-static const uint8_t CMD_XSC_DATA_DONE[2] = {0x09, 0x00};
-static const uint8_t CMD_XSC_DATA_SUCR[2] = {0x0E, 0x00};
-static const uint8_t CMD_XSC_DATA_WRPT[2] = {0xF7, 0x00};
-static const uint8_t CMD_XSC_OP_STATUS[2] = {0xE3, 0x00};
-static const uint8_t CMD_XSC_READ[2] = {0xEF, 0x00};
-static const uint8_t CMD_XSC_UNLOCK[2] = {0x55, 0xAA};
+static const uint8_t cmd_bypass[2] = {0xFF, 0xFF};
+
+static const uint8_t cmd_isc_address_shift[2] = {0xEB, 0x00};
+static const uint8_t cmd_isc_data_shift[2] = {0xED, 0x00};
+static const uint8_t cmd_isc_disable[2] = {0xF0, 0x00};
+static const uint8_t cmd_isc_enable[2] = {0xE8, 0x00};
+static const uint8_t cmd_isc_erase[2] = {0xEC, 0x00};
+static const uint8_t cmd_isc_program[2] = {0xEA, 0x00};
+
+static const uint8_t cmd_xsc_blank_check[2] = {0x0D, 0x00};
+static const uint8_t cmd_xsc_config[2] = {0xEE, 0x00};
+static const uint8_t cmd_xsc_data_btc[2] = {0xF2, 0x00};
+static const uint8_t cmd_xsc_data_ccb[2] = {0x0C, 0x00};
+static const uint8_t cmd_xsc_data_done[2] = {0x09, 0x00};
+static const uint8_t cmd_xsc_data_sucr[2] = {0x0E, 0x00};
+static const uint8_t cmd_xsc_data_wrpt[2] = {0xF7, 0x00};
+static const uint8_t cmd_xsc_op_status[2] = {0xE3, 0x00};
+static const uint8_t cmd_xsc_read[2] = {0xEF, 0x00};
+static const uint8_t cmd_xsc_unlock[2] = {0x55, 0xAA};
/*
******************************************************************************
scan.check_mask = NULL;
scan.check_value = NULL;
scan.num_bits = 16;
- scan.out_value = CMD_BYPASS;
+ scan.out_value = cmd_bypass;
scan.in_value = irdata;
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
scan.check_mask = NULL;
scan.check_value = NULL;
scan.num_bits = 16;
- scan.out_value = CMD_ISC_ENABLE;
+ scan.out_value = cmd_isc_enable;
scan.in_value = NULL;
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
scan.check_mask = NULL;
scan.check_value = NULL;
scan.num_bits = 16;
- scan.out_value = CMD_ISC_DISABLE;
+ scan.out_value = cmd_isc_disable;
scan.in_value = NULL;
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
int64_t dt;
do {
- isc_read_register(bank, CMD_XSC_OP_STATUS, &isc_default, 8);
+ isc_read_register(bank, cmd_xsc_op_status, &isc_default, 8);
if (((isc_default >> 2) & 1) == 1)
return ERROR_OK;
dt = timeval_ms() - t0;
jtag_add_dr_scan(bank->target->tap, 1, &scan, TAP_IRSHIFT);
scan.num_bits = 16;
- scan.out_value = CMD_ISC_PROGRAM;
+ scan.out_value = cmd_isc_program;
scan.in_value = NULL;
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
{
uint8_t select_block[3] = {0x0, 0x0, 0x0};
select_block[0] = fill_select_block(first, last);
- return isc_set_register(bank, CMD_XSC_UNLOCK, select_block, 24, 0);
+ return isc_set_register(bank, cmd_xsc_unlock, select_block, 24, 0);
}
static int isc_set_protect(struct flash_bank *bank, unsigned int first,
for (unsigned int i = first; i <= last; i++)
wrpt[0] &= ~(1 << i);
- return isc_program_register(bank, CMD_XSC_DATA_WRPT, wrpt, 16, 0);
+ return isc_program_register(bank, cmd_xsc_data_wrpt, wrpt, 16, 0);
}
static int isc_erase_sectors(struct flash_bank *bank, unsigned int first,
uint8_t select_block[3] = {0, 0, 0};
select_block[0] = fill_select_block(first, last);
int64_t timeout = SECTOR_ERASE_TIMEOUT_MS * (last - first + 1);
- return isc_set_register(bank, CMD_ISC_ERASE, select_block, 24, timeout);
+ return isc_set_register(bank, cmd_isc_erase, select_block, 24, timeout);
}
static int isc_adr_shift(struct flash_bank *bank, int adr)
{
uint8_t adr_buf[3];
h_u24_to_le(adr_buf, adr);
- return isc_set_register(bank, CMD_ISC_ADDRESS_SHIFT, adr_buf, 24, 0);
+ return isc_set_register(bank, cmd_isc_address_shift, adr_buf, 24, 0);
}
static int isc_program_data_page(struct flash_bank *bank, const uint8_t *page_buf)
{
- return isc_program_register(bank, CMD_ISC_DATA_SHIFT, page_buf, 8 * XCF_PAGE_SIZE, 100);
+ return isc_program_register(bank, cmd_isc_data_shift, page_buf, 8 * XCF_PAGE_SIZE, 100);
}
static void isc_data_read_out(struct flash_bank *bank, uint8_t *buffer, uint32_t count)
scan.check_mask = NULL;
scan.check_value = NULL;
scan.num_bits = 16;
- scan.out_value = CMD_XSC_READ;
+ scan.out_value = cmd_xsc_read;
scan.in_value = NULL;
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
{
uint8_t done = 0xFF;
done &= ~(1 << sector);
- return isc_program_register(bank, CMD_XSC_DATA_DONE, &done, 8, 100);
+ return isc_program_register(bank, cmd_xsc_data_done, &done, 8, 100);
}
static void flip_u8(uint8_t *out, const uint8_t *in, int len)
static uint16_t isc_read_ccb(struct flash_bank *bank)
{
uint8_t ccb[2];
- isc_read_register(bank, CMD_XSC_DATA_CCB, ccb, 16);
+ isc_read_register(bank, cmd_xsc_data_ccb, ccb, 16);
return le_to_h_u16(ccb);
}
{
uint8_t buf[2];
h_u16_to_le(buf, ccb);
- return isc_program_register(bank, CMD_XSC_DATA_CCB, buf, 16, 100);
+ return isc_program_register(bank, cmd_xsc_data_ccb, buf, 16, 100);
}
static int isc_program_singe_revision_sucr(struct flash_bank *bank)
{
uint8_t sucr[2] = {0xFC, 0xFF};
- return isc_program_register(bank, CMD_XSC_DATA_SUCR, sucr, 16, 100);
+ return isc_program_register(bank, cmd_xsc_data_sucr, sucr, 16, 100);
}
static int isc_program_single_revision_btc(struct flash_bank *bank)
btc |= ((bank->num_sectors - 1) << 2);
btc &= ~(1 << 4);
h_u32_to_le(buf, btc);
- return isc_program_register(bank, CMD_XSC_DATA_BTC, buf, 32, 100);
+ return isc_program_register(bank, cmd_xsc_data_btc, buf, 32, 100);
}
static int fpga_configure(struct flash_bank *bank)
scan.check_mask = NULL;
scan.check_value = NULL;
scan.num_bits = 16;
- scan.out_value = CMD_XSC_CONFIG;
+ scan.out_value = cmd_xsc_config;
scan.in_value = NULL;
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
jtag_execute_queue();
uint8_t wrpt[2];
isc_enter(bank);
- isc_read_register(bank, CMD_XSC_DATA_WRPT, wrpt, 16);
+ isc_read_register(bank, cmd_xsc_data_wrpt, wrpt, 16);
isc_leave(bank);
for (unsigned int i = 0; i < bank->num_sectors; i++)
scan.check_mask = NULL;
scan.check_value = NULL;
scan.num_bits = 16;
- scan.out_value = CMD_XSC_BLANK_CHECK;
+ scan.out_value = cmd_xsc_blank_check;
scan.in_value = NULL;
jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
jtag_execute_queue();