* Call adiv5_jim_configure() to parse the common DAP options
* It will return JIM_CONTINUE if it didn't find any known
* options, JIM_OK if it correctly parsed the topmost option
- * and JIM_ERR if an error occured during parameter evaluation.
+ * and JIM_ERR if an error occurred during parameter evaluation.
* For JIM_CONTINUE, we check our own params.
*/
e = adiv5_jim_configure(target, goi);
* unexisting register is safe RAZ, rather then an error.
* Note, core registers cannot be BCR.
*
- * In arc/cpu/ tcl files all regiters are defined as core, non-BCR aux
+ * In arc/cpu/ tcl files all registers are defined as core, non-BCR aux
* and BCR aux, in "add-reg" command they are passed to three lists
* respectively: core_reg_descriptions, aux_reg_descriptions,
* bcr_reg_descriptions.
.set = arc_set_register,
};
-/* GDB register groups. For now we suport only general and "empty" */
+/* GDB register groups. For now we support only general and "empty" */
static const char * const reg_group_general = "general";
static const char * const reg_group_other = "";
struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
if (!reg) {
- LOG_ERROR("Requested register `%s' doens't exist.", reg_name);
+ LOG_ERROR("Requested register `%s' doesn't exist.", reg_name);
return ERROR_ARC_REGISTER_NOT_FOUND;
}
if (!reg->valid)
CHECK_RETVAL(reg->type->get(reg));
- /* First do endiannes-safe read of register value
+ /* First do endianness-safe read of register value
* then convert it to binary buffer for further
* field extraction */
* Write 4-byte instruction to memory. This is like target_write_u32, however
* in case of little endian ARC instructions are in middle endian format, not
* little endian, so different type of conversion should be done.
- * Middle endinan: instruction "aabbccdd", stored as "bbaaddcc"
+ * Middle endian: instruction "aabbccdd", stored as "bbaaddcc"
*/
int arc_write_instruction_u32(struct target *target, uint32_t address,
uint32_t instr)
return retval;
}
-/* Helper function which swiches core to single_step mode by
+/* Helper function which switches core to single_step mode by
* doing aux r/w operations. */
int arc_config_step(struct target *target, int enable_step)
{
.arch_state = arc_arch_state,
- /* TODO That seems like something similiar to metaware hostlink, so perhaps
+ /* TODO That seems like something similar to metaware hostlink, so perhaps
* we can exploit this in the future. */
.target_request_data = NULL,
int e = JIM_OK;
if ((type == CFG_ADD_REG_TYPE_STRUCT && goi->argc < 3) ||
(type == CFG_ADD_REG_TYPE_FLAG && goi->argc < 2)) {
- Jim_SetResultFormatted(goi->interp, "Not enough argmunets after -flag/-bitfield");
+ Jim_SetResultFormatted(goi->interp, "Not enough arguments after -flag/-bitfield");
return JIM_ERR;
}
end_pos = start_pos;
- /* Check if any argnuments remain,
+ /* Check if any arguments remain,
* set bitfields[cur_field].end if flag is multibit */
if (goi->argc > 0)
/* Check current argv[0], if it is equal to "-flag",
int e = JIM_OK;
- /* Check if the amount of argnuments is not zero */
+ /* Check if the amount of arguments is not zero */
if (goi.argc <= 0) {
- Jim_SetResultFormatted(goi.interp, "The command has no argnuments");
+ Jim_SetResultFormatted(goi.interp, "The command has no arguments");
return JIM_ERR;
}
unsigned int fields_sz = (goi.argc - 2) / 3;
unsigned int cur_field = 0;
- /* Tha maximum amount of bitfilds is 32 */
+ /* The maximum amount of bitfields is 32 */
if (fields_sz > 32) {
Jim_SetResultFormatted(goi.interp, "The amount of bitfields exceed 32");
return JIM_ERR;
int e = JIM_OK;
- /* Check if the amount of argnuments is not zero */
+ /* Check if the amount of arguments is not zero */
if (goi.argc <= 0) {
- Jim_SetResultFormatted(goi.interp, "The command has no argnuments");
+ Jim_SetResultFormatted(goi.interp, "The command has no arguments");
return JIM_ERR;
}
unsigned int fields_sz = (goi.argc - 2) / 4;
unsigned int cur_field = 0;
- /* Tha maximum amount of bitfilds is 32 */
+ /* The maximum amount of bitfields is 32 */
if (fields_sz > 32) {
Jim_SetResultFormatted(goi.interp, "The amount of bitfields exceed 32");
return JIM_ERR;
}
/* There is no architecture number that we could treat as invalid, so
- * separate variable requried to ensure that arch num has been set. */
+ * separate variable required to ensure that arch num has been set. */
bool arch_num_set = false;
const char *type_name = "int"; /* Default type */
int type_name_len = strlen(type_name);
int e = ERROR_OK;
/* At least we need to specify 4 parameters: name, number and gdb_feature,
- * which means there should be 6 arguments. Also there can be additional paramters
+ * which means there should be 6 arguments. Also there can be additional parameters
* "-type <type>", "-g" and "-core" or "-bcr" which makes maximum 10 parameters. */
if (goi.argc < 6 || goi.argc > 10) {
free_reg_desc(reg);
Jim_SetResultFormatted(goi.interp,
- "Should be at least 6 argnuments and not greater than 10: "
+ "Should be at least 6 arguments and not greater than 10: "
" -name <name> -num <num> -feature <gdb_feature> "
" [-type <type_name>] [-core|-bcr] [-g].");
return JIM_ERR;
.usage = "arc add-reg -name <string> -num <int> -feature <string> [-gdbnum <int>] "
"[-core|-bcr] [-type <type_name>] [-g]",
.help = "Add new register. Name, architectural number and feature name "
- "are requried options. GDB regnum will default to previous register "
+ "are required options. GDB regnum will default to previous register "
"(gdbnum + 1) and shouldn't be specified in most cases. Type "
"defaults to default GDB 'int'.",
},
assert(jtag_info->tap);
assert(buffer);
- /* first writin code(0x8) of jtag status register in IR */
+ /* first writing code(0x8) of jtag status register in IR */
arc_jtag_enque_write_ir(jtag_info, ARC_JTAG_STATUS_REG);
/* Now reading dr performs jtag status register read */
arc_jtag_enque_read_dr(jtag_info, buffer, TAP_IDLE);
else
arc_jtag_enque_read_dr(jtag_info, read_buffer + i * 4, TAP_IDLE);
}
- /* To prevent pollution of next regiter due to optimization it is necessary *
+ /* To prevent pollution of next register due to optimization it is necessary *
* to reset transaction */
arc_jtag_enque_reset_transaction(jtag_info);
}
/* We will read data from memory, so we need to flush the cache. */
CHECK_RETVAL(arc_cache_flush(target));
- /* non-word writes are less common, than 4-byte writes, so I suppose we can
- * allowe ourselves to write this in a cycle, instead of calling arc_jtag
+ /* non-word writes are less common than 4-byte writes, so I suppose we can
+ * allow ourselves to write this in a cycle, instead of calling arc_jtag
* with count > 1. */
for (i = 0; i < count; i++) {
/* We can read only word at word-aligned address. Also *jtag_read_memory
/* We will read data from memory, so we need to flush the cache. */
CHECK_RETVAL(arc_cache_flush(target));
- /* non-word writes are less common, than 4-byte writes, so I suppose we can
- * allowe ourselves to write this in a cycle, instead of calling arc_jtag
+ /* non-word writes are less common than 4-byte writes, so I suppose we can
+ * allow ourselves to write this in a cycle, instead of calling arc_jtag
* with count > 1. */
for (i = 0; i < count; i++) {
/* See comment in arc_mem_write_block16 for details. Since it is a byte
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
- /* correct endianess if we have word or hword access */
+ /* correct endianness if we have word or hword access */
if (size > 1) {
/*
* arc_..._write_mem with size 4/2 requires uint32_t/uint16_t
* shadowed registers, and support for the Thumb instruction set.
*
* Processor differences include things like presence or absence of MMU
- * and cache, pipeline sizes, use of a modified Harvard Architecure
- * (with separate instruction and data busses from the CPU), support
+ * and cache, pipeline sizes, use of a modified Harvard Architecture
+ * (with separate instruction and data buses from the CPU), support
* for cpu clock gating during idle, and more.
*/
/**
* Clears the halt condition for an ARM7/9 target. If it isn't coming out of
- * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
+ * reset and if DBGRQ is used, it is programmed to be deasserted. If the reset
* vector catch was used, it is restored. Otherwise, the control value is
* restored and the watchpoint unit is restored if it was in use.
*
/**
* flag to give info about cache manipulation during debug :
* "0" - cache lines are invalidated "on the fly", for affected addresses.
- * This is prefered from performance point of view.
+ * This is preferred from performance point of view.
* "1" - cache is invalidated and switched off on debug_entry, and switched back on on restore.
* It is kept off during debugging.
*/
*/
int nb_idx = (csize / (4*8*NB_CACHE_WAYS)); /* gives nb of lines (indexes) in the cache */
- /* Loop for all segmentde (i.e. ways) */
+ /* Loop for all segments (i.e. ways) */
uint32_t seg;
for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
/* Loop for all indexes */
* is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
* further AP operations will fail. There are two basic methods to avoid
* such overrun errors. One involves polling for status instead of using
- * transaction piplining. The other involves adding delays to ensure the
+ * transaction pipelining. The other involves adding delays to ensure the
* AP has enough time to complete one operation before starting the next
* one. (For JTAG these delays are controlled by memaccess_tck.)
*/
* 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
*/
- /* Reading register for a non-existant AP should not cause an error,
+ /* Reading register for a non-existent AP should not cause an error,
* but just to be sure, try to continue searching if an error does happen.
*/
if ((retval == ERROR_OK) && /* Register read success */
* the Cortex-M implementations).
*/
-/* textual represenation of the condition field
- * ALways (default) is ommitted (empty string) */
+/* textual representation of the condition field
+ * ALways (default) is omitted (empty string) */
static const char *arm_condition_strings[] = {
"EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "", "NV"
};
instruction->instruction_size = 2;
if ((opcode & 0xe000) == 0x0000) {
- /* add/substract register or immediate */
+ /* add/subtract register or immediate */
if ((opcode & 0x1800) == 0x1800)
return evaluate_add_sub_thumb(opcode, address, instruction);
/* shift by immediate */
return evaluate_shift_imm_thumb(opcode, address, instruction);
}
- /* Add/substract/compare/move immediate */
+ /* Add/subtract/compare/move immediate */
if ((opcode & 0xe000) == 0x2000)
return evaluate_data_proc_imm_thumb(opcode, address, instruction);
LOG_WARNING("Jazelle PC adjustment unknown");
break;
default:
- LOG_WARNING("unknow core state");
+ LOG_WARNING("unknown core state");
break;
}
break;
}
/**
- * Read basic registers of the the current context: R0 to R15, and CPSR;
+ * Read basic registers of the current context: R0 to R15, and CPSR;
* sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
* In normal operation this is called on entry to halting debug state,
* possibly after some other operations supporting restore of debug state
/* Store multiple increment after
* Rn: base register
* List: for each bit in list: store register
- * S: in priviledged mode: store user-mode registers
+ * S: in privileged mode: store user-mode registers
* W = 1: update the base register. W = 0: leave the base register untouched
*/
#define ARMV4_5_STMIA(Rn, List, S, W) \
/* Load multiple increment after
* Rn: base register
* List: for each bit in list: store register
- * S: in priviledged mode: store user-mode registers
+ * S: in privileged mode: store user-mode registers
* W = 1: update the base register. W = 0: leave the base register untouched
*/
#define ARMV4_5_LDMIA(Rn, List, S, W) \
}
/*
- * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+ * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
* document # ARM DDI 0406C
*/
armv7a->armv7a_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
};
struct armv7a_cachesize {
- /* cache dimensionning */
+ /* cache dimensioning */
uint32_t linelen;
uint32_t associativity;
uint32_t nsets;
* We assume that target core was chosen correctly. It means if same data
* was handled by two cores, other core will loose the changes. Since it
* is impossible to know (FIXME) which core has correct data, keep in mind
- * that some kind of data lost or korruption is possible.
+ * that some kind of data lost or corruption is possible.
* Possible scenario:
* - core1 loaded and changed data on 0x12345678
* - we halted target and modified same data on core0
.name = "info",
.handler = arm7a_l1_cache_info_cmd,
.mode = COMMAND_ANY,
- .help = "print cache realted information",
+ .help = "print cache related information",
.usage = "",
},
{
.name = "info",
.handler = arm7a_l2x_cache_info_command,
.mode = COMMAND_ANY,
- .help = "print cache realted information",
+ .help = "print cache related information",
.usage = "",
},
{
/** Synchronous output port width */
uint32_t port_size;
- /** Bitmask of currenty enabled ITM stimuli */
+ /** Bitmask of currently enabled ITM stimuli */
uint32_t itm_ter[8];
/** Identifier for multi-source trace stream formatting */
unsigned int trace_bus_id;
ret = 48;
break;
default:
- LOG_INFO("Unknow physicall address size");
+ LOG_INFO("Unknown physical address size");
break;
}
return ret;
armv8->armv8_mmu.ttbcr = ttbcr;
/*
- * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+ * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
* document # ARM DDI 0406C
*/
armv8->armv8_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
if (retval != ERROR_OK)
goto done;
- /* claaer ttrr1_used and ttbr0_mask */
+ /* clear ttrr1_used and ttbr0_mask */
memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
goto done;
break;
default:
- LOG_ERROR("unknow core state");
+ LOG_ERROR("unknown core state");
retval = ERROR_FAIL;
break;
}
struct armv8_cachesize {
uint32_t level_num;
- /* cache dimensionning */
+ /* cache dimensioning */
uint32_t linelen;
uint32_t associativity;
uint32_t nsets;
}
/**
- * Read basic registers of the the current context: R0 to R15, and CPSR;
+ * Read basic registers of the current context: R0 to R15, and CPSR;
* sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
* In normal operation this is called on entry to halting debug state,
* possibly after some other operations supporting restore of debug state
uint8_t ir_out, int ir_len, int rti)
{
if (ir_len > 8) {
- LOG_ERROR("ir_len overflow, maxium is 8");
+ LOG_ERROR("ir_len overflow, maximum is 8");
return ERROR_FAIL;
}
uint32_t dr_out, int dr_len, int rti)
{
if (dr_len > 32) {
- LOG_ERROR("dr_len overflow, maxium is 32");
+ LOG_ERROR("dr_len overflow, maximum is 32");
return ERROR_FAIL;
}
LOG_ERROR("How do I resume into Jazelle state??");
return ERROR_FAIL;
case ARM_STATE_AARCH64:
- LOG_ERROR("Shoudn't be in AARCH64 state");
+ LOG_ERROR("Shouldn't be in AARCH64 state");
return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
return retval;
if (target->dbg_msg_enabled) {
- /* restore DCB_DCRDR - this needs to be in a seperate
+ /* restore DCB_DCRDR - this needs to be in a separate
* transaction otherwise the emulated DCC channel breaks */
if (retval == ERROR_OK)
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
* just step over the instruction with interrupts disabled.
*
* The documentation has no information about this, it was found by observation
- * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
+ * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
* suffer from this problem.
*
* To add some confusion: pc_value has bit 0 always set, while the breakpoint
#define INSTR_JUMP 0x0AF080
/* Effective Addressing Mode Encoding */
#define EAME_R0 0x10
-/* instrcution encoder */
+/* instruction encoder */
/* movep
* s - peripheral space X/Y (X=0,Y=1)
* w - write/read
if (target->state == TARGET_HALTED) {
/* after a reset the cpu jmp to the
* reset vector and need 2 cycles to fill
- * the cache (fetch,decode,excecute)
+ * the cache (fetch,decode,execute)
*/
err = dsp563xx_step_ex(target, 1, 0, 1, 1);
if (err != ERROR_OK)
if (len > 32) {
retval = ERROR_FAIL;
err_check(retval, DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW,
- "dr_len overflow, maxium is 32");
+ "dr_len overflow, maximum is 32");
}
/* TODO what values of len are valid for jtag_add_plain_dr_scan? */
/* can i send as many bits as i want? */
* more complicated routine, which is guaranteed to work, but requires
* a reset. This will complicate comm with the flash module, since
* after a reset clock divisors must be set again.
- * This implementation works most of the time, and is not accesible to the
+ * This implementation works most of the time, and is not accessible to the
* user.
*
* @param target
* Executes the FM calculate signature command. The FM will calculate over the
* data from @address to @address + @words -1. The result is written to a
* register, then read out by this function and returned in @signature. The
- * value @signature may be compared to the the one returned by perl_crc to
+ * value @signature may be compared to the one returned by perl_crc to
* verify the flash was written correctly.
*
* @param target
#define CSR_CONFIG_DBG 0x0f /* Debug Configuration */
#define CSR_CONFIG_MID 0x10 /* Manufacturer ID */
#define CSR_CONFIG_REV 0x11 /* Revision Number */
-#define CSR_CONFIG_MPID 0x12 /* Mulitprocessor ID */
+#define CSR_CONFIG_MPID 0x12 /* Multiprocessor ID */
#define CSR_CONFIG_FREQn 0x13 /* Frequency [0..2] */
#define CSR_CONFIG_TRACE 0x16 /* Trace Configuration */
BR_ENABLE = 0x1, /* Trace has been enabled */
BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
BR_NODEBUG = 0x3, /* ARM has exited for debug state */
- BR_PERIOD = 0x4, /* Peridioc synchronization point (ETM >= v1.2)*/
+ BR_PERIOD = 0x4, /* Periodic synchronization point (ETM >= v1.2)*/
BR_RSVD5 = 0x5, /* reserved */
BR_RSVD6 = 0x6, /* reserved */
BR_RSVD7 = 0x7, /* reserved */
* - asserting DBGRQ doesn't work if target is looping on the undef vector
*
* - the EICE version signature in the COMMS_CTL reg is next to the flow bits
- * not at the top, and rather meaningless due to existing discrepencies
+ * not at the top, and rather meaningless due to existing discrepancies
*
* - the DCC channel is half duplex (only one FIFO for both directions) with
* seemingly no proper flow control.
for (section = 0; section < image->num_sections; section++)
image->sections[section].base_address += image->base_address;
/* we're done relocating. The two statements below are mainly
- * for documenation purposes: stop anyone from empirically
+ * for documentation purposes: stop anyone from empirically
* thinking they should use these values henceforth. */
image->base_address = 0;
image->base_address_set = 0;
/*
* we keep reg_cache in sync with hardware at halt/resume time, we avoid
- * writing to real hardware here bacause pm_regs reflects the hardware
+ * writing to real hardware here because pm_regs reflects the hardware
* while we are halted then reg_cache syncs with hw on resume
* TODO - in order for "reg eip force" to work it assume get/set reads
* and writes from hardware, may be other reasons also because generally
}
static const struct reg_arch_type lakemont_reg_type = {
- /* these get called if reg_cache doesnt have a "valid" value
+ /* these get called if reg_cache doesn't have a "valid" value
* of an individual reg eg "reg eip" but not for "reg" block
*/
.get = lakemont_get_core_reg,
struct x86_32_common *x86_32 = target_to_x86_32(t);
struct lakemont_core_reg *arch_info;
arch_info = x86_32->cache->reg_list[reg].arch_info;
- x86_32->flush = 0; /* dont flush scans till we have a batch */
+ x86_32->flush = 0; /* don't flush scans till we have a batch */
if (submit_reg_pir(t, reg) != ERROR_OK)
return ERROR_FAIL;
if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
arch_info->op,
regval);
- x86_32->flush = 0; /* dont flush scans till we have a batch */
+ x86_32->flush = 0; /* don't flush scans till we have a batch */
if (submit_reg_pir(t, reg) != ERROR_OK)
return ERROR_FAIL;
if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
if (bp != NULL) {
t->debug_reason = DBG_REASON_BREAKPOINT;
if (bp->type == BKPT_SOFT) {
- /* The EIP is now pointing the the next byte after the
+ /* The EIP is now pointing the next byte after the
* breakpoint instruction. This needs to be corrected.
*/
buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
break; /* no more config registers implemented */
}
else
- return ERROR_OK; /* already succesfully read */
+ return ERROR_OK; /* already successfully read */
LOG_DEBUG("read %"PRId32" config registers", ejtag_info->config_regs);
/** Returns the kernel segment base of a given address */
#define KSEGX(a) ((a) & 0xe0000000)
-/** CP0 CONFIG regites fields */
+/** CP0 CONFIG register fields */
#define MIPS32_CONFIG0_KU_SHIFT 25
#define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT)
return ERROR_JTAG_DEVICE_ERROR;
}
} else
- if (code_count > 10) { /* enough, abandone */
+ if (code_count > 10) { /* enough, abandon */
LOG_DEBUG("execution abandoned, store pending: %d", store_pending);
return ERROR_JTAG_DEVICE_ERROR;
}
fetch_addr += 4;
scan_count++;
- /* check if previous intrucction is a store instruction at dmesg */
+ /* check if previous instruction is a store instruction at dmesg */
if (i > 0 && ctx->pracc_list[i - 1].addr) {
uint32_t store_addr = ctx->pracc_list[i - 1].addr;
ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32);
* If we are in the cacheable region and cache is activated,
* we must clean D$ (if Cache Coherency Attribute is set to 3) + invalidate I$ after we did the write,
* so that changes do not continue to live only in D$ (if CCA = 3), but to be
- * replicated in I$ also (maybe we wrote the istructions)
+ * replicated in I$ also (maybe we wrote the instructions)
*/
uint32_t conf = 0;
int cached = 0;
}
/**
- * Check cachablitiy bits coherency algorithm
+ * Check cacheability bits coherency algorithm
* is the region cacheable or uncached.
* If cacheable we have to synchronize the cache
*/
int retval;
int code_count;
int store_count;
- int max_code; /* max intstructions with currently allocated memory */
+ int max_code; /* max instructions with currently allocated memory */
pa_list *pracc_list; /* Code and store addresses at dmseg */
};
* @param[in] cp0_reg Number of copro C0 register we want to read
* @param[in] cp0_sel Select for the given C0 register
*
- * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
+ * @return ERROR_OK on Success, ERROR_FAIL otherwise
*/
int mips32_cp0_read(struct mips_ejtag *ejtag_info,
uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
* @param[in] cp0_reg Number of copro C0 register we want to write to
* @param[in] cp0_sel Select for the given C0 register
*
- * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
+ * @return ERROR_OK on Success, ERROR_FAIL otherwise
*/
int mips32_cp0_write(struct mips_ejtag *ejtag_info,
uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
return ctx.retval;
}
-/* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
+/* mips_ejtag_init_mmr - assign Memory-Mapped Registers depending
* on EJTAG version.
*/
static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
if (ejtag_info->endianness && isa_req)
sdbbp32_instr = SWAP16(sdbbp32_instr);
- if ((breakpoint->address & 3) == 0) { /* word alligned */
+ if ((breakpoint->address & 3) == 0) { /* word aligned */
retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
return retval;
/**
- * target_read_memory() gets us data in _target_ endianess.
+ * target_read_memory() gets us data in _target_ endianness.
* If we want to use this data on the host for comparisons with some macros
- * we must first transform it to _host_ endianess using target_buffer_get_u16().
+ * we must first transform it to _host_ endianness using target_buffer_get_u16().
*/
if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
retval = target_write_memory(target, breakpoint->address, 4, 1,
if (retval != ERROR_OK)
return retval;
}
- } else { /* 16bit alligned */
+ } else { /* 16bit aligned */
retval = target_read_memory(target, breakpoint->address, 2, 2, current_instr);
if (retval != ERROR_OK)
return retval;
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
- /** correct endianess if we have word or hword access */
+ /** correct endianness if we have word or hword access */
void *t = NULL;
if (size > 1) {
/* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
aice_write_register(aice, IR2, val_ir2);
}
- /* get origianl DT bit and set to current state let debugger has same memory view
+ /* get original DT bit and set to current state let debugger has same memory view
PSW.IT MUST be turned off. Otherwise, DIM could not operate normally. */
aice_read_register(aice, IR1, &val_ir1);
modified_psw = val_ir0 | (val_ir1 & 0x80);
LOG_WARNING("Debug IF CPU control reg read failure.");
/* Try once to restart the JTAG infrastructure -
quite possibly the board has just been reset. */
- LOG_WARNING("Resetting JTAG TAP state and reconnectiong to debug IF.");
+ LOG_WARNING("Resetting JTAG TAP state and reconnecting to debug IF.");
du_core->or1k_jtag_init(&or1k->jtag);
LOG_WARNING("...attempt %d of %d", tries, RETRIES_MAX);
int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_NOT_RESET);
if (retval != ERROR_OK) {
- LOG_ERROR("Error while desasserting RESET");
+ LOG_ERROR("Error while deasserting RESET");
return retval;
}
int *out_len, unsigned char *out_buffer,
int *in_len, unsigned char *in_buffer)
{
- LOG_DEBUG("JSP transfert");
+ LOG_DEBUG("JSP transfer");
int retval;
if (!jtag_info->or1k_jtag_inited)
/* You can use a custom JTAG controller to discover transactions
* necessary to enumerate all Virtual JTAG megafunction instances
- * from your design atruntime. All SLD nodes and the virtual JTAG
+ * from your design at runtime. All SLD nodes and the virtual JTAG
* registers that they contain are targeted by two Instruction Register
* values, USER0 and USER1.
*
COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &testval_read, GDB_REGNO_ZERO + i),
"GPR Reads should be supported.");
if (riscv_xlen(target) > 32) {
- /* Dummy comment to satisfy linter, since removing the brances here doesn't actually compile. */
+ /* Dummy comment to satisfy linter, since removing the branches here doesn't actually compile. */
COMPLIANCE_TEST(testval == testval_read, "GPR Reads and writes should be supported.");
} else {
- /* Dummy comment to satisfy linter, since removing the brances here doesn't actually compile. */
+ /* Dummy comment to satisfy linter, since removing the branches here doesn't actually compile. */
COMPLIANCE_TEST((testval & 0xFFFFFFFF) == testval_read, "GPR Reads and writes should be supported.");
}
}
* without requiring multiple targets. */
/* When using the RTOS to debug, this selects the hart that is currently being
- * debugged. This doesn't propogate to the hardware. */
+ * debugged. This doesn't propagate to the hardware. */
void riscv_set_all_rtos_harts(struct target *target);
void riscv_set_rtos_hartid(struct target *target, int hartid);
/* Lists the number of harts in the system, which are assumed to be
- * concecutive and start with mhartid=0. */
+ * consecutive and start with mhartid=0. */
int riscv_count_harts(struct target *target);
/* Returns TRUE if the target has the given register on the given hart. */
{
struct semihosting *semihosting = target->semihosting;
if (!semihosting) {
- /* Silently ignore if the semhosting field was not set. */
+ /* Silently ignore if the semihosting field was not set. */
return ERROR_OK;
}
"semihosting: *** application exited normally ***\n");
}
} else if (semihosting->param == ADP_STOPPED_RUN_TIME_ERROR) {
- /* Chosen more or less arbitrarly to have a nicer message,
+ /* Chosen more or less arbitrarily to have a nicer message,
* otherwise all other return the same exit code 1. */
if (!gdb_actual_connections)
exit(1);
continue
}
- # Wait upto 1 second for target to halt. Why 1sec? Cause
+ # Wait up to 1 second for target to halt. Why 1sec? Cause
# the JTAG tap reset signal might be hooked to a slow
# resistor/capacitor circuit - and it might take a while
# to charge
if (target->reset_halt)
return ERROR_OK;
- /* Instead of going thrugh saving context, polling and
+ /* Instead of going through saving context, polling and
then resuming target again just clear stall and proceed. */
target->state = TARGET_RUNNING;
return stm8_exit_debug(target);
* @param address Optionally used as the program counter.
* @param handle_breakpoints True iff breakpoints at the resumption PC
* should be skipped. (For example, maybe execution was stopped by
- * such a breakpoint, in which case it would be counterprodutive to
+ * such a breakpoint, in which case it would be counterproductive to
* let it re-trigger.
* @param debug_execution False if all working areas allocated by OpenOCD
* should be released and/or restored to their original contents.
return ERROR_OK;
}
-/* Equvivalent Tcl code arp_examine_one is in src/target/startup.tcl
+/* Equivalent Tcl code arp_examine_one is in src/target/startup.tcl
* Keep in sync */
int target_examine_one(struct target *target)
{
uint32_t offset = 0;
uint32_t length = buf_cnt;
- /* DANGER!!! beware of unsigned comparision here!!! */
+ /* DANGER!!! beware of unsigned comparison here!!! */
if ((image.sections[i].base_address + buf_cnt >= min_address) &&
(image.sections[i].base_address < max_address)) {
}
switch (n->value) {
case TCFG_TYPE:
- /* not setable */
+ /* not settable */
if (goi->isconfigure) {
Jim_SetResultFormatted(goi->interp,
"not settable: %s", n->name);
retval = 0;
LOG_DEBUG("%d", argc);
/* argv[1] = target to associate in smp
- * argv[2] = target to assoicate in smp
+ * argv[2] = target to associate in smp
* argv[3] ...
*/
uint32_t offset = 0;
uint32_t length = buf_cnt;
- /* DANGER!!! beware of unsigned comparision here!!! */
+ /* DANGER!!! beware of unsigned comparison here!!! */
if ((image.sections[i].base_address + buf_cnt >= min_address) &&
(image.sections[i].base_address < max_address)) {
return ERROR_OK;
}
- /* see if reciever is already registered */
+ /* see if receiver is already registered */
if (find_debug_msg_receiver(CMD_CTX, target) != NULL)
receiving = 1;
retval = xscale_debug_entry(target);
} else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
LOG_USER("error while polling TX register, reset CPU");
- /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
+ /* here we "lie" so GDB won't get stuck and a reset can be performed */
target->state = TARGET_HALTED;
}
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4;
break;
- case 0x5: /* Vector trap occured */
+ case 0x5: /* Vector trap occurred */
target->debug_reason = DBG_REASON_BREAKPOINT;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4;
} else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
/* can't (explicitly) read from TXRXCTRL register */
return ERROR_OK;
- } else {/* Other DBG registers have to be transfered by the debug handler
+ } else {/* Other DBG registers have to be transferred by the debug handler
* send CP read request (command 0x40) */
xscale_send_u32(target, 0x40);
} else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
/* can't (explicitly) write to TXRXCTRL register */
return ERROR_OK;
- } else {/* Other DBG registers have to be transfered by the debug handler
+ } else {/* Other DBG registers have to be transferred by the debug handler
* send CP write request (command 0x41) */
xscale_send_u32(target, 0x41);
current_pc = chkpt_reg;
else if (current_pc != chkpt_reg) /* sanity check */
LOG_WARNING("trace is suspect: checkpoint register "
- "inconsistent with adddress from image");
+ "inconsistent with address from image");
}
if (current_pc == 0)
arm = &xscale->arm;
- /* store architecture specfic data */
+ /* store architecture specific data */
xscale->common_magic = XSCALE_COMMON_MAGIC;
/* PXA3xx with 11 bit IR shifts the JTAG instructions */
Code Review / openocd.git / commitdiff