- Replace ')\(!=\)\(\w\)' with ') \1 \2'.
- Replace '\(\w\)\(!=\)(' with '\1 \2 ('.
- Replace '\(\w\)\(!=\)\(\w\)' with '\1 \2 \3'.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2363
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
44 files changed:
int timeout = (len / 20480 + 1) * 1000; /*asume 20 KB/s*/
retval=loadDriver(info);
int timeout = (len / 20480 + 1) * 1000; /*asume 20 KB/s*/
retval=loadDriver(info);
+ if (retval != ERROR_OK)
return retval;
uint32_t flashErr;
return retval;
uint32_t flashErr;
+ if (retval != ERROR_OK)
return retval;
if (flashErr != 0x0)
return retval;
if (flashErr != 0x0)
int timeout = (chunk / 20480 + 1) * 1000; /*asume 20 KB/s + 1 second*/
retval=loadDriver(info);
int timeout = (chunk / 20480 + 1) * 1000; /*asume 20 KB/s + 1 second*/
retval=loadDriver(info);
+ if (retval != ERROR_OK)
return retval;
uint32_t buffer;
return retval;
uint32_t buffer;
+ if (retval != ERROR_OK)
int retval;
retval=bank->driver->write(bank, buffer, offset, count);
int retval;
retval=bank->driver->write(bank, buffer, offset, count);
+ if (retval != ERROR_OK)
{
LOG_ERROR("error writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32 " (%d)",
bank->base, offset, retval);
{
LOG_ERROR("error writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32 " (%d)",
bank->base, offset, retval);
int retval;
retval=bank->driver->erase(bank, first, last);
int retval;
retval=bank->driver->erase(bank, first, last);
+ if (retval != ERROR_OK)
{
LOG_ERROR("failed erasing sectors %d to %d (%d)", first, last, retval);
}
{
LOG_ERROR("failed erasing sectors %d to %d (%d)", first, last, retval);
}
int retval;
retval=bank->driver->protect(bank, set, first, last);
int retval;
retval=bank->driver->protect(bank, set, first, last);
+ if (retval != ERROR_OK)
{
LOG_ERROR("failed setting protection for areas %d to %d (%d)", first, last, retval);
}
{
LOG_ERROR("failed setting protection for areas %d to %d (%d)", first, last, retval);
}
return ERROR_FAIL;
}
err = flash_driver_write(bank, chunk, address - bank->base + wrote, cur_size);
return ERROR_FAIL;
}
err = flash_driver_write(bank, chunk, address - bank->base + wrote, cur_size);
return err;
err = target_read_buffer(target, address + wrote, cur_size, readback);
return err;
err = target_read_buffer(target, address + wrote, cur_size, readback);
LOG_DEBUG("checksum: 0x%8.8" PRIx32, checksum);
uint32_t original_value=buf_get_u32(buffer + (5 * 4), 0, 32);
LOG_DEBUG("checksum: 0x%8.8" PRIx32, checksum);
uint32_t original_value=buf_get_u32(buffer + (5 * 4), 0, 32);
- if (original_value!=checksum)
+ if (original_value != checksum)
{
LOG_WARNING("Verification will fail since checksum in image(0x%8.8" PRIx32 ") written to flash was different from calculated vector checksum(0x%8.8" PRIx32 ").",
original_value, checksum);
{
LOG_WARNING("Verification will fail since checksum in image(0x%8.8" PRIx32 ") written to flash was different from calculated vector checksum(0x%8.8" PRIx32 ").",
original_value, checksum);
chksum=OCL_CHKS_INIT;
for (bi=0; bi<bi_end; bi++) chksum^=buffer[bi]=dcc_rd();
chksum=OCL_CHKS_INIT;
for (bi=0; bi<bi_end; bi++) chksum^=buffer[bi]=dcc_rd();
- if (dcc_rd()!=chksum) {
+ if (dcc_rd() != chksum) {
dcc_wr(OCL_CHKS_FAIL);
return;
}
dcc_wr(OCL_CHKS_FAIL);
return;
}
- if ((result=flash_erase_plane(0))!=FLASH_STAT_OK) return result;
+ if ((result=flash_erase_plane(0)) != FLASH_STAT_OK) return result;
/* the second flash controller, if any */
if (flash_page_count>1024) result=flash_erase_plane(0x10);
/* the second flash controller, if any */
if (flash_page_count>1024) result=flash_erase_plane(0x10);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
- if ((retval=target_write_buffer(target, pic32mx_info->write_algorithm->address, sizeof(pic32mx_flash_write_code), pic32mx_flash_write_code))!=ERROR_OK)
+ if ((retval=target_write_buffer(target, pic32mx_info->write_algorithm->address, sizeof(pic32mx_flash_write_code), pic32mx_flash_write_code)) != ERROR_OK)
- if ((retval = target_write_buffer(target, source->address, buffer_size, buffer))!=ERROR_OK) {
+ if ((retval = target_write_buffer(target, source->address, buffer_size, buffer)) != ERROR_OK) {
LOG_ERROR("Failed to write row buffer (%d words) to RAM", (int)(buffer_size/4));
break;
}
LOG_ERROR("Failed to write row buffer (%d words) to RAM", (int)(buffer_size/4));
break;
}
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
- if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
+ if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
return retval;
/* memory buffer */
return retval;
/* memory buffer */
{
uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
{
uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
- if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
+ if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer)) != ERROR_OK)
break;
buf_set_u32(reg_params[0].value, 0, 32, source->address);
break;
buf_set_u32(reg_params[0].value, 0, 32, source->address);
if (str9x_info->bank1)
{
adr = bank1start + 0x18;
if (str9x_info->bank1)
{
adr = bank1start + 0x18;
- if ((retval=target_write_u16(target, adr, 0x90))!=ERROR_OK)
+ if ((retval=target_write_u16(target, adr, 0x90)) != ERROR_OK)
- if ((retval=target_read_u16(target, adr, &hstatus))!=ERROR_OK)
+ if ((retval=target_read_u16(target, adr, &hstatus)) != ERROR_OK)
else
{
adr = bank1start + 0x14;
else
{
adr = bank1start + 0x14;
- if ((retval=target_write_u16(target, adr, 0x90))!=ERROR_OK)
+ if ((retval=target_write_u16(target, adr, 0x90)) != ERROR_OK)
- if ((retval=target_read_u32(target, adr, &status))!=ERROR_OK)
+ if ((retval=target_read_u32(target, adr, &status)) != ERROR_OK)
else
{
adr = bank1start + 0x10;
else
{
adr = bank1start + 0x10;
- if ((retval=target_write_u16(target, adr, 0x90))!=ERROR_OK)
+ if ((retval=target_write_u16(target, adr, 0x90)) != ERROR_OK)
- if ((retval=target_read_u16(target, adr, &hstatus))!=ERROR_OK)
+ if ((retval=target_read_u16(target, adr, &hstatus)) != ERROR_OK)
}
/* read array command */
}
/* read array command */
- if ((retval=target_write_u16(target, adr, 0xFF))!=ERROR_OK)
+ if ((retval=target_write_u16(target, adr, 0xFF)) != ERROR_OK)
adr = bank->base + bank->sectors[i].offset;
/* erase sectors */
adr = bank->base + bank->sectors[i].offset;
/* erase sectors */
- if ((retval=target_write_u16(target, adr, erase_cmd))!=ERROR_OK)
+ if ((retval=target_write_u16(target, adr, erase_cmd)) != ERROR_OK)
- if ((retval=target_write_u16(target, adr, 0xD0))!=ERROR_OK)
+ if ((retval=target_write_u16(target, adr, 0xD0)) != ERROR_OK)
{
return retval;
}
/* get status */
{
return retval;
}
/* get status */
- if ((retval=target_write_u16(target, adr, 0x70))!=ERROR_OK)
+ if ((retval=target_write_u16(target, adr, 0x70)) != ERROR_OK)
{
return retval;
}
int timeout;
for (timeout=0; timeout<1000; timeout++) {
{
return retval;
}
int timeout;
for (timeout=0; timeout<1000; timeout++) {
- if ((retval=target_read_u8(target, adr, &status))!=ERROR_OK)
+ if ((retval=target_read_u8(target, adr, &status)) != ERROR_OK)
}
/* clear status, also clear read array */
}
/* clear status, also clear read array */
- if ((retval=target_write_u16(target, adr, 0x50))!=ERROR_OK)
+ if ((retval=target_write_u16(target, adr, 0x50)) != ERROR_OK)
{
return retval;
}
/* read array command */
{
return retval;
}
/* read array command */
- if ((retval=target_write_u16(target, adr, 0xFF))!=ERROR_OK)
+ if ((retval=target_write_u16(target, adr, 0xFF)) != ERROR_OK)
const char *t2="";
const char *t3="";
/* maximum of two levels :-) */
const char *t2="";
const char *t3="";
/* maximum of two levels :-) */
{
t1=c->parent->name;
t2="_";
{
t1=c->parent->name;
t2="_";
Jim_Obj *cmd_list=Jim_NewListObj(interp, NULL, 0);
/* maximum of two levels :-) */
Jim_Obj *cmd_list=Jim_NewListObj(interp, NULL, 0);
/* maximum of two levels :-) */
{
Jim_ListAppendElement(interp, cmd_list, Jim_NewStringObj(interp, c->parent->name, -1));
}
{
Jim_ListAppendElement(interp, cmd_list, Jim_NewStringObj(interp, c->parent->name, -1));
}
const char *t2="";
const char *t3="";
/* maximum of two levels :-) */
const char *t2="";
const char *t3="";
/* maximum of two levels :-) */
{
t1=c->parent->name;
t2=" ";
{
t1=c->parent->name;
t2=" ";
Jim_DeleteAssocData(interp, "context");
}
if (retcode == JIM_ERR) {
Jim_DeleteAssocData(interp, "context");
}
if (retcode == JIM_ERR) {
- if (retval!=ERROR_COMMAND_CLOSE_CONNECTION)
+ if (retval != ERROR_COMMAND_CLOSE_CONNECTION)
{
/* We do not print the connection closed error message */
Jim_PrintErrorMessage(interp);
{
/* We do not print the connection closed error message */
Jim_PrintErrorMessage(interp);
va_list ap;
va_start(ap, format);
string = alloc_vprintf(format, ap);
va_list ap;
va_start(ap, format);
string = alloc_vprintf(format, ap);
{
retval=command_run_line(context, string);
}
{
retval=command_run_line(context, string);
}
int handle_fast_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
int handle_fast_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
return ERROR_COMMAND_SYNTAX_ERROR;
fast_and_dangerous = strcmp("enable", args[0])==0;
return ERROR_COMMAND_SYNTAX_ERROR;
fast_and_dangerous = strcmp("enable", args[0])==0;
while (*cfg)
{
retval=command_run_line(cmd_ctx, *cfg);
while (*cfg)
{
retval=command_run_line(cmd_ctx, *cfg);
+ if (retval != ERROR_OK)
LOG_ERROR("Can't open %s\n", fileName);
return ERROR_FAIL;
}
LOG_ERROR("Can't open %s\n", fileName);
return ERROR_FAIL;
}
- if (fseek(pFile, 0, SEEK_END)!=0)
+ if (fseek(pFile, 0, SEEK_END) != 0)
{
LOG_ERROR("Can't open %s\n", fileName);
fclose(pFile);
{
LOG_ERROR("Can't open %s\n", fileName);
fclose(pFile);
- if (fseek(pFile, 0, SEEK_SET)!=0)
+ if (fseek(pFile, 0, SEEK_SET) != 0)
{
LOG_ERROR("Can't open %s\n", fileName);
fclose(pFile);
{
LOG_ERROR("Can't open %s\n", fileName);
fclose(pFile);
for (i = 1; i < argc; i++)
{
for (i = 1; i < argc; i++)
{
- if (fwrite(args[i], 1, strlen(args[i]), config_file)!=strlen(args[i]))
+ if (fwrite(args[i], 1, strlen(args[i]), config_file) != strlen(args[i]))
break;
if (i != argc - 1)
{
break;
if (i != argc - 1)
{
- if (fwrite(" ", 1, 1, config_file)!=1)
+ if (fwrite(" ", 1, 1, config_file) != 1)
- if ((retval==ERROR_OK)&&(fwrite(((char *)data)+pos, 1, chunk, f)!=chunk))
+ if ((retval==ERROR_OK)&&(fwrite(((char *)data)+pos, 1, chunk, f) != chunk))
retval = ERROR_INVALID_ARGUMENTS;
if (retval != ERROR_OK)
retval = ERROR_INVALID_ARGUMENTS;
if (retval != ERROR_OK)
{
//if (ifr->ifr_addr.sa_family == AF_INET)
{
{
//if (ifr->ifr_addr.sa_family == AF_INET)
{
- if (strcmp("eth0", ifr->ifr_name)!=0)
+ if (strcmp("eth0", ifr->ifr_name) != 0)
continue;
strncpy(ifreq.ifr_name, ifr->ifr_name, sizeof(ifreq.ifr_name));
if (ioctl(SockFD, SIOCGIFHWADDR, &ifreq) < 0)
continue;
strncpy(ifreq.ifr_name, ifr->ifr_name, sizeof(ifreq.ifr_name));
if (ioctl(SockFD, SIOCGIFHWADDR, &ifreq) < 0)
static jim_wide JimPowWide(jim_wide b, jim_wide e)
{
jim_wide i, res = 1;
static jim_wide JimPowWide(jim_wide b, jim_wide e)
{
jim_wide i, res = 1;
- if ((b==0 && e!=0) || (e<0)) return 0;
+ if ((b==0 && e != 0) || (e<0)) return 0;
for (i=0; i<e; i++) {res *= b;}
return res;
}
for (i=0; i<e; i++) {res *= b;}
return res;
}
case JIM_EXPROP_LSHIFT: wC = wA<<wB; break;
case JIM_EXPROP_RSHIFT: wC = wA>>wB; break;
case JIM_EXPROP_NUMEQ: wC = wA==wB; break;
case JIM_EXPROP_LSHIFT: wC = wA<<wB; break;
case JIM_EXPROP_RSHIFT: wC = wA>>wB; break;
case JIM_EXPROP_NUMEQ: wC = wA==wB; break;
- case JIM_EXPROP_NUMNE: wC = wA!=wB; break;
+ case JIM_EXPROP_NUMNE: wC = wA != wB; break;
case JIM_EXPROP_BITAND: wC = wA&wB; break;
case JIM_EXPROP_BITXOR: wC = wA^wB; break;
case JIM_EXPROP_BITOR: wC = wA|wB; break;
case JIM_EXPROP_BITAND: wC = wA&wB; break;
case JIM_EXPROP_BITXOR: wC = wA^wB; break;
case JIM_EXPROP_BITOR: wC = wA|wB; break;
case JIM_EXPROP_LTE: dC = dA<=dB; break;
case JIM_EXPROP_GTE: dC = dA>=dB; break;
case JIM_EXPROP_NUMEQ: dC = dA==dB; break;
case JIM_EXPROP_LTE: dC = dA<=dB; break;
case JIM_EXPROP_GTE: dC = dA>=dB; break;
case JIM_EXPROP_NUMEQ: dC = dA==dB; break;
- case JIM_EXPROP_NUMNE: dC = dA!=dB; break;
+ case JIM_EXPROP_NUMNE: dC = dA != dB; break;
case JIM_EXPROP_LOGICAND_LEFT:
if (dA == 0) {
i += (int)dB;
case JIM_EXPROP_LOGICAND_LEFT:
if (dA == 0) {
i += (int)dB;
if (f != NULL)
file = f + 1;
if (f != NULL)
file = f + 1;
- if (strchr(string, '\n')!=NULL)
+ if (strchr(string, '\n') != NULL)
{
if (debug_level >= LOG_LVL_DEBUG)
{
{
if (debug_level >= LOG_LVL_DEBUG)
{
void *clear_malloc(size_t size)
{
void *t = malloc(size);
void *clear_malloc(size_t size)
{
void *t = malloc(size);
{
memset(t, 0x00, size);
}
{
memset(t, 0x00, size);
}
void *fill_malloc(size_t size)
{
void *t = malloc(size);
void *fill_malloc(size_t size)
{
void *t = malloc(size);
{
/* We want to initialize memory to some known bad state. */
/* 0 and 0xff yields 0 and -1 as integers, which often */
{
/* We want to initialize memory to some known bad state. */
/* 0 and 0xff yields 0 and -1 as integers, which often */
bitbang_interface->write(0, tms, tdi);
bitbang_interface->write(0, tms, tdi);
val=bitbang_interface->read();
bitbang_interface->write(1, tms, tdi);
val=bitbang_interface->read();
bitbang_interface->write(1, tms, tdi);
if (field->num_bits>bitq_in_bufsize * 8)
{
/* buffer previously allocated? */
if (field->num_bits>bitq_in_bufsize * 8)
{
/* buffer previously allocated? */
- if (bitq_in_buffer!=NULL)
+ if (bitq_in_buffer != NULL)
{
/* free it */
free(bitq_in_buffer);
{
/* free it */
free(bitq_in_buffer);
out_ptr = field->out_value;
for (bit_cnt = field->num_bits; bit_cnt>1; bit_cnt--)
{
out_ptr = field->out_value;
for (bit_cnt = field->num_bits; bit_cnt>1; bit_cnt--)
{
- bitq_io(0, ( (*out_ptr) & out_mask )!=0, tdo_req);
+ bitq_io(0, ( (*out_ptr) & out_mask ) != 0, tdo_req);
if (out_mask==0x80)
{
out_mask = 0x01;
if (out_mask==0x80)
{
out_mask = 0x01;
- bitq_io(pause, ( (*out_ptr) & out_mask )!=0, tdo_req);
+ bitq_io(pause, ( (*out_ptr) & out_mask ) != 0, tdo_req);
void bitq_cleanup(void)
{
void bitq_cleanup(void)
{
- if (bitq_in_buffer!=NULL)
+ if (bitq_in_buffer != NULL)
{
free(bitq_in_buffer);
bitq_in_buffer = NULL;
{
free(bitq_in_buffer);
bitq_in_buffer = NULL;
- assert(state!=TAP_INVALID);
+ assert(state != TAP_INVALID);
cmd_queue_cur_state = state;
}
cmd_queue_cur_state = state;
}
LOG_ERROR("BUG: TAP_DRSHIFT/IRSHIFT can't be end state. Calling code should use a larger scan field");
}
LOG_ERROR("BUG: TAP_DRSHIFT/IRSHIFT can't be end state. Calling code should use a larger scan field");
}
- if (state!=TAP_INVALID)
+ if (state != TAP_INVALID)
cmd_queue_end_state = state;
return cmd_queue_end_state;
}
cmd_queue_end_state = state;
return cmd_queue_end_state;
}
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
/* examine chain first, as this could discover the real chain layout */
return retval;
/* examine chain first, as this could discover the real chain layout */
if (retval == ERROR_OK)
{
struct jtag_callback_entry *entry;
if (retval == ERROR_OK)
{
struct jtag_callback_entry *entry;
- for (entry=jtag_callback_queue_head; entry!=NULL; entry=entry->next)
+ for (entry=jtag_callback_queue_head; entry != NULL; entry=entry->next)
{
retval=entry->callback(entry->data0, entry->data1, entry->data2, entry->data3);
{
retval=entry->callback(entry->data0, entry->data1, entry->data2, entry->data3);
+ if (retval != ERROR_OK)
#if (BUILD_FT2232_FTD2XX==1 && BUILD_FT2232_LIBFTDI==1)
#error "BUILD_FT2232_FTD2XX && BUILD_FT2232_LIBFTDI are mutually exclusive"
#if (BUILD_FT2232_FTD2XX==1 && BUILD_FT2232_LIBFTDI==1)
#error "BUILD_FT2232_FTD2XX && BUILD_FT2232_LIBFTDI are mutually exclusive"
-#elif (BUILD_FT2232_FTD2XX!=1 && BUILD_FT2232_LIBFTDI!=1)
+#elif (BUILD_FT2232_FTD2XX != 1 && BUILD_FT2232_LIBFTDI != 1)
#error "BUILD_FT2232_FTD2XX || BUILD_FT2232_LIBFTDI must be chosen"
#endif
#error "BUILD_FT2232_FTD2XX || BUILD_FT2232_LIBFTDI must be chosen"
#endif
for (i = 0; i < length; i++)
{
int tms = (i < (length - 1)) ? 0 : 1;
for (i = 0; i < length; i++)
{
int tms = (i < (length - 1)) ? 0 : 1;
- int tdi = (buffer[i / 8] & (1 << (i % 8)))!=0;
+ int tdi = (buffer[i / 8] & (1 << (i % 8))) != 0;
jlink_tap_append_step(tms, tdi);
}
pending_scan_results_length++;
jlink_tap_append_step(tms, tdi);
}
pending_scan_results_length++;
* matter if the operation was executed *before* jtag_execute_queue(),
* jtag_execute_queue() will still return an error code.
*
* matter if the operation was executed *before* jtag_execute_queue(),
* jtag_execute_queue() will still return an error code.
*
- * All jtag_add_xxx() calls that have in_handler!=NULL will have been
+ * All jtag_add_xxx() calls that have in_handler != NULL will have been
* executed when this fn returns, but if what has been queued only
* clocks data out, without reading anything back, then JTAG could
* be running *after* jtag_execute_queue() returns. The API does
* executed when this fn returns, but if what has been queued only
* clocks data out, without reading anything back, then JTAG could
* be running *after* jtag_execute_queue() returns. The API does
if ((presto->status = FT_Read(presto->handle, &presto_data, 1, &ftbytes)) != FT_OK)
return ERROR_JTAG_DEVICE_ERROR;
if ((presto->status = FT_Read(presto->handle, &presto_data, 1, &ftbytes)) != FT_OK)
return ERROR_JTAG_DEVICE_ERROR;
{
LOG_DEBUG("PRESTO reset");
{
LOG_DEBUG("PRESTO reset");
if ((presto->status = FT_Read(presto->handle, &presto_data, 1, &ftbytes)) != FT_OK)
return ERROR_JTAG_DEVICE_ERROR;
if ((presto->status = FT_Read(presto->handle, &presto_data, 1, &ftbytes)) != FT_OK)
return ERROR_JTAG_DEVICE_ERROR;
{
LOG_DEBUG("PRESTO not responding");
return ERROR_JTAG_DEVICE_ERROR;
{
LOG_DEBUG("PRESTO not responding");
return ERROR_JTAG_DEVICE_ERROR;
* args[N-2] = "-endstate"
* args[N-1] = statename
*/
* args[N-2] = "-endstate"
* args[N-1] = statename
*/
- if ((argc < 4) || ((argc % 2)!=0))
+ if ((argc < 4) || ((argc % 2) != 0))
{
Jim_WrongNumArgs(interp, 1, args, "wrong arguments");
return JIM_ERR;
{
Jim_WrongNumArgs(interp, 1, args, "wrong arguments");
return JIM_ERR;
- * Enter state and cause repeat transitions *out* of that state. So if the endState!=state, then
+ * Enter state and cause repeat transitions *out* of that state. So if the endState != state, then
* the transition from state to endState counts as a transition out of state.
*/
static __inline__ void shiftValueInner(const enum tap_state state, const enum tap_state endState, int repeat, cyg_uint32 value)
* the transition from state to endState counts as a transition out of state.
*/
static __inline__ void shiftValueInner(const enum tap_state state, const enum tap_state endState, int repeat, cyg_uint32 value)
ZY1000_POKE(ZY1000_JTAG_BASE+0xc, value);
#if 1
#if TEST_MANUAL()
ZY1000_POKE(ZY1000_JTAG_BASE+0xc, value);
#if 1
#if TEST_MANUAL()
- if ((state==TAP_DRSHIFT)&&(endState!=TAP_DRSHIFT))
+ if ((state==TAP_DRSHIFT)&&(endState != TAP_DRSHIFT))
{
int i;
setCurrentState(state);
{
int i;
setCurrentState(state);
- if ((i==repeat-1)&&(state!=endState))
+ if ((i==repeat-1)&&(state != endState))
- /* Danger!!! if clk!=0 when in
+ /* Danger!!! if clk != 0 when in
* idle in TAP_IDLE, reset halt on str912 will fail.
*/
ZY1000_POKE(ZY1000_JTAG_BASE+0x10, 0x00000001);
* idle in TAP_IDLE, reset halt on str912 will fail.
*/
ZY1000_POKE(ZY1000_JTAG_BASE+0x10, 0x00000001);
cyg_uint32 status;
ZY1000_PEEK(ZY1000_JTAG_BASE+0x10, status);
cyg_uint32 status;
ZY1000_PEEK(ZY1000_JTAG_BASE+0x10, status);
- Jim_SetResult(interp, Jim_NewIntObj(interp, (status&0x80)!=0));
+ Jim_SetResult(interp, Jim_NewIntObj(interp, (status&0x80) != 0));
/* clear JTAG error register */
ZY1000_POKE(ZY1000_JTAG_BASE+0x14, 0x400);
/* clear JTAG error register */
ZY1000_POKE(ZY1000_JTAG_BASE+0x14, 0x400);
+ if ((empty&0x400) != 0)
{
LOG_WARNING("RCLK timeout");
/* the error is informative only as we don't want to break the firmware if there
{
LOG_WARNING("RCLK timeout");
/* the error is informative only as we don't want to break the firmware if there
// figure out where to store the input data
int num_bits=fields[i].num_bits;
// figure out where to store the input data
int num_bits=fields[i].num_bits;
- if (fields[i].in_value!=NULL)
+ if (fields[i].in_value != NULL)
{
inBuffer=fields[i].in_value;
}
{
inBuffer=fields[i].in_value;
}
// we have (num_bits+7)/8 bytes of bits to toggle out.
// bits are pushed out LSB to MSB
value=0;
// we have (num_bits+7)/8 bytes of bits to toggle out.
// bits are pushed out LSB to MSB
value=0;
- if (fields[i].out_value!=NULL)
+ if (fields[i].out_value != NULL)
shiftValueInner(shiftState, pause_state, k, value);
shiftValueInner(shiftState, pause_state, k, value);
{
// data in, LSB to MSB
value=getShiftValue();
{
// data in, LSB to MSB
value=getShiftValue();
/* Give TELNET a way to find out what version this is */
static int handle_version_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
/* Give TELNET a way to find out what version this is */
static int handle_version_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
return ERROR_COMMAND_SYNTAX_ERROR;
command_print(cmd_ctx, OPENOCD_VERSION);
return ERROR_COMMAND_SYNTAX_ERROR;
command_print(cmd_ctx, OPENOCD_VERSION);
static int handle_init_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
static int handle_init_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
return ERROR_COMMAND_SYNTAX_ERROR;
int retval;
return ERROR_COMMAND_SYNTAX_ERROR;
int retval;
return EXIT_FAILURE;
#if BUILD_HTTPD
return EXIT_FAILURE;
#if BUILD_HTTPD
- if (httpd_start()!=ERROR_OK)
+ if (httpd_start() != ERROR_OK)
return EXIT_FAILURE;
#endif
if (ret != ERROR_COMMAND_CLOSE_CONNECTION)
{
command_context_mode(cmd_ctx, COMMAND_EXEC);
return EXIT_FAILURE;
#endif
if (ret != ERROR_COMMAND_CLOSE_CONNECTION)
{
command_context_mode(cmd_ctx, COMMAND_EXEC);
- if (command_run_line(cmd_ctx, "init")!=ERROR_OK)
+ if (command_run_line(cmd_ctx, "init") != ERROR_OK)
return EXIT_FAILURE;
/* handle network connections */
return EXIT_FAILURE;
/* handle network connections */
- *got_data=FD_ISSET(connection->fd, &read_fds)!=0;
+ *got_data=FD_ISSET(connection->fd, &read_fds) != 0;
- if ((retval=check_pending(connection, 0, &gotdata))!=ERROR_OK)
+ if ((retval=check_pending(connection, 0, &gotdata)) != ERROR_OK)
return retval;
if (!gotdata)
break;
return retval;
if (!gotdata)
break;
*/
if (gdb_con->noack_mode)
{
*/
if (gdb_con->noack_mode)
{
- if ((retval=fetch_packet(connection, &checksum_ok, 1, len, buffer))!=ERROR_OK)
+ if ((retval=fetch_packet(connection, &checksum_ok, 1, len, buffer)) != ERROR_OK)
- if ((retval=fetch_packet(connection, &checksum_ok, 0, len, buffer))!=ERROR_OK)
+ if ((retval=fetch_packet(connection, &checksum_ok, 0, len, buffer)) != ERROR_OK)
retval = target_read_buffer(target, addr, len, buffer);
retval = target_read_buffer(target, addr, len, buffer);
- if ((retval!=ERROR_OK)&&!gdb_report_data_abort)
+ if ((retval != ERROR_OK)&&!gdb_report_data_abort)
{
/* TODO : Here we have to lie and send back all zero's lest stack traces won't work.
* At some point this might be fixed in GDB, in which case this code can be removed.
{
/* TODO : Here we have to lie and send back all zero's lest stack traces won't work.
* At some point this might be fixed in GDB, in which case this code can be removed.
p->base, p->size, blocksize);
ram_start=p->base+p->size;
}
p->base, p->size, blocksize);
ram_start=p->base+p->size;
}
{
xml_printf(&retval, &xml, &pos, &size, "<memory type=\"ram\" start=\"0x%x\" length=\"0x%x\"/>\n",
ram_start, 0-ram_start);
{
xml_printf(&retval, &xml, &pos, &size, "<memory type=\"ram\" start=\"0x%x\" length=\"0x%x\"/>\n",
ram_start, 0-ram_start);
log_add_callback(gdb_log_callback, connection);
target_call_event_callbacks(target, TARGET_EVENT_GDB_START);
int retval=gdb_step_continue_packet(connection, target, packet, packet_size);
log_add_callback(gdb_log_callback, connection);
target_call_event_callbacks(target, TARGET_EVENT_GDB_START);
int retval=gdb_step_continue_packet(connection, target, packet, packet_size);
+ if (retval != ERROR_OK)
{
/* we'll never receive a halted condition... issue a false one.. */
gdb_frontend_halted(target, connection);
{
/* we'll never receive a halted condition... issue a false one.. */
gdb_frontend_halted(target, connection);
int argc,
Jim_Obj *const *argv)
{
int argc,
Jim_Obj *const *argv)
{
{
Jim_WrongNumArgs(interp, 1, argv, "method ?args ...?");
return JIM_ERR;
{
Jim_WrongNumArgs(interp, 1, argv, "method ?args ...?");
return JIM_ERR;
Jim_Obj *dict = Jim_GetVariableStr(interp, "httppostdata", 0);
Jim_Obj *dict = Jim_GetVariableStr(interp, "httppostdata", 0);
{
if (Jim_DictKey(interp, dict, keyObj, &value, 0) != JIM_OK)
{
{
if (Jim_DictKey(interp, dict, keyObj, &value, 0) != JIM_OK)
{
}
else if (breakpoint->type == BKPT_SOFT)
{
}
else if (breakpoint->type == BKPT_SOFT)
{
- if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
+ if ((retval=arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
return retval;
/* did we already set this breakpoint? */
return retval;
/* did we already set this breakpoint? */
{
reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
uint32_t t=*((uint32_t *)reg->value);
{
reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
uint32_t t=*((uint32_t *)reg->value);
{
LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
}
{
LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
}
jtag_add_reset(0, 0);
enum reset_types jtag_reset_config = jtag_get_reset_config();
jtag_add_reset(0, 0);
enum reset_types jtag_reset_config = jtag_get_reset_config();
- if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
+ if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
{
LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
/* set up embedded ice registers again */
if ((retval = target_examine_one(target)) != ERROR_OK)
return retval;
{
LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
/* set up embedded ice registers again */
if ((retval = target_examine_one(target)) != ERROR_OK)
return retval;
- if ((retval=target_poll(target))!=ERROR_OK)
+ if ((retval=target_poll(target)) != ERROR_OK)
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target)) != ERROR_OK)
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target)) != ERROR_OK)
return retval;
long long then=timeval_ms();
return retval;
long long then=timeval_ms();
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
break;
embeddedice_read_reg(dbg_stat);
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
break;
embeddedice_read_reg(dbg_stat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
if (debug_level>=3)
{
return retval;
if (debug_level>=3)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
+ if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
return retval;
int little=target->endianness==TARGET_LITTLE_ENDIAN;
return retval;
int little=target->endianness==TARGET_LITTLE_ENDIAN;
if (retval==ERROR_OK)
{
uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32);
if (retval==ERROR_OK)
{
uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32);
- if (endaddress!=(address+count*4))
+ if (endaddress != (address+count*4))
{
LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress);
retval=ERROR_FAIL;
{
LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress);
retval=ERROR_FAIL;
/* convert flash writing code into a buffer in target endianness */
for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
{
/* convert flash writing code into a buffer in target endianness */
for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
{
- if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i]))!=ERROR_OK)
+ if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK)
}
target_set_examined(target);
}
}
target_set_examined(target);
}
- if ((retval=embeddedice_setup(target))!=ERROR_OK)
+ if ((retval=embeddedice_setup(target)) != ERROR_OK)
- if ((retval=arm7_9_setup(target))!=ERROR_OK)
+ if ((retval=arm7_9_setup(target)) != ERROR_OK)
return retval;
if (arm7_9->etm_ctx)
{
return retval;
if (arm7_9->etm_ctx)
{
- if ((retval=etm_setup(target))!=ERROR_OK)
+ if ((retval=etm_setup(target)) != ERROR_OK)
return retval;
}
return ERROR_OK;
return retval;
}
return ERROR_OK;
}
target_set_examined(target);
}
}
target_set_examined(target);
}
- if ((retval=embeddedice_setup(target))!=ERROR_OK)
+ if ((retval=embeddedice_setup(target)) != ERROR_OK)
- if ((retval=arm7_9_setup(target))!=ERROR_OK)
+ if ((retval=arm7_9_setup(target)) != ERROR_OK)
return retval;
if (arm7_9->etm_ctx)
{
return retval;
if (arm7_9->etm_ctx)
{
- if ((retval=etm_setup(target))!=ERROR_OK)
+ if ((retval=etm_setup(target)) != ERROR_OK)
return retval;
}
return ERROR_OK;
return retval;
}
return ERROR_OK;
https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
*/
https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
*/
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("BUG: Why does this fail the first time????");
}
{
LOG_ERROR("BUG: Why does this fail the first time????");
}
#endif
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
#endif
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
swjdp->ack = swjdp->ack & 0x7;
return retval;
swjdp->ack = swjdp->ack & 0x7;
}
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
}
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
swjdp->ack = swjdp->ack & 0x7;
}
return retval;
swjdp->ack = swjdp->ack & 0x7;
}
/* Clear Sticky Error Bits */
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
/* Clear Sticky Error Bits */
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
return retval;
LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
}
return retval;
LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
}
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
return ERROR_JTAG_DEVICE_ERROR;
}
return retval;
return ERROR_JTAG_DEVICE_ERROR;
}
dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
/* Check that we have debug power domains activated */
return retval;
/* Check that we have debug power domains activated */
{
LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
{
LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
alive_sleep(10);
}
return retval;
alive_sleep(10);
}
{
LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
{
LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
alive_sleep(10);
}
return retval;
alive_sleep(10);
}
dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
swjdp_transaction_endcheck(swjdp);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
swjdp_transaction_endcheck(swjdp);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
+ mem_ap = ((apid&0x10000)&&((apid&0x0F) != 0));
command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid);
if (apid)
{
command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid);
if (apid)
{
- if ((imm==0) && (opc!=0))
+ if ((imm==0) && (opc != 0))
imm = 32;
instruction->info.data_proc.Rd = Rd;
imm = 32;
instruction->info.data_proc.Rd = Rd;
}
if (target->state != TARGET_HALTED)
{
}
if (target->state != TARGET_HALTED)
{
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target)) != ERROR_OK)
- if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
+ if ((retval=target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
breakpoint_remove(target, exit_point);
breakpoint_remove(target, exit_point);
+ if (retval != ERROR_OK)
return retval;
for (i = 0; i < num_mem_params; i++)
return retval;
for (i = 0; i < num_mem_params; i++)
/* If the target fails to halt due to the breakpoint, force a halt */
if (retval != ERROR_OK || target->state != TARGET_HALTED)
{
/* If the target fails to halt due to the breakpoint, force a halt */
if (retval != ERROR_OK || target->state != TARGET_HALTED)
{
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval=target_halt(target)) != ERROR_OK)
- if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
+ if ((retval=target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
for (i = 0; i < num_mem_params; i++)
{
for (i = 0; i < num_mem_params; i++)
{
- if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value))!=ERROR_OK)
+ if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
void breakpoint_clear_target(target_t *target)
{
breakpoint_t *breakpoint;
void breakpoint_clear_target(target_t *target)
{
breakpoint_t *breakpoint;
- while ((breakpoint = target->breakpoints)!=NULL)
+ while ((breakpoint = target->breakpoints) != NULL)
{
breakpoint_free(target, breakpoint);
}
{
breakpoint_free(target, breakpoint);
}
void watchpoint_clear_target(target_t *target)
{
watchpoint_t *watchpoint;
void watchpoint_clear_target(target_t *target)
{
watchpoint_t *watchpoint;
- while ((watchpoint = target->watchpoints)!=NULL)
+ while ((watchpoint = target->watchpoints) != NULL)
{
watchpoint_free(target, watchpoint);
}
{
watchpoint_free(target, watchpoint);
}
if (target->reset_halt)
{
int retval;
if (target->reset_halt)
{
int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
+ if ((retval = target_halt(target)) != ERROR_OK)
/* identify EmbeddedICE version by reading DCC control register */
embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
/* identify EmbeddedICE version by reading DCC control register */
embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
{
for (i = 0; i < num_regs; i++)
{
{
for (i = 0; i < num_regs; i++)
{
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
embeddedice_read_reg(dbg_ctrl);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
embeddedice_read_reg(dbg_ctrl);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
buf_set_u32(dbg_ctrl->value, 4, 1, 0);
embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
return retval;
buf_set_u32(dbg_ctrl->value, 4, 1, 0);
embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
etm_store_reg(etm_ctrl_reg);
buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
etm_store_reg(etm_ctrl_reg);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval=jtag_execute_queue()) != ERROR_OK)
return retval;
if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
return retval;
if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
int retval;
retval = arm9tdmi_examine(target);
int retval;
retval = arm9tdmi_examine(target);
+ if (retval != ERROR_OK)
return retval;
armv4_5 = target->arch_info;
return retval;
armv4_5 = target->arch_info;
+ if (retval != ERROR_OK)
return retval;
/* check header against known signatures */
return retval;
/* check header against known signatures */
return ERROR_FILEIO_OPERATION_FAILED;
}
return ERROR_FILEIO_OPERATION_FAILED;
}
- if (strncmp((char*)elf->header->e_ident,ELFMAG,SELFMAG)!=0)
+ if (strncmp((char*)elf->header->e_ident,ELFMAG,SELFMAG) != 0)
{
LOG_ERROR("invalid ELF file, bad magic number");
return ERROR_IMAGE_FORMAT_ERROR;
{
LOG_ERROR("invalid ELF file, bad magic number");
return ERROR_IMAGE_FORMAT_ERROR;
}
elf->endianness = elf->header->e_ident[EI_DATA];
}
elf->endianness = elf->header->e_ident[EI_DATA];
- if ((elf->endianness!=ELFDATA2LSB)
- &&(elf->endianness!=ELFDATA2MSB))
+ if ((elf->endianness != ELFDATA2LSB)
+ &&(elf->endianness != ELFDATA2MSB))
{
LOG_ERROR("invalid ELF file, unknown endianess setting");
return ERROR_IMAGE_FORMAT_ERROR;
{
LOG_ERROR("invalid ELF file, unknown endianess setting");
return ERROR_IMAGE_FORMAT_ERROR;
if (target->reset_halt)
{
int retval;
if (target->reset_halt)
{
int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
+ if ((retval = target_halt(target)) != ERROR_OK)
LOG_USER("target state: %s",
Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
LOG_USER("target state: %s",
Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
- if (target->state!=TARGET_HALTED)
+ if (target->state != TARGET_HALTED)
return ERROR_OK;
retval=target->type->arch_state(target);
return ERROR_OK;
retval=target->type->arch_state(target);
static int prevPowerdropout = 0;
int retval;
static int prevPowerdropout = 0;
int retval;
- if ((retval=jtag_power_dropout(&powerDropout))!=ERROR_OK)
+ if ((retval=jtag_power_dropout(&powerDropout)) != ERROR_OK)
return retval;
int powerRestored;
return retval;
int powerRestored;
- if ((retval=jtag_srst_asserted(&srstAsserted))!=ERROR_OK)
+ if ((retval=jtag_srst_asserted(&srstAsserted)) != ERROR_OK)
return retval;
int srstDeasserted;
return retval;
int srstDeasserted;
- if ((retval=target_poll(target))!=ERROR_OK)
+ if ((retval=target_poll(target)) != ERROR_OK)
return retval;
if (target->state == state)
{
return retval;
if (target->state == state)
{
/*append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size) */
char *data=malloc(2*length);
/*append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size) */
char *data=malloc(2*length);
{
for (i=0; i<length;i++)
{
{
for (i=0; i<length;i++)
{
struct timeval timeout, now;
gettimeofday(&timeout, NULL);
struct timeval timeout, now;
gettimeofday(&timeout, NULL);
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
retval=ERROR_OK;
break;
}
retval=ERROR_OK;
break;
}
+ if (retval != ERROR_OK)
e,
Jim_Nvp_value2name_simple( nvp_target_event, e )->name,
Jim_GetString( teap->body, NULL ) );
e,
Jim_Nvp_value2name_simple( nvp_target_event, e )->name,
Jim_GetString( teap->body, NULL ) );
- if (Jim_EvalObj( interp, teap->body )!=JIM_OK)
+ if (Jim_EvalObj( interp, teap->body ) != JIM_OK)
{
Jim_PrintErrorMessage(interp);
}
{
Jim_PrintErrorMessage(interp);
}
static void free_fastload(void)
{
static void free_fastload(void)
{
{
int i;
for (i=0; i<fastload_num; i++)
{
int i;
for (i=0; i<fastload_num; i++)
+ if (retval != ERROR_OK)
retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
+ if (retval != ERROR_OK)
{
/* Some of these reads will fail as part of normal execution */
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
{
/* Some of these reads will fail as part of normal execution */
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
if (retval == ERROR_TARGET_TIMEOUT)
return retval;
+ if (retval != ERROR_OK)
{
/* Some of these reads will fail as part of normal execution */
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
{
/* Some of these reads will fail as part of normal execution */
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
/* clear external dbg break (will be written on next DCSR read) */
xscale->external_debug_break = 0;
/* clear external dbg break (will be written on next DCSR read) */
xscale->external_debug_break = 0;
- if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ if ((retval=xscale_read_dcsr(target)) != ERROR_OK)
return retval;
/* get r0, pc, r1 to r7 and cpsr */
return retval;
/* get r0, pc, r1 to r7 and cpsr */
- if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
+ if ((retval=xscale_receive(target, buffer, 10)) != ERROR_OK)
return retval;
/* move r0 from buffer to register cache */
return retval;
/* move r0 from buffer to register cache */
- if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1))!=ERROR_OK)
+ if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK)
return retval;
return ERROR_OK;
return retval;
return ERROR_OK;
reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
int retval;
reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
int retval;
- if ((retval=xscale_set_reg_u32(ibcr0, 0x0))!=ERROR_OK)
+ if ((retval=xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
return retval;
return ERROR_OK;
return retval;
return ERROR_OK;
}
/* update vector tables */
}
/* update vector tables */
- if ((retval=xscale_update_vectors(target))!=ERROR_OK)
+ if ((retval=xscale_update_vectors(target)) != ERROR_OK)
return retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
return retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
}
LOG_DEBUG("enable single-step");
}
LOG_DEBUG("enable single-step");
- if ((retval=xscale_enable_single_step(target, next_pc))!=ERROR_OK)
+ if ((retval=xscale_enable_single_step(target, next_pc)) != ERROR_OK)
return retval;
/* restore banked registers */
return retval;
/* restore banked registers */
- if ((retval=xscale_restore_context(target))!=ERROR_OK)
+ if ((retval=xscale_restore_context(target)) != ERROR_OK)
return retval;
/* send resume request (command 0x30 or 0x31)
* clean the trace buffer if it is to be enabled (0x62) */
if (xscale->trace.buffer_enabled)
{
return retval;
/* send resume request (command 0x30 or 0x31)
* clean the trace buffer if it is to be enabled (0x62) */
if (xscale->trace.buffer_enabled)
{
- if ((retval=xscale_send_u32(target, 0x62))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x62)) != ERROR_OK)
- if ((retval=xscale_send_u32(target, 0x31))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x31)) != ERROR_OK)
- if ((retval=xscale_send_u32(target, 0x30))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x30)) != ERROR_OK)
return retval;
/* send CPSR */
return retval;
/* send CPSR */
- if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
for (i = 7; i >= 0; i--)
{
/* send register */
return retval;
LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
for (i = 7; i >= 0; i--)
{
/* send register */
- if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
return retval;
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
- if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
return retval;
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* registers are now invalid */
return retval;
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* registers are now invalid */
- if ((retval=armv4_5_invalidate_core_regs(target))!=ERROR_OK)
+ if ((retval=armv4_5_invalidate_core_regs(target)) != ERROR_OK)
return retval;
/* wait for and process debug entry */
return retval;
/* wait for and process debug entry */
- if ((retval=xscale_debug_entry(target))!=ERROR_OK)
+ if ((retval=xscale_debug_entry(target)) != ERROR_OK)
return retval;
LOG_DEBUG("disable single-step");
return retval;
LOG_DEBUG("disable single-step");
- if ((retval=xscale_disable_single_step(target))!=ERROR_OK)
+ if ((retval=xscale_disable_single_step(target)) != ERROR_OK)
return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
/* if we're at the reset vector, we have to simulate the step */
if (current_pc == 0x0)
{
/* if we're at the reset vector, we have to simulate the step */
if (current_pc == 0x0)
{
- if ((retval=arm_simulate_step(target, NULL))!=ERROR_OK)
+ if ((retval=arm_simulate_step(target, NULL)) != ERROR_OK)
return retval;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
return retval;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
{
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
{
- if ((retval=xscale_unset_breakpoint(target, breakpoint))!=ERROR_OK)
+ if ((retval=xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
if (target->reset_halt)
{
int retval;
if (target->reset_halt)
{
int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
+ if ((retval = target_halt(target)) != ERROR_OK)
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory read request (command 0x1n, n: access size) */
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory read request (command 0x1n, n: access size) */
- if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x10 | size)) != ERROR_OK)
return retval;
/* send base address for read request */
return retval;
/* send base address for read request */
- if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, address)) != ERROR_OK)
return retval;
/* send number of requested data words */
return retval;
/* send number of requested data words */
- if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, count)) != ERROR_OK)
return retval;
/* receive data from target (count times 32-bit words in host endianness) */
buf32 = malloc(4 * count);
return retval;
/* receive data from target (count times 32-bit words in host endianness) */
buf32 = malloc(4 * count);
- if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
+ if ((retval=xscale_receive(target, buf32, count)) != ERROR_OK)
return retval;
/* extract data from host-endian buffer into byte stream */
return retval;
/* extract data from host-endian buffer into byte stream */
free(buf32);
/* examine DCSR, to see if Sticky Abort (SA) got set */
free(buf32);
/* examine DCSR, to see if Sticky Abort (SA) got set */
- if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ if ((retval=xscale_read_dcsr(target)) != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK)
return retval;
return ERROR_TARGET_DATA_ABORT;
return retval;
return ERROR_TARGET_DATA_ABORT;
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory write request (command 0x2n, n: access size) */
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory write request (command 0x2n, n: access size) */
- if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x20 | size)) != ERROR_OK)
return retval;
/* send base address for read request */
return retval;
/* send base address for read request */
- if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, address)) != ERROR_OK)
return retval;
/* send number of requested data words to be written*/
return retval;
/* send number of requested data words to be written*/
- if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, count)) != ERROR_OK)
return retval;
/* extract data from host-endian buffer into byte stream */
return retval;
/* extract data from host-endian buffer into byte stream */
- if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
+ if ((retval=xscale_send(target, buffer, count, size)) != ERROR_OK)
return retval;
/* examine DCSR, to see if Sticky Abort (SA) got set */
return retval;
/* examine DCSR, to see if Sticky Abort (SA) got set */
- if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ if ((retval=xscale_read_dcsr(target)) != ERROR_OK)
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ if ((retval=xscale_send_u32(target, 0x60)) != ERROR_OK)
return retval;
return ERROR_TARGET_DATA_ABORT;
return retval;
return ERROR_TARGET_DATA_ABORT;
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