Remove misleading typedef and redundant suffix from struct arm_instruction.
}
static int evaluate_pld(uint32_t opcode,
}
static int evaluate_pld(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
/* PLD */
if ((opcode & 0x0d70f000) == 0x0550f000)
{
/* PLD */
if ((opcode & 0x0d70f000) == 0x0550f000)
}
static int evaluate_swi(uint32_t opcode,
}
static int evaluate_swi(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
instruction->type = ARM_SWI;
{
instruction->type = ARM_SWI;
}
static int evaluate_blx_imm(uint32_t opcode,
}
static int evaluate_blx_imm(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
int offset;
uint32_t immediate;
{
int offset;
uint32_t immediate;
}
static int evaluate_b_bl(uint32_t opcode,
}
static int evaluate_b_bl(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t L;
uint32_t immediate;
{
uint8_t L;
uint32_t immediate;
/* Coprocessor load/store and double register transfers */
/* both normal and extended instruction space (condition field b1111) */
static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
/* Coprocessor load/store and double register transfers */
/* both normal and extended instruction space (condition field b1111) */
static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t cp_num = (opcode & 0xf00) >> 8;
{
uint8_t cp_num = (opcode & 0xf00) >> 8;
/* Coprocessor register transfer instructions */
/* both normal and extended instruction space (condition field b1111) */
static int evaluate_cdp_mcr_mrc(uint32_t opcode,
/* Coprocessor register transfer instructions */
/* both normal and extended instruction space (condition field b1111) */
static int evaluate_cdp_mcr_mrc(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
const char *cond;
char* mnemonic;
{
const char *cond;
char* mnemonic;
/* Load/store instructions */
static int evaluate_load_store(uint32_t opcode,
/* Load/store instructions */
static int evaluate_load_store(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t I, P, U, B, W, L;
uint8_t Rn, Rd;
{
uint8_t I, P, U, B, W, L;
uint8_t Rn, Rd;
/* ARMv6 and later support "media" instructions (includes SIMD) */
static int evaluate_media(uint32_t opcode, uint32_t address,
/* ARMv6 and later support "media" instructions (includes SIMD) */
static int evaluate_media(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction)
+ struct arm_instruction *instruction)
{
char *cp = instruction->text;
char *mnemonic = NULL;
{
char *cp = instruction->text;
char *mnemonic = NULL;
/* Miscellaneous load/store instructions */
static int evaluate_misc_load_store(uint32_t opcode,
/* Miscellaneous load/store instructions */
static int evaluate_misc_load_store(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t P, U, I, W, L, S, H;
uint8_t Rn, Rd;
{
uint8_t P, U, I, W, L, S, H;
uint8_t Rn, Rd;
/* Load/store multiples instructions */
static int evaluate_ldm_stm(uint32_t opcode,
/* Load/store multiples instructions */
static int evaluate_ldm_stm(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t P, U, S, W, L, Rn;
uint32_t register_list;
{
uint8_t P, U, S, W, L, Rn;
uint32_t register_list;
/* Multiplies, extra load/stores */
static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
/* Multiplies, extra load/stores */
static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
/* Multiply (accumulate) (long) and Swap/swap byte */
if ((opcode & 0x000000f0) == 0x00000090)
{
/* Multiply (accumulate) (long) and Swap/swap byte */
if ((opcode & 0x000000f0) == 0x00000090)
}
static int evaluate_mrs_msr(uint32_t opcode,
}
static int evaluate_mrs_msr(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
int R = (opcode & 0x00400000) >> 22;
char *PSR = (R) ? "SPSR" : "CPSR";
{
int R = (opcode & 0x00400000) >> 22;
char *PSR = (R) ? "SPSR" : "CPSR";
/* Miscellaneous instructions */
static int evaluate_misc_instr(uint32_t opcode,
/* Miscellaneous instructions */
static int evaluate_misc_instr(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
/* MRS/MSR */
if ((opcode & 0x000000f0) == 0x00000000)
{
/* MRS/MSR */
if ((opcode & 0x000000f0) == 0x00000000)
}
static int evaluate_data_proc(uint32_t opcode,
}
static int evaluate_data_proc(uint32_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t I, op, S, Rn, Rd;
char *mnemonic = NULL;
{
uint8_t I, op, S, Rn, Rd;
char *mnemonic = NULL;
-int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+int arm_evaluate_opcode(uint32_t opcode, uint32_t address, struct arm_instruction *instruction)
{
/* clear fields, to avoid confusion */
{
/* clear fields, to avoid confusion */
- memset(instruction, 0, sizeof(arm_instruction_t));
+ memset(instruction, 0, sizeof(struct arm_instruction));
instruction->opcode = opcode;
instruction->instruction_size = 4;
instruction->opcode = opcode;
instruction->instruction_size = 4;
}
static int evaluate_b_bl_blx_thumb(uint16_t opcode,
}
static int evaluate_b_bl_blx_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint32_t offset = opcode & 0x7ff;
uint32_t opc = (opcode >> 11) & 0x3;
{
uint32_t offset = opcode & 0x7ff;
uint32_t opc = (opcode >> 11) & 0x3;
}
static int evaluate_add_sub_thumb(uint16_t opcode,
}
static int evaluate_add_sub_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
{
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
}
static int evaluate_shift_imm_thumb(uint16_t opcode,
}
static int evaluate_shift_imm_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rm = (opcode >> 3) & 0x7;
{
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rm = (opcode >> 3) & 0x7;
}
static int evaluate_data_proc_imm_thumb(uint16_t opcode,
}
static int evaluate_data_proc_imm_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t imm = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
{
uint8_t imm = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
}
static int evaluate_data_proc_thumb(uint16_t opcode,
}
static int evaluate_data_proc_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t high_reg, op, Rm, Rd,H1,H2;
char *mnemonic = NULL;
{
uint8_t high_reg, op, Rm, Rd,H1,H2;
char *mnemonic = NULL;
}
static int evaluate_load_literal_thumb(uint16_t opcode,
}
static int evaluate_load_literal_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint32_t immediate;
uint8_t Rd = (opcode >> 8) & 0x7;
{
uint32_t immediate;
uint8_t Rd = (opcode >> 8) & 0x7;
}
static int evaluate_load_store_reg_thumb(uint16_t opcode,
}
static int evaluate_load_store_reg_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
{
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
}
static int evaluate_load_store_imm_thumb(uint16_t opcode,
}
static int evaluate_load_store_imm_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint32_t offset = (opcode >> 6) & 0x1f;
uint8_t Rd = (opcode >> 0) & 0x7;
{
uint32_t offset = (opcode >> 6) & 0x1f;
uint8_t Rd = (opcode >> 0) & 0x7;
}
static int evaluate_load_store_stack_thumb(uint16_t opcode,
}
static int evaluate_load_store_stack_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint32_t offset = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
{
uint32_t offset = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
}
static int evaluate_add_sp_pc_thumb(uint16_t opcode,
}
static int evaluate_add_sp_pc_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint32_t imm = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
{
uint32_t imm = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
}
static int evaluate_adjust_stack_thumb(uint16_t opcode,
}
static int evaluate_adjust_stack_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint32_t imm = opcode & 0x7f;
uint8_t opc = opcode & (1 << 7);
{
uint32_t imm = opcode & 0x7f;
uint8_t opc = opcode & (1 << 7);
}
static int evaluate_breakpoint_thumb(uint16_t opcode,
}
static int evaluate_breakpoint_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint32_t imm = opcode & 0xff;
{
uint32_t imm = opcode & 0xff;
}
static int evaluate_load_store_multiple_thumb(uint16_t opcode,
}
static int evaluate_load_store_multiple_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint32_t reg_list = opcode & 0xff;
uint32_t L = opcode & (1 << 11);
{
uint32_t reg_list = opcode & 0xff;
uint32_t L = opcode & (1 << 11);
}
static int evaluate_cond_branch_thumb(uint16_t opcode,
}
static int evaluate_cond_branch_thumb(uint16_t opcode,
- uint32_t address, arm_instruction_t *instruction)
+ uint32_t address, struct arm_instruction *instruction)
{
uint32_t offset = opcode & 0xff;
uint8_t cond = (opcode >> 8) & 0xf;
{
uint32_t offset = opcode & 0xff;
uint8_t cond = (opcode >> 8) & 0xf;
}
static int evaluate_cb_thumb(uint16_t opcode, uint32_t address,
}
static int evaluate_cb_thumb(uint16_t opcode, uint32_t address,
- arm_instruction_t *instruction)
+ struct arm_instruction *instruction)
}
static int evaluate_extend_thumb(uint16_t opcode, uint32_t address,
}
static int evaluate_extend_thumb(uint16_t opcode, uint32_t address,
- arm_instruction_t *instruction)
+ struct arm_instruction *instruction)
{
/* added in ARMv6 */
snprintf(instruction->text, 128,
{
/* added in ARMv6 */
snprintf(instruction->text, 128,
}
static int evaluate_cps_thumb(uint16_t opcode, uint32_t address,
}
static int evaluate_cps_thumb(uint16_t opcode, uint32_t address,
- arm_instruction_t *instruction)
+ struct arm_instruction *instruction)
{
/* added in ARMv6 */
if ((opcode & 0x0ff0) == 0x0650)
{
/* added in ARMv6 */
if ((opcode & 0x0ff0) == 0x0650)
}
static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address,
}
static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address,
- arm_instruction_t *instruction)
+ struct arm_instruction *instruction)
}
static int evaluate_hint_thumb(uint16_t opcode, uint32_t address,
}
static int evaluate_hint_thumb(uint16_t opcode, uint32_t address,
- arm_instruction_t *instruction)
+ struct arm_instruction *instruction)
}
static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address,
}
static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address,
- arm_instruction_t *instruction)
+ struct arm_instruction *instruction)
{
unsigned cond = (opcode >> 4) & 0x0f;
char *x = "", *y = "", *z = "";
{
unsigned cond = (opcode >> 4) & 0x0f;
char *x = "", *y = "", *z = "";
-int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruction *instruction)
{
/* clear fields, to avoid confusion */
{
/* clear fields, to avoid confusion */
- memset(instruction, 0, sizeof(arm_instruction_t));
+ memset(instruction, 0, sizeof(struct arm_instruction));
instruction->opcode = opcode;
instruction->instruction_size = 2;
instruction->opcode = opcode;
instruction->instruction_size = 2;
}
static int t2ev_b_bl(uint32_t opcode, uint32_t address,
}
static int t2ev_b_bl(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
unsigned offset;
unsigned b21 = 1 << 21;
{
unsigned offset;
unsigned b21 = 1 << 21;
}
static int t2ev_cond_b(uint32_t opcode, uint32_t address,
}
static int t2ev_cond_b(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
unsigned offset;
unsigned b17 = 1 << 17;
{
unsigned offset;
unsigned b17 = 1 << 17;
}
static int t2ev_hint(uint32_t opcode, uint32_t address,
}
static int t2ev_hint(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
}
static int t2ev_misc(uint32_t opcode, uint32_t address,
}
static int t2ev_misc(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
}
static int t2ev_b_misc(uint32_t opcode, uint32_t address,
}
static int t2ev_b_misc(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
/* permanently undefined */
if ((opcode & 0x07f07000) == 0x07f02000) {
{
/* permanently undefined */
if ((opcode & 0x07f07000) == 0x07f02000) {
}
static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
}
static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
char *mnemonic = NULL;
int rn = (opcode >> 16) & 0xf;
{
char *mnemonic = NULL;
int rn = (opcode >> 16) & 0xf;
}
static int t2ev_data_immed(uint32_t opcode, uint32_t address,
}
static int t2ev_data_immed(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
char *mnemonic = NULL;
int rn = (opcode >> 16) & 0xf;
{
char *mnemonic = NULL;
int rn = (opcode >> 16) & 0xf;
}
static int t2ev_store_single(uint32_t opcode, uint32_t address,
}
static int t2ev_store_single(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
unsigned op = (opcode >> 20) & 0xf;
char *size = "";
{
unsigned op = (opcode >> 20) & 0xf;
char *size = "";
}
static int t2ev_mul32(uint32_t opcode, uint32_t address,
}
static int t2ev_mul32(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
int ra = (opcode >> 12) & 0xf;
{
int ra = (opcode >> 12) & 0xf;
}
static int t2ev_mul64_div(uint32_t opcode, uint32_t address,
}
static int t2ev_mul64_div(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
int op = (opcode >> 4) & 0xf;
char *infix = "MUL";
{
int op = (opcode >> 4) & 0xf;
char *infix = "MUL";
}
static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
}
static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
int rn = (opcode >> 16) & 0xf;
int op = (opcode >> 22) & 0x6;
{
int rn = (opcode >> 16) & 0xf;
int op = (opcode >> 22) & 0x6;
/* load/store dual or exclusive, table branch */
static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address,
/* load/store dual or exclusive, table branch */
static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
unsigned op1op2 = (opcode >> 20) & 0x3;
unsigned op3 = (opcode >> 4) & 0xf;
{
unsigned op1op2 = (opcode >> 20) & 0x3;
unsigned op3 = (opcode >> 4) & 0xf;
}
static int t2ev_data_shift(uint32_t opcode, uint32_t address,
}
static int t2ev_data_shift(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
int op = (opcode >> 21) & 0xf;
int rd = (opcode >> 8) & 0xf;
{
int op = (opcode >> 21) & 0xf;
int rd = (opcode >> 8) & 0xf;
}
static int t2ev_data_reg(uint32_t opcode, uint32_t address,
}
static int t2ev_data_reg(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
char *mnemonic;
char * suffix = "";
{
char *mnemonic;
char * suffix = "";
}
static int t2ev_load_word(uint32_t opcode, uint32_t address,
}
static int t2ev_load_word(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
int rn = (opcode >> 16) & 0xf;
int immed;
{
int rn = (opcode >> 16) & 0xf;
int immed;
}
static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address,
}
static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
int rn = (opcode >> 16) & 0xf;
int rt = (opcode >> 12) & 0xf;
{
int rn = (opcode >> 16) & 0xf;
int rt = (opcode >> 12) & 0xf;
}
static int t2ev_load_halfword(uint32_t opcode, uint32_t address,
}
static int t2ev_load_halfword(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction, char *cp)
+ struct arm_instruction *instruction, char *cp)
{
int rn = (opcode >> 16) & 0xf;
int rt = (opcode >> 12) & 0xf;
{
int rn = (opcode >> 16) & 0xf;
int rt = (opcode >> 12) & 0xf;
* always set. That means eventual arm_simulate_step() support for Thumb2
* will need work in this area.
*/
* always set. That means eventual arm_simulate_step() support for Thumb2
* will need work in this area.
*/
-int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruction)
+int thumb2_opcode(target_t *target, uint32_t address, struct arm_instruction *instruction)
{
int retval;
uint16_t op;
{
int retval;
uint16_t op;
address &= ~1;
/* clear fields, to avoid confusion */
address &= ~1;
/* clear fields, to avoid confusion */
- memset(instruction, 0, sizeof(arm_instruction_t));
+ memset(instruction, 0, sizeof(struct arm_instruction));
/* read first halfword, see if this is the only one */
retval = target_read_u16(target, address, &op);
/* read first halfword, see if this is the only one */
retval = target_read_u16(target, address, &op);
-int arm_access_size(arm_instruction_t *instruction)
+int arm_access_size(struct arm_instruction *instruction)
{
if ((instruction->type == ARM_LDRB)
|| (instruction->type == ARM_LDRBT)
{
if ((instruction->type == ARM_LDRB)
|| (instruction->type == ARM_LDRBT)
-typedef struct arm_instruction_s
{
enum arm_instruction_type type;
char text[128];
{
enum arm_instruction_type type;
char text[128];
struct arm_load_store_multiple_instr load_store_multiple;
} info;
struct arm_load_store_multiple_instr load_store_multiple;
} info;
int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
- arm_instruction_t *instruction);
+ struct arm_instruction *instruction);
int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
- arm_instruction_t *instruction);
+ struct arm_instruction *instruction);
int thumb2_opcode(target_t *target, uint32_t address,
int thumb2_opcode(target_t *target, uint32_t address,
- arm_instruction_t *instruction);
-int arm_access_size(arm_instruction_t *instruction);
+ struct arm_instruction *instruction);
+int arm_access_size(struct arm_instruction *instruction);
#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
uint32_t *dry_run_pc, struct arm_sim_interface *sim)
{
uint32_t current_pc = sim->get_reg(sim, 15);
uint32_t *dry_run_pc, struct arm_sim_interface *sim)
{
uint32_t current_pc = sim->get_reg(sim, 15);
- arm_instruction_t instruction;
+ struct arm_instruction instruction;
int instruction_size;
int retval = ERROR_OK;
int instruction_size;
int retval = ERROR_OK;
uint32_t address;
int count = 1;
int i;
uint32_t address;
int count = 1;
int i;
- arm_instruction_t cur_instruction;
+ struct arm_instruction cur_instruction;
uint32_t opcode;
uint16_t thumb_opcode;
int thumb = 0;
uint32_t opcode;
uint16_t thumb_opcode;
int thumb = 0;
}
for (i = 0; i < count; i++) {
}
for (i = 0; i < count; i++) {
- arm_instruction_t cur_instruction;
+ struct arm_instruction cur_instruction;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
uint32_t address;
unsigned long count = 1;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
uint32_t address;
unsigned long count = 1;
- arm_instruction_t cur_instruction;
+ struct arm_instruction cur_instruction;
retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
if (retval != ERROR_OK)
retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
if (retval != ERROR_OK)
-static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
+static int etm_read_instruction(etm_context_t *ctx, struct arm_instruction *instruction)
{
int i;
int section = -1;
{
int i;
int section = -1;
static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
{
int retval;
static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
{
int retval;
- arm_instruction_t instruction;
+ struct arm_instruction instruction;
/* read the trace data if it wasn't read already */
if (ctx->trace_depth == 0)
/* read the trace data if it wasn't read already */
if (ctx->trace_depth == 0)
}
static int xscale_read_instruction(target_t *target,
}
static int xscale_read_instruction(target_t *target,
- arm_instruction_t *instruction)
+ struct arm_instruction *instruction)
{
struct xscale_common *xscale = target_to_xscale(target);
int i;
{
struct xscale_common *xscale = target_to_xscale(target);
int i;
if (xscale->trace.pc_ok)
{
int executed = (trace_data->entries[i].data & 0xf) + rollover * 16;
if (xscale->trace.pc_ok)
{
int executed = (trace_data->entries[i].data & 0xf) + rollover * 16;
- arm_instruction_t instruction;
+ struct arm_instruction instruction;
if ((exception == 6) || (exception == 7))
{
if ((exception == 6) || (exception == 7))
{
for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
{
for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
{
- arm_instruction_t instruction;
+ struct arm_instruction instruction;
if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
{
/* can't continue tracing with no image available */
if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
{
/* can't continue tracing with no image available */
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