Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into

the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index fd8072325ef3f5367c5893c62d6e7c57ae6a23d1..9585b35c2a658cb0de9980ce5b99b6ac854234c2 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -546,7 +546,7 @@ int cortex_a8_resume(struct target_s *target, int current,
 int cortex_a8_debug_entry(target_t *target)
 {
        int i;
-       uint32_t regfile[16], pc, cpsr;
+       uint32_t regfile[16], pc, cpsr, dscr;
        int retval = ERROR_OK;
        working_area_t *regfile_working_area = NULL;
 
@@ -561,6 +561,14 @@ int cortex_a8_debug_entry(target_t *target)
 
        LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
+       /* Enable the ITR execution once we are in debug mode */
+       mem_ap_read_atomic_u32(swjdp,
+                               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       dscr |= (1 << 13);
+       retval = mem_ap_write_atomic_u32(swjdp,
+                       OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
+
+
        /* Examine debug reason */
        switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
        {