* Cortex-A8(tm) TRM, ARM DDI 0344H *
* Cortex-A9(tm) TRM, ARM DDI 0407F *
* Cortex-A4(tm) TRM, ARM DDI 0363E *
+ * Cortex-A15(tm)TRM, ARM DDI 0438C *
* *
***************************************************************************/
#include "arm_opcodes.h"
#include <helper/time_support.h>
-static int cortex_a8_poll(struct target *target);
-static int cortex_a8_debug_entry(struct target *target);
-static int cortex_a8_restore_context(struct target *target, bool bpwp);
-static int cortex_a8_set_breakpoint(struct target *target,
+static int cortex_a_poll(struct target *target);
+static int cortex_a_debug_entry(struct target *target);
+static int cortex_a_restore_context(struct target *target, bool bpwp);
+static int cortex_a_set_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode);
-static int cortex_a8_set_context_breakpoint(struct target *target,
+static int cortex_a_set_context_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode);
-static int cortex_a8_set_hybrid_breakpoint(struct target *target,
+static int cortex_a_set_hybrid_breakpoint(struct target *target,
struct breakpoint *breakpoint);
-static int cortex_a8_unset_breakpoint(struct target *target,
+static int cortex_a_unset_breakpoint(struct target *target,
struct breakpoint *breakpoint);
-static int cortex_a8_dap_read_coreregister_u32(struct target *target,
+static int cortex_a_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum);
-static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+static int cortex_a_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum);
-static int cortex_a8_mmu(struct target *target, int *enabled);
-static int cortex_a8_virt2phys(struct target *target,
+static int cortex_a_mmu(struct target *target, int *enabled);
+static int cortex_a_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys);
-static int cortex_a8_read_apb_ab_memory(struct target *target,
+static int cortex_a_read_apb_ab_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
/* restore cp15_control_reg at resume */
-static int cortex_a8_restore_cp15_control_reg(struct target *target)
+static int cortex_a_restore_cp15_control_reg(struct target *target)
{
int retval = ERROR_OK;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
- if (cortex_a8->cp15_control_reg != cortex_a8->cp15_control_reg_curr) {
- cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg;
- /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); */
+ if (cortex_a->cp15_control_reg != cortex_a->cp15_control_reg_curr) {
+ cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
+ /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
retval = armv7a->arm.mcr(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
- cortex_a8->cp15_control_reg);
+ cortex_a->cp15_control_reg);
}
return retval;
}
-/* check address before cortex_a8_apb read write access with mmu on
+/* check address before cortex_a_apb read write access with mmu on
* remove apb predictible data abort */
-static int cortex_a8_check_address(struct target *target, uint32_t address)
+static int cortex_a_check_address(struct target *target, uint32_t address)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
uint32_t os_border = armv7a->armv7a_mmu.os_border;
if ((address < os_border) &&
(armv7a->arm.core_mode == ARM_MODE_SVC)) {
return ERROR_FAIL;
}
if ((address >= os_border) &&
- (cortex_a8->curr_mode != ARM_MODE_SVC)) {
+ (cortex_a->curr_mode != ARM_MODE_SVC)) {
dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
- cortex_a8->curr_mode = ARM_MODE_SVC;
+ cortex_a->curr_mode = ARM_MODE_SVC;
LOG_INFO("%" PRIx32 " access in kernel space and target not in supervisor",
address);
return ERROR_OK;
}
if ((address < os_border) &&
- (cortex_a8->curr_mode == ARM_MODE_SVC)) {
+ (cortex_a->curr_mode == ARM_MODE_SVC)) {
dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
- cortex_a8->curr_mode = ARM_MODE_ANY;
+ cortex_a->curr_mode = ARM_MODE_ANY;
}
return ERROR_OK;
}
/* modify cp15_control_reg in order to enable or disable mmu for :
* - virt2phys address conversion
* - read or write memory in phys or virt address */
-static int cortex_a8_mmu_modify(struct target *target, int enable)
+static int cortex_a_mmu_modify(struct target *target, int enable)
{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
int retval = ERROR_OK;
if (enable) {
/* if mmu enabled at target stop and mmu not enable */
- if (!(cortex_a8->cp15_control_reg & 0x1U)) {
+ if (!(cortex_a->cp15_control_reg & 0x1U)) {
LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
return ERROR_FAIL;
}
- if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) {
- cortex_a8->cp15_control_reg_curr |= 0x1U;
+ if (!(cortex_a->cp15_control_reg_curr & 0x1U)) {
+ cortex_a->cp15_control_reg_curr |= 0x1U;
retval = armv7a->arm.mcr(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
- cortex_a8->cp15_control_reg_curr);
+ cortex_a->cp15_control_reg_curr);
}
} else {
- if (cortex_a8->cp15_control_reg_curr & 0x4U) {
+ if (cortex_a->cp15_control_reg_curr & 0x4U) {
/* data cache is active */
- cortex_a8->cp15_control_reg_curr &= ~0x4U;
+ cortex_a->cp15_control_reg_curr &= ~0x4U;
/* flush data cache armv7 function to be called */
if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache)
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target);
}
- if ((cortex_a8->cp15_control_reg_curr & 0x1U)) {
- cortex_a8->cp15_control_reg_curr &= ~0x1U;
+ if ((cortex_a->cp15_control_reg_curr & 0x1U)) {
+ cortex_a->cp15_control_reg_curr &= ~0x1U;
retval = armv7a->arm.mcr(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
- cortex_a8->cp15_control_reg_curr);
+ cortex_a->cp15_control_reg_curr);
}
}
return retval;
}
/*
- * Cortex-A8 Basic debug access, very low level assumes state is saved
+ * Cortex-A Basic debug access, very low level assumes state is saved
*/
-static int cortex_a8_init_debug_access(struct target *target)
+static int cortex_a_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
/* Resync breakpoint registers */
/* Since this is likely called from init or reset, update target state information*/
- return cortex_a8_poll(target);
+ return cortex_a_poll(target);
}
/* To reduce needless round-trips, pass in a pointer to the current
* value on return from this function; or DSCR_INSTR_COMP if you
* happen to know that no instruction is pending.
*/
-static int cortex_a8_exec_opcode(struct target *target,
+static int cortex_a_exec_opcode(struct target *target,
uint32_t opcode, uint32_t *dscr_p)
{
uint32_t dscr;
return retval;
}
if (timeval_ms() > then + 1000) {
- LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
return ERROR_FAIL;
}
}
return retval;
}
if (timeval_ms() > then + 1000) {
- LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
return ERROR_FAIL;
}
} while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
Read core register with very few exec_opcode, fast but needs work_area.
This can cause problems with MMU active.
**************************************************************************/
-static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
+static int cortex_a_read_regs_through_mem(struct target *target, uint32_t address,
uint32_t *regfile)
{
int retval = ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
- retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
+ retval = cortex_a_dap_read_coreregister_u32(target, regfile, 0);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_coreregister_u32(target, address, 0);
+ retval = cortex_a_dap_write_coreregister_u32(target, address, 0);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
+ retval = cortex_a_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
if (retval != ERROR_OK)
return retval;
return retval;
}
-static int cortex_a8_dap_read_coreregister_u32(struct target *target,
+static int cortex_a_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum)
{
int retval = ERROR_OK;
if (reg < 15) {
/* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
- retval = cortex_a8_exec_opcode(target,
+ retval = cortex_a_exec_opcode(target,
ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
} else if (reg == 15) {
/* "MOV r0, r15"; then move r0 to DCCTX */
- retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
+ retval = cortex_a_exec_opcode(target, 0xE1A0000F, &dscr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target,
+ retval = cortex_a_exec_opcode(target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
/* "MRS r0, CPSR" or "MRS r0, SPSR"
* then move r0 to DCCTX
*/
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target,
+ retval = cortex_a_exec_opcode(target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
return retval;
if (timeval_ms() > then + 1000) {
- LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
return ERROR_FAIL;
}
}
return retval;
}
-static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+static int cortex_a_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum)
{
int retval = ERROR_OK;
if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
if (Rd < 15) {
/* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
/* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "mov r15, r0"
*/
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
+ retval = cortex_a_exec_opcode(target, 0xE1A0F000, &dscr);
if (retval != ERROR_OK)
return retval;
} else {
/* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
*/
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
&dscr);
if (retval != ERROR_OK)
return retval;
/* "Prefetch flush" after modifying execution status in CPSR */
if (Rd == 16) {
- retval = cortex_a8_exec_opcode(target,
+ retval = cortex_a_exec_opcode(target,
ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
&dscr);
if (retval != ERROR_OK)
}
/* Write to memory mapped registers directly with no cache or mmu handling */
-static int cortex_a8_dap_write_memap_register_u32(struct target *target,
+static int cortex_a_dap_write_memap_register_u32(struct target *target,
uint32_t address,
uint32_t value)
{
}
/*
- * Cortex-A8 implementation of Debug Programmer's Model
+ * Cortex-A implementation of Debug Programmer's Model
*
* NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
* so there's no need to poll for it before executing an instruction.
* be the places to enable/disable that mode.
*/
-static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
+static inline struct cortex_a_common *dpm_to_a(struct arm_dpm *dpm)
{
- return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
+ return container_of(dpm, struct cortex_a_common, armv7a_common.dpm);
}
-static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
+static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
- return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap,
- a8->armv7a_common.debug_ap, a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+ return mem_ap_sel_write_u32(a->armv7a_common.arm.dap,
+ a->armv7a_common.debug_ap, a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
-static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
+static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
uint32_t *dscr_p)
{
- struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
+ struct adiv5_dap *swjdp = a->armv7a_common.arm.dap;
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
/* Wait for DTRRXfull */
long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap,
- a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap,
+ a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
return retval;
}
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap,
- a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+ retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap,
+ a->armv7a_common.debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
/* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
return retval;
}
-static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
+static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap;
+ struct cortex_a_common *a = dpm_to_a(dpm);
+ struct adiv5_dap *swjdp = a->armv7a_common.arm.dap;
uint32_t dscr;
int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */
long long then = timeval_ms();
for (;; ) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap,
- a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap,
+ a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
return retval;
if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
}
-static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
+static int cortex_a_dpm_finish(struct arm_dpm *dpm)
{
/* REVISIT what could be done here? */
return ERROR_OK;
}
-static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
+static int cortex_a_instr_write_data_dcc(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
int retval;
uint32_t dscr = DSCR_INSTR_COMP;
- retval = cortex_a8_write_dcc(a8, data);
+ retval = cortex_a_write_dcc(a, data);
if (retval != ERROR_OK)
return retval;
- return cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ return cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
opcode,
&dscr);
}
-static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
+static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
- retval = cortex_a8_write_dcc(a8, data);
+ retval = cortex_a_write_dcc(a, data);
if (retval != ERROR_OK)
return retval;
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
/* then the opcode, taking data from R0 */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
opcode,
&dscr);
return retval;
}
-static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
+static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
{
struct target *target = dpm->arm->target;
uint32_t dscr = DSCR_INSTR_COMP;
/* "Prefetch flush" after modifying execution status in CPSR */
- return cortex_a8_exec_opcode(target,
+ return cortex_a_exec_opcode(target,
ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
&dscr);
}
-static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
+static int cortex_a_instr_read_data_dcc(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
int retval;
uint32_t dscr = DSCR_INSTR_COMP;
/* the opcode, writing data to DCC */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
return retval;
- return cortex_a8_read_dcc(a8, data, &dscr);
+ return cortex_a_read_dcc(a, data, &dscr);
}
-static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
+static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
/* the opcode, writing data to R0 */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
opcode,
&dscr);
if (retval != ERROR_OK)
return retval;
/* write R0 to DCC */
- retval = cortex_a8_exec_opcode(
- a8->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(
+ a->armv7a_common.arm.target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
- return cortex_a8_read_dcc(a8, data, &dscr);
+ return cortex_a_read_dcc(a, data, &dscr);
}
-static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
+static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
uint32_t addr, uint32_t control)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- uint32_t vr = a8->armv7a_common.debug_base;
- uint32_t cr = a8->armv7a_common.debug_base;
+ struct cortex_a_common *a = dpm_to_a(dpm);
+ uint32_t vr = a->armv7a_common.debug_base;
+ uint32_t cr = a->armv7a_common.debug_base;
int retval;
switch (index_t) {
vr += 4 * index_t;
cr += 4 * index_t;
- LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
+ LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
(unsigned) vr, (unsigned) cr);
- retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
vr, addr);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ retval = cortex_a_dap_write_memap_register_u32(dpm->arm->target,
cr, control);
return retval;
}
-static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
+static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
{
- struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct cortex_a_common *a = dpm_to_a(dpm);
uint32_t cr;
switch (index_t) {
case 0 ... 15:
- cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
+ cr = a->armv7a_common.debug_base + CPUDBG_BCR_BASE;
break;
case 16 ... 31:
- cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
+ cr = a->armv7a_common.debug_base + CPUDBG_WCR_BASE;
index_t -= 16;
break;
default:
}
cr += 4 * index_t;
- LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
+ LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
/* clear control register */
- return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
+ return cortex_a_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
}
-static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
+static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
{
- struct arm_dpm *dpm = &a8->armv7a_common.dpm;
+ struct arm_dpm *dpm = &a->armv7a_common.dpm;
int retval;
- dpm->arm = &a8->armv7a_common.arm;
+ dpm->arm = &a->armv7a_common.arm;
dpm->didr = didr;
- dpm->prepare = cortex_a8_dpm_prepare;
- dpm->finish = cortex_a8_dpm_finish;
+ dpm->prepare = cortex_a_dpm_prepare;
+ dpm->finish = cortex_a_dpm_finish;
- dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
- dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
- dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
+ dpm->instr_write_data_dcc = cortex_a_instr_write_data_dcc;
+ dpm->instr_write_data_r0 = cortex_a_instr_write_data_r0;
+ dpm->instr_cpsr_sync = cortex_a_instr_cpsr_sync;
- dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
- dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
+ dpm->instr_read_data_dcc = cortex_a_instr_read_data_dcc;
+ dpm->instr_read_data_r0 = cortex_a_instr_read_data_r0;
- dpm->bpwp_enable = cortex_a8_bpwp_enable;
- dpm->bpwp_disable = cortex_a8_bpwp_disable;
+ dpm->bpwp_enable = cortex_a_bpwp_enable;
+ dpm->bpwp_disable = cortex_a_bpwp_disable;
retval = arm_dpm_setup(dpm);
if (retval == ERROR_OK)
return retval;
}
-static struct target *get_cortex_a8(struct target *target, int32_t coreid)
+static struct target *get_cortex_a(struct target *target, int32_t coreid)
{
struct target_list *head;
struct target *curr;
}
return target;
}
-static int cortex_a8_halt(struct target *target);
+static int cortex_a_halt(struct target *target);
-static int cortex_a8_halt_smp(struct target *target)
+static int cortex_a_halt_smp(struct target *target)
{
int retval = 0;
struct target_list *head;
while (head != (struct target_list *)NULL) {
curr = head->target;
if ((curr != target) && (curr->state != TARGET_HALTED))
- retval += cortex_a8_halt(curr);
+ retval += cortex_a_halt(curr);
head = head->next;
}
return retval;
if (target->gdb_service && target->gdb_service->core[0] == -1) {
target->gdb_service->target = target;
target->gdb_service->core[0] = target->coreid;
- retval += cortex_a8_halt_smp(target);
+ retval += cortex_a_halt_smp(target);
}
return retval;
}
/*
- * Cortex-A8 Run control
+ * Cortex-A Run control
*/
-static int cortex_a8_poll(struct target *target)
+static int cortex_a_poll(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
struct adiv5_dap *swjdp = armv7a->arm.dap;
enum target_state prev_target_state = target->state;
/* toggle to another core is done by gdb as follow */
(target->gdb_service) &&
(target->gdb_service->target == NULL)) {
target->gdb_service->target =
- get_cortex_a8(target, target->gdb_service->core[1]);
+ get_cortex_a(target, target->gdb_service->core[1]);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return retval;
}
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- cortex_a8->cpudbg_dscr = dscr;
+ cortex_a->cpudbg_dscr = dscr;
if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) {
if (prev_target_state != TARGET_HALTED) {
if ((prev_target_state == TARGET_RUNNING)
|| (prev_target_state == TARGET_UNKNOWN)
|| (prev_target_state == TARGET_RESET)) {
- retval = cortex_a8_debug_entry(target);
+ retval = cortex_a_debug_entry(target);
if (retval != ERROR_OK)
return retval;
if (target->smp) {
if (prev_target_state == TARGET_DEBUG_RUNNING) {
LOG_DEBUG(" ");
- retval = cortex_a8_debug_entry(target);
+ retval = cortex_a_debug_entry(target);
if (retval != ERROR_OK)
return retval;
if (target->smp) {
return retval;
}
-static int cortex_a8_halt(struct target *target)
+static int cortex_a_halt(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
return ERROR_OK;
}
-static int cortex_a8_internal_restore(struct target *target, int current,
+static int cortex_a_internal_restore(struct target *target, int current,
uint32_t *address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
/* called it now before restoring context because it uses cpu
* register r0 for restoring cp15 control register */
- retval = cortex_a8_restore_cp15_control_reg(target);
+ retval = cortex_a_restore_cp15_control_reg(target);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_restore_context(target, handle_breakpoints);
+ retval = cortex_a_restore_context(target, handle_breakpoints);
if (retval != ERROR_OK)
return retval;
target->debug_reason = DBG_REASON_NOTHALTED;
return retval;
}
-static int cortex_a8_internal_restart(struct target *target)
+static int cortex_a_internal_restart(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
return ERROR_OK;
}
-static int cortex_a8_restore_smp(struct target *target, int handle_breakpoints)
+static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
{
int retval = 0;
struct target_list *head;
curr = head->target;
if ((curr != target) && (curr->state != TARGET_RUNNING)) {
/* resume current address , not in step mode */
- retval += cortex_a8_internal_restore(curr, 1, &address,
+ retval += cortex_a_internal_restore(curr, 1, &address,
handle_breakpoints, 0);
- retval += cortex_a8_internal_restart(curr);
+ retval += cortex_a_internal_restart(curr);
}
head = head->next;
return retval;
}
-static int cortex_a8_resume(struct target *target, int current,
+static int cortex_a_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
int retval = 0;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
return 0;
}
- cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
+ cortex_a_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
if (target->smp) {
target->gdb_service->core[0] = -1;
- retval = cortex_a8_restore_smp(target, handle_breakpoints);
+ retval = cortex_a_restore_smp(target, handle_breakpoints);
if (retval != ERROR_OK)
return retval;
}
- cortex_a8_internal_restart(target);
+ cortex_a_internal_restart(target);
if (!debug_execution) {
target->state = TARGET_RUNNING;
return ERROR_OK;
}
-static int cortex_a8_debug_entry(struct target *target)
+static int cortex_a_debug_entry(struct target *target)
{
int i;
uint32_t regfile[16], cpsr, dscr;
int retval = ERROR_OK;
struct working_area *regfile_working_area = NULL;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
struct adiv5_dap *swjdp = armv7a->arm.dap;
struct reg *reg;
- LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
+ LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
/* REVISIT surely we should not re-read DSCR !! */
retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
if (retval != ERROR_OK)
return retval;
- /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
+ /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
* imprecise data aborts get discarded by issuing a Data
* Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
*/
return retval;
/* Examine debug reason */
- arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
+ arm_dpm_report_dscr(&armv7a->dpm, cortex_a->cpudbg_dscr);
/* save address of instruction that triggered the watchpoint? */
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
/* REVISIT fast_reg_read is never set ... */
/* Examine target state and mode */
- if (cortex_a8->fast_reg_read)
+ if (cortex_a->fast_reg_read)
target_alloc_working_area(target, 64, ®file_working_area);
/* First load register acessible through core debug port*/
if (!regfile_working_area)
retval = arm_dpm_read_current_registers(&armv7a->dpm);
else {
- retval = cortex_a8_read_regs_through_mem(target,
+ retval = cortex_a_read_regs_through_mem(target,
regfile_working_area->address, regfile);
target_free_working_area(target, regfile_working_area);
return retval;
/* read Current PSR */
- retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ retval = cortex_a_dap_read_coreregister_u32(target, &cpsr, 16);
/* store current cpsr */
if (retval != ERROR_OK)
return retval;
#if 0
/* TODO, Move this */
uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
- cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
+ cortex_a_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
- cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
+ cortex_a_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
- cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
+ cortex_a_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
#endif
return retval;
}
-static int cortex_a8_post_debug_entry(struct target *target)
+static int cortex_a_post_debug_entry(struct target *target)
{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
int retval;
/* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
retval = armv7a->arm.mrc(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
- &cortex_a8->cp15_control_reg);
+ &cortex_a->cp15_control_reg);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
- cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg;
+ LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg);
+ cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg;
if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1)
armv7a_identify_cache(target);
armv7a->armv7a_mmu.mmu_enabled = 0;
} else {
armv7a->armv7a_mmu.mmu_enabled =
- (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
+ (cortex_a->cp15_control_reg & 0x1U) ? 1 : 0;
}
armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled =
- (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
+ (cortex_a->cp15_control_reg & 0x4U) ? 1 : 0;
armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled =
- (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
- cortex_a8->curr_mode = armv7a->arm.core_mode;
+ (cortex_a->cp15_control_reg & 0x1000U) ? 1 : 0;
+ cortex_a->curr_mode = armv7a->arm.core_mode;
return ERROR_OK;
}
-static int cortex_a8_step(struct target *target, int current, uint32_t address,
+static int cortex_a_step(struct target *target, int current, uint32_t address,
int handle_breakpoints)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
address = buf_get_u32(r->value, 0, 32);
/* The front-end may request us not to handle breakpoints.
- * But since Cortex-A8 uses breakpoint for single step,
+ * But since Cortex-A uses breakpoint for single step,
* we MUST handle breakpoints.
*/
handle_breakpoints = 1;
if (handle_breakpoints) {
breakpoint = breakpoint_find(target, address);
if (breakpoint)
- cortex_a8_unset_breakpoint(target, breakpoint);
+ cortex_a_unset_breakpoint(target, breakpoint);
}
/* Setup single step breakpoint */
stepbreakpoint.set = 0;
/* Break on IVA mismatch */
- cortex_a8_set_breakpoint(target, &stepbreakpoint, 0x04);
+ cortex_a_set_breakpoint(target, &stepbreakpoint, 0x04);
target->debug_reason = DBG_REASON_SINGLESTEP;
- retval = cortex_a8_resume(target, 1, address, 0, 0);
+ retval = cortex_a_resume(target, 1, address, 0, 0);
if (retval != ERROR_OK)
return retval;
long long then = timeval_ms();
while (target->state != TARGET_HALTED) {
- retval = cortex_a8_poll(target);
+ retval = cortex_a_poll(target);
if (retval != ERROR_OK)
return retval;
if (timeval_ms() > then + 1000) {
}
}
- cortex_a8_unset_breakpoint(target, &stepbreakpoint);
+ cortex_a_unset_breakpoint(target, &stepbreakpoint);
target->debug_reason = DBG_REASON_BREAKPOINT;
if (breakpoint)
- cortex_a8_set_breakpoint(target, breakpoint, 0);
+ cortex_a_set_breakpoint(target, breakpoint, 0);
if (target->state != TARGET_HALTED)
LOG_DEBUG("target stepped");
return ERROR_OK;
}
-static int cortex_a8_restore_context(struct target *target, bool bpwp)
+static int cortex_a_restore_context(struct target *target, bool bpwp)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
}
/*
- * Cortex-A8 Breakpoint and watchpoint functions
+ * Cortex-A Breakpoint and watchpoint functions
*/
/* Setup hardware Breakpoint Register Pair */
-static int cortex_a8_set_breakpoint(struct target *target,
+static int cortex_a_set_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode)
{
int retval;
int brp_i = 0;
uint32_t control;
uint8_t byte_addr_select = 0x0F;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct cortex_a8_brp *brp_list = cortex_a8->brp_list;
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
+ struct cortex_a_brp *brp_list = cortex_a->brp_list;
if (breakpoint->set) {
LOG_WARNING("breakpoint already set");
}
if (breakpoint->type == BKPT_HARD) {
- while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num))
+ while (brp_list[brp_i].used && (brp_i < cortex_a->brp_num))
brp_i++;
- if (brp_i >= cortex_a8->brp_num) {
+ if (brp_i >= cortex_a->brp_num) {
LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
brp_list[brp_i].used = 1;
brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_i].control = control;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return ERROR_OK;
}
-static int cortex_a8_set_context_breakpoint(struct target *target,
+static int cortex_a_set_context_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode)
{
int retval = ERROR_FAIL;
int brp_i = 0;
uint32_t control;
uint8_t byte_addr_select = 0x0F;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct cortex_a8_brp *brp_list = cortex_a8->brp_list;
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
+ struct cortex_a_brp *brp_list = cortex_a->brp_list;
if (breakpoint->set) {
LOG_WARNING("breakpoint already set");
}
/*check available context BRPs*/
while ((brp_list[brp_i].used ||
- (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < cortex_a8->brp_num))
+ (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < cortex_a->brp_num))
brp_i++;
- if (brp_i >= cortex_a8->brp_num) {
+ if (brp_i >= cortex_a->brp_num) {
LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
return ERROR_FAIL;
}
brp_list[brp_i].used = 1;
brp_list[brp_i].value = (breakpoint->asid);
brp_list[brp_i].control = control;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
}
-static int cortex_a8_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
+static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval = ERROR_FAIL;
int brp_1 = 0; /* holds the contextID pair */
uint8_t IVA_byte_addr_select = 0x0F;
uint8_t CTX_machmode = 0x03;
uint8_t IVA_machmode = 0x01;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct cortex_a8_brp *brp_list = cortex_a8->brp_list;
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
+ struct cortex_a_brp *brp_list = cortex_a->brp_list;
if (breakpoint->set) {
LOG_WARNING("breakpoint already set");
}
/*check available context BRPs*/
while ((brp_list[brp_1].used ||
- (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a8->brp_num))
+ (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a->brp_num))
brp_1++;
printf("brp(CTX) found num: %d\n", brp_1);
- if (brp_1 >= cortex_a8->brp_num) {
+ if (brp_1 >= cortex_a->brp_num) {
LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
return ERROR_FAIL;
}
while ((brp_list[brp_2].used ||
- (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a8->brp_num))
+ (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a->brp_num))
brp_2++;
printf("brp(IVA) found num: %d\n", brp_2);
- if (brp_2 >= cortex_a8->brp_num) {
+ if (brp_2 >= cortex_a->brp_num) {
LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
return ERROR_FAIL;
}
brp_list[brp_1].used = 1;
brp_list[brp_1].value = (breakpoint->asid);
brp_list[brp_1].control = control_CTX;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn,
brp_list[brp_1].value);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn,
brp_list[brp_1].control);
if (retval != ERROR_OK)
brp_list[brp_2].used = 1;
brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_2].control = control_IVA;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn,
brp_list[brp_2].value);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn,
brp_list[brp_2].control);
if (retval != ERROR_OK)
return ERROR_OK;
}
-static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
+static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct cortex_a8_brp *brp_list = cortex_a8->brp_list;
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
+ struct cortex_a_brp *brp_list = cortex_a->brp_list;
if (!breakpoint->set) {
LOG_WARNING("breakpoint not set");
if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
int brp_i = breakpoint->set - 1;
int brp_j = breakpoint->linked_BRP;
- if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) {
+ if ((brp_i < 0) || (brp_i >= cortex_a->brp_num)) {
LOG_DEBUG("Invalid BRP number in breakpoint");
return ERROR_OK;
}
brp_list[brp_i].used = 0;
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
- if ((brp_j < 0) || (brp_j >= cortex_a8->brp_num)) {
+ if ((brp_j < 0) || (brp_j >= cortex_a->brp_num)) {
LOG_DEBUG("Invalid BRP number in breakpoint");
return ERROR_OK;
}
brp_list[brp_j].used = 0;
brp_list[brp_j].value = 0;
brp_list[brp_j].control = 0;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_j].BRPn,
brp_list[brp_j].control);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_j].BRPn,
brp_list[brp_j].value);
if (retval != ERROR_OK)
} else {
int brp_i = breakpoint->set - 1;
- if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) {
+ if ((brp_i < 0) || (brp_i >= cortex_a->brp_num)) {
LOG_DEBUG("Invalid BRP number in breakpoint");
return ERROR_OK;
}
brp_list[brp_i].used = 0;
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
- retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return ERROR_OK;
}
-static int cortex_a8_add_breakpoint(struct target *target,
+static int cortex_a_add_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
- if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) {
+ if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
LOG_INFO("no hardware breakpoint available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->type == BKPT_HARD)
- cortex_a8->brp_num_available--;
+ cortex_a->brp_num_available--;
- return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
+ return cortex_a_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
}
-static int cortex_a8_add_context_breakpoint(struct target *target,
+static int cortex_a_add_context_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
- if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) {
+ if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
LOG_INFO("no hardware breakpoint available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->type == BKPT_HARD)
- cortex_a8->brp_num_available--;
+ cortex_a->brp_num_available--;
- return cortex_a8_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */
+ return cortex_a_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */
}
-static int cortex_a8_add_hybrid_breakpoint(struct target *target,
+static int cortex_a_add_hybrid_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
- if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) {
+ if ((breakpoint->type == BKPT_HARD) && (cortex_a->brp_num_available < 1)) {
LOG_INFO("no hardware breakpoint available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->type == BKPT_HARD)
- cortex_a8->brp_num_available--;
+ cortex_a->brp_num_available--;
- return cortex_a8_set_hybrid_breakpoint(target, breakpoint); /* ??? */
+ return cortex_a_set_hybrid_breakpoint(target, breakpoint); /* ??? */
}
-static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
+static int cortex_a_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
#if 0
/* It is perfectly possible to remove breakpoints while the target is running */
#endif
if (breakpoint->set) {
- cortex_a8_unset_breakpoint(target, breakpoint);
+ cortex_a_unset_breakpoint(target, breakpoint);
if (breakpoint->type == BKPT_HARD)
- cortex_a8->brp_num_available++;
+ cortex_a->brp_num_available++;
}
}
/*
- * Cortex-A8 Reset functions
+ * Cortex-A Reset functions
*/
-static int cortex_a8_assert_reset(struct target *target)
+static int cortex_a_assert_reset(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
return ERROR_OK;
}
-static int cortex_a8_deassert_reset(struct target *target)
+static int cortex_a_deassert_reset(struct target *target)
{
int retval;
/* be certain SRST is off */
jtag_add_reset(0, 0);
- retval = cortex_a8_poll(target);
+ retval = cortex_a_poll(target);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
-static int cortex_a8_write_apb_ab_memory(struct target *target,
+static int cortex_a_write_apb_ab_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, const uint8_t *buffer)
{
return retval;
/* This algorithm comes from either :
- * Cortex-A8 TRM Example 12-25
+ * Cortex-A TRM Example 12-25
* Cortex-R4 TRM Example 11-26
* (slight differences)
*/
/* First bytes not aligned - read the 32 bit word to avoid corrupting
* the other bytes in the word.
*/
- retval = cortex_a8_read_apb_ab_memory(target, (address & ~0x3), 4, 1, tmp_buff);
+ retval = cortex_a_read_apb_ab_memory(target, (address & ~0x3), 4, 1, tmp_buff);
if (retval != ERROR_OK)
goto error_free_buff_w;
}
/* Read the last word to avoid corruption during 32 bit write */
int mem_offset = (total_u32-1) * 4;
- retval = cortex_a8_read_apb_ab_memory(target, (address & ~0x3) + mem_offset, 4, 1, &tmp_buff[mem_offset]);
+ retval = cortex_a_read_apb_ab_memory(target, (address & ~0x3) + mem_offset, 4, 1, &tmp_buff[mem_offset]);
if (retval != ERROR_OK)
goto error_free_buff_w;
}
return ERROR_FAIL;
}
-static int cortex_a8_read_apb_ab_memory(struct target *target,
+static int cortex_a_read_apb_ab_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
armv7a->debug_base + CPUDBG_DSCR, &dscr);
/* This algorithm comes from either :
- * Cortex-A8 TRM Example 12-24
+ * Cortex-A TRM Example 12-24
* Cortex-R4 TRM Example 11-25
* (slight differences)
*/
retval += mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, address & ~0x3);
/* - Copy value from DTRRX to R0 using instruction mrc p14, 0, r0, c5, c0 */
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
+ cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
/* Write the data transfer instruction (ldc p14, c5, [r0],4)
* and the DTR mode setting to fast mode
/*
- * Cortex-A8 Memory access
+ * Cortex-A Memory access
*
* This is same Cortex M3 but we must also use the correct
* ap number for every access.
*/
-static int cortex_a8_read_phys_memory(struct target *target,
+static int cortex_a_read_phys_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
/* read memory through APB-AP */
if (!armv7a->is_armv7r) {
/* disable mmu */
- retval = cortex_a8_mmu_modify(target, 0);
+ retval = cortex_a_mmu_modify(target, 0);
if (retval != ERROR_OK)
return retval;
}
- retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer);
+ retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
}
}
return retval;
}
-static int cortex_a8_read_memory(struct target *target, uint32_t address,
+static int cortex_a_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
int mmu_enabled = 0;
struct adiv5_dap *swjdp = armv7a->arm.dap;
uint8_t apsel = swjdp->apsel;
- /* cortex_a8 handles unaligned memory access */
+ /* cortex_a handles unaligned memory access */
LOG_DEBUG("Reading memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
size, count);
/* determine if MMU was enabled on target stop */
if (!armv7a->is_armv7r) {
- retval = cortex_a8_mmu(target, &mmu_enabled);
+ retval = cortex_a_mmu(target, &mmu_enabled);
if (retval != ERROR_OK)
return retval;
}
if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
if (mmu_enabled) {
virt = address;
- retval = cortex_a8_virt2phys(target, virt, &phys);
+ retval = cortex_a_virt2phys(target, virt, &phys);
if (retval != ERROR_OK)
return retval;
virt, phys);
address = phys;
}
- retval = cortex_a8_read_phys_memory(target, address, size, count, buffer);
+ retval = cortex_a_read_phys_memory(target, address, size, count, buffer);
} else {
if (mmu_enabled) {
- retval = cortex_a8_check_address(target, address);
+ retval = cortex_a_check_address(target, address);
if (retval != ERROR_OK)
return retval;
/* enable MMU as we could have disabled it for phys access */
- retval = cortex_a8_mmu_modify(target, 1);
+ retval = cortex_a_mmu_modify(target, 1);
if (retval != ERROR_OK)
return retval;
}
- retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer);
+ retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
}
return retval;
}
-static int cortex_a8_write_phys_memory(struct target *target,
+static int cortex_a_write_phys_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, const uint8_t *buffer)
{
/* write memory through APB-AP */
if (!armv7a->is_armv7r) {
- retval = cortex_a8_mmu_modify(target, 0);
+ retval = cortex_a_mmu_modify(target, 0);
if (retval != ERROR_OK)
return retval;
}
- return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer);
+ return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
}
}
* wrong addresses will be invalidated!
*
* For both ICache and DCache, walk all cache lines in the
- * address range. Cortex-A8 has fixed 64 byte line length.
+ * address range. Cortex-A has fixed 64 byte line length.
*
* REVISIT per ARMv7, these may trigger watchpoints ...
*/
return retval;
}
-static int cortex_a8_write_memory(struct target *target, uint32_t address,
+static int cortex_a_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int mmu_enabled = 0;
struct adiv5_dap *swjdp = armv7a->arm.dap;
uint8_t apsel = swjdp->apsel;
- /* cortex_a8 handles unaligned memory access */
+ /* cortex_a handles unaligned memory access */
LOG_DEBUG("Writing memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
size, count);
/* determine if MMU was enabled on target stop */
if (!armv7a->is_armv7r) {
- retval = cortex_a8_mmu(target, &mmu_enabled);
+ retval = cortex_a_mmu(target, &mmu_enabled);
if (retval != ERROR_OK)
return retval;
}
count);
if (mmu_enabled) {
virt = address;
- retval = cortex_a8_virt2phys(target, virt, &phys);
+ retval = cortex_a_virt2phys(target, virt, &phys);
if (retval != ERROR_OK)
return retval;
phys);
address = phys;
}
- retval = cortex_a8_write_phys_memory(target, address, size,
+ retval = cortex_a_write_phys_memory(target, address, size,
count, buffer);
} else {
if (mmu_enabled) {
- retval = cortex_a8_check_address(target, address);
+ retval = cortex_a_check_address(target, address);
if (retval != ERROR_OK)
return retval;
/* enable MMU as we could have disabled it for phys access */
- retval = cortex_a8_mmu_modify(target, 1);
+ retval = cortex_a_mmu_modify(target, 1);
if (retval != ERROR_OK)
return retval;
}
- retval = cortex_a8_write_apb_ab_memory(target, address, size, count, buffer);
+ retval = cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
}
return retval;
}
-static int cortex_a8_handle_target_request(void *priv)
+static int cortex_a_handle_target_request(void *priv)
{
struct target *target = priv;
struct armv7a_common *armv7a = target_to_armv7a(target);
}
/*
- * Cortex-A8 target information and configuration
+ * Cortex-A target information and configuration
*/
-static int cortex_a8_examine_first(struct target *target)
+static int cortex_a_examine_first(struct target *target)
{
- struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
struct adiv5_dap *swjdp = armv7a->arm.dap;
int i;
int retval = ERROR_OK;
LOG_DEBUG("didr = 0x%08" PRIx32, didr);
armv7a->arm.core_type = ARM_MODE_MON;
- retval = cortex_a8_dpm_setup(cortex_a8, didr);
+ retval = cortex_a_dpm_setup(cortex_a, didr);
if (retval != ERROR_OK)
return retval;
/* Setup Breakpoint Register Pairs */
- cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
- cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
- cortex_a8->brp_num_available = cortex_a8->brp_num;
- cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp));
-/* cortex_a8->brb_enabled = ????; */
- for (i = 0; i < cortex_a8->brp_num; i++) {
- cortex_a8->brp_list[i].used = 0;
- if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context))
- cortex_a8->brp_list[i].type = BRP_NORMAL;
+ cortex_a->brp_num = ((didr >> 24) & 0x0F) + 1;
+ cortex_a->brp_num_context = ((didr >> 20) & 0x0F) + 1;
+ cortex_a->brp_num_available = cortex_a->brp_num;
+ cortex_a->brp_list = calloc(cortex_a->brp_num, sizeof(struct cortex_a_brp));
+/* cortex_a->brb_enabled = ????; */
+ for (i = 0; i < cortex_a->brp_num; i++) {
+ cortex_a->brp_list[i].used = 0;
+ if (i < (cortex_a->brp_num-cortex_a->brp_num_context))
+ cortex_a->brp_list[i].type = BRP_NORMAL;
else
- cortex_a8->brp_list[i].type = BRP_CONTEXT;
- cortex_a8->brp_list[i].value = 0;
- cortex_a8->brp_list[i].control = 0;
- cortex_a8->brp_list[i].BRPn = i;
+ cortex_a->brp_list[i].type = BRP_CONTEXT;
+ cortex_a->brp_list[i].value = 0;
+ cortex_a->brp_list[i].control = 0;
+ cortex_a->brp_list[i].BRPn = i;
}
- LOG_DEBUG("Configured %i hw breakpoints", cortex_a8->brp_num);
+ LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
target_set_examined(target);
return ERROR_OK;
}
-static int cortex_a8_examine(struct target *target)
+static int cortex_a_examine(struct target *target)
{
int retval = ERROR_OK;
/* don't re-probe hardware after each reset */
if (!target_was_examined(target))
- retval = cortex_a8_examine_first(target);
+ retval = cortex_a_examine_first(target);
/* Configure core debug access */
if (retval == ERROR_OK)
- retval = cortex_a8_init_debug_access(target);
+ retval = cortex_a_init_debug_access(target);
return retval;
}
/*
- * Cortex-A8 target creation and initialization
+ * Cortex-A target creation and initialization
*/
-static int cortex_a8_init_target(struct command_context *cmd_ctx,
+static int cortex_a_init_target(struct command_context *cmd_ctx,
struct target *target)
{
/* examine_first() does a bunch of this */
return ERROR_OK;
}
-static int cortex_a8_init_arch_info(struct target *target,
- struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
+static int cortex_a_init_arch_info(struct target *target,
+ struct cortex_a_common *cortex_a, struct jtag_tap *tap)
{
- struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
struct adiv5_dap *dap = &armv7a->dap;
armv7a->arm.dap = dap;
- /* Setup struct cortex_a8_common */
- cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
+ /* Setup struct cortex_a_common */
+ cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
/* tap has no dap initialized */
if (!tap->dap) {
armv7a->arm.dap = dap;
- /* Setup struct cortex_a8_common */
+ /* Setup struct cortex_a_common */
/* prepare JTAG information for the new target */
- cortex_a8->jtag_info.tap = tap;
- cortex_a8->jtag_info.scann_size = 4;
+ cortex_a->jtag_info.tap = tap;
+ cortex_a->jtag_info.scann_size = 4;
/* Leave (only) generic DAP stuff for debugport_init() */
- dap->jtag_info = &cortex_a8->jtag_info;
+ dap->jtag_info = &cortex_a->jtag_info;
/* Number of bits for tar autoincrement, impl. dep. at least 10 */
dap->tar_autoincr_block = (1 << 10);
} else
armv7a->arm.dap = tap->dap;
- cortex_a8->fast_reg_read = 0;
+ cortex_a->fast_reg_read = 0;
/* register arch-specific functions */
armv7a->examine_debug_reason = NULL;
- armv7a->post_debug_entry = cortex_a8_post_debug_entry;
+ armv7a->post_debug_entry = cortex_a_post_debug_entry;
armv7a->pre_restore_context = NULL;
- armv7a->armv7a_mmu.read_physical_memory = cortex_a8_read_phys_memory;
+ armv7a->armv7a_mmu.read_physical_memory = cortex_a_read_phys_memory;
-/* arm7_9->handle_target_request = cortex_a8_handle_target_request; */
+/* arm7_9->handle_target_request = cortex_a_handle_target_request; */
/* REVISIT v7a setup should be in a v7a-specific routine */
armv7a_init_arch_info(target, armv7a);
- target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
+ target_register_timer_callback(cortex_a_handle_target_request, 1, 1, target);
return ERROR_OK;
}
-static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
+static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
{
- struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
+ struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
- cortex_a8->armv7a_common.is_armv7r = false;
+ cortex_a->armv7a_common.is_armv7r = false;
- return cortex_a8_init_arch_info(target, cortex_a8, target->tap);
+ return cortex_a_init_arch_info(target, cortex_a, target->tap);
}
static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
{
- struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
+ struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
- cortex_a8->armv7a_common.is_armv7r = true;
+ cortex_a->armv7a_common.is_armv7r = true;
- return cortex_a8_init_arch_info(target, cortex_a8, target->tap);
+ return cortex_a_init_arch_info(target, cortex_a, target->tap);
}
-static int cortex_a8_mmu(struct target *target, int *enabled)
+static int cortex_a_mmu(struct target *target, int *enabled)
{
if (target->state != TARGET_HALTED) {
LOG_ERROR("%s: target not halted", __func__);
return ERROR_TARGET_INVALID;
}
- *enabled = target_to_cortex_a8(target)->armv7a_common.armv7a_mmu.mmu_enabled;
+ *enabled = target_to_cortex_a(target)->armv7a_common.armv7a_mmu.mmu_enabled;
return ERROR_OK;
}
-static int cortex_a8_virt2phys(struct target *target,
+static int cortex_a_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys)
{
int retval = ERROR_FAIL;
*phys = ret;
} else {/* use this method if armv7a->memory_ap not selected
* mmu must be enable in order to get a correct translation */
- retval = cortex_a8_mmu_modify(target, 1);
+ retval = cortex_a_mmu_modify(target, 1);
if (retval != ERROR_OK)
goto done;
retval = armv7a_mmu_translate_va_pa(target, virt, phys, 1);
return retval;
}
-COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
+COMMAND_HANDLER(cortex_a_handle_cache_info_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7a_common *armv7a = target_to_armv7a(target);
}
-COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
+COMMAND_HANDLER(cortex_a_handle_dbginit_command)
{
struct target *target = get_current_target(CMD_CTX);
if (!target_was_examined(target)) {
return ERROR_FAIL;
}
- return cortex_a8_init_debug_access(target);
+ return cortex_a_init_debug_access(target);
}
-COMMAND_HANDLER(cortex_a8_handle_smp_off_command)
+COMMAND_HANDLER(cortex_a_handle_smp_off_command)
{
struct target *target = get_current_target(CMD_CTX);
/* check target is an smp target */
return ERROR_OK;
}
-COMMAND_HANDLER(cortex_a8_handle_smp_on_command)
+COMMAND_HANDLER(cortex_a_handle_smp_on_command)
{
struct target *target = get_current_target(CMD_CTX);
struct target_list *head;
return ERROR_OK;
}
-COMMAND_HANDLER(cortex_a8_handle_smp_gdb_command)
+COMMAND_HANDLER(cortex_a_handle_smp_gdb_command)
{
struct target *target = get_current_target(CMD_CTX);
int retval = ERROR_OK;
return ERROR_OK;
}
-static const struct command_registration cortex_a8_exec_command_handlers[] = {
+static const struct command_registration cortex_a_exec_command_handlers[] = {
{
.name = "cache_info",
- .handler = cortex_a8_handle_cache_info_command,
+ .handler = cortex_a_handle_cache_info_command,
.mode = COMMAND_EXEC,
.help = "display information about target caches",
.usage = "",
},
{
.name = "dbginit",
- .handler = cortex_a8_handle_dbginit_command,
+ .handler = cortex_a_handle_dbginit_command,
.mode = COMMAND_EXEC,
.help = "Initialize core debug",
.usage = "",
},
{ .name = "smp_off",
- .handler = cortex_a8_handle_smp_off_command,
+ .handler = cortex_a_handle_smp_off_command,
.mode = COMMAND_EXEC,
.help = "Stop smp handling",
.usage = "",},
{
.name = "smp_on",
- .handler = cortex_a8_handle_smp_on_command,
+ .handler = cortex_a_handle_smp_on_command,
.mode = COMMAND_EXEC,
.help = "Restart smp handling",
.usage = "",
},
{
.name = "smp_gdb",
- .handler = cortex_a8_handle_smp_gdb_command,
+ .handler = cortex_a_handle_smp_gdb_command,
.mode = COMMAND_EXEC,
.help = "display/fix current core played to gdb",
.usage = "",
COMMAND_REGISTRATION_DONE
};
-static const struct command_registration cortex_a8_command_handlers[] = {
+static const struct command_registration cortex_a_command_handlers[] = {
{
.chain = arm_command_handlers,
},
.mode = COMMAND_ANY,
.help = "Cortex-A command group",
.usage = "",
- .chain = cortex_a8_exec_command_handlers,
+ .chain = cortex_a_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
-struct target_type cortexa8_target = {
+struct target_type cortexa_target = {
.name = "cortex_a",
.deprecated_name = "cortex_a8",
- .poll = cortex_a8_poll,
+ .poll = cortex_a_poll,
.arch_state = armv7a_arch_state,
- .halt = cortex_a8_halt,
- .resume = cortex_a8_resume,
- .step = cortex_a8_step,
+ .halt = cortex_a_halt,
+ .resume = cortex_a_resume,
+ .step = cortex_a_step,
- .assert_reset = cortex_a8_assert_reset,
- .deassert_reset = cortex_a8_deassert_reset,
+ .assert_reset = cortex_a_assert_reset,
+ .deassert_reset = cortex_a_deassert_reset,
/* REVISIT allow exporting VFP3 registers ... */
.get_gdb_reg_list = arm_get_gdb_reg_list,
- .read_memory = cortex_a8_read_memory,
- .write_memory = cortex_a8_write_memory,
+ .read_memory = cortex_a_read_memory,
+ .write_memory = cortex_a_write_memory,
.checksum_memory = arm_checksum_memory,
.blank_check_memory = arm_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
- .add_breakpoint = cortex_a8_add_breakpoint,
- .add_context_breakpoint = cortex_a8_add_context_breakpoint,
- .add_hybrid_breakpoint = cortex_a8_add_hybrid_breakpoint,
- .remove_breakpoint = cortex_a8_remove_breakpoint,
+ .add_breakpoint = cortex_a_add_breakpoint,
+ .add_context_breakpoint = cortex_a_add_context_breakpoint,
+ .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint,
+ .remove_breakpoint = cortex_a_remove_breakpoint,
.add_watchpoint = NULL,
.remove_watchpoint = NULL,
- .commands = cortex_a8_command_handlers,
- .target_create = cortex_a8_target_create,
- .init_target = cortex_a8_init_target,
- .examine = cortex_a8_examine,
+ .commands = cortex_a_command_handlers,
+ .target_create = cortex_a_target_create,
+ .init_target = cortex_a_init_target,
+ .examine = cortex_a_examine,
- .read_phys_memory = cortex_a8_read_phys_memory,
- .write_phys_memory = cortex_a8_write_phys_memory,
- .mmu = cortex_a8_mmu,
- .virt2phys = cortex_a8_virt2phys,
+ .read_phys_memory = cortex_a_read_phys_memory,
+ .write_phys_memory = cortex_a_write_phys_memory,
+ .mmu = cortex_a_mmu,
+ .virt2phys = cortex_a_virt2phys,
};
static const struct command_registration cortex_r4_exec_command_handlers[] = {
{
.name = "cache_info",
- .handler = cortex_a8_handle_cache_info_command,
+ .handler = cortex_a_handle_cache_info_command,
.mode = COMMAND_EXEC,
.help = "display information about target caches",
.usage = "",
},
{
.name = "dbginit",
- .handler = cortex_a8_handle_dbginit_command,
+ .handler = cortex_a_handle_dbginit_command,
.mode = COMMAND_EXEC,
.help = "Initialize core debug",
.usage = "",
struct target_type cortexr4_target = {
.name = "cortex_r4",
- .poll = cortex_a8_poll,
+ .poll = cortex_a_poll,
.arch_state = armv7a_arch_state,
- .halt = cortex_a8_halt,
- .resume = cortex_a8_resume,
- .step = cortex_a8_step,
+ .halt = cortex_a_halt,
+ .resume = cortex_a_resume,
+ .step = cortex_a_step,
- .assert_reset = cortex_a8_assert_reset,
- .deassert_reset = cortex_a8_deassert_reset,
+ .assert_reset = cortex_a_assert_reset,
+ .deassert_reset = cortex_a_deassert_reset,
/* REVISIT allow exporting VFP3 registers ... */
.get_gdb_reg_list = arm_get_gdb_reg_list,
- .read_memory = cortex_a8_read_memory,
- .write_memory = cortex_a8_write_memory,
+ .read_memory = cortex_a_read_memory,
+ .write_memory = cortex_a_write_memory,
.checksum_memory = arm_checksum_memory,
.blank_check_memory = arm_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
- .add_breakpoint = cortex_a8_add_breakpoint,
- .add_context_breakpoint = cortex_a8_add_context_breakpoint,
- .add_hybrid_breakpoint = cortex_a8_add_hybrid_breakpoint,
- .remove_breakpoint = cortex_a8_remove_breakpoint,
+ .add_breakpoint = cortex_a_add_breakpoint,
+ .add_context_breakpoint = cortex_a_add_context_breakpoint,
+ .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint,
+ .remove_breakpoint = cortex_a_remove_breakpoint,
.add_watchpoint = NULL,
.remove_watchpoint = NULL,
.commands = cortex_r4_command_handlers,
.target_create = cortex_r4_target_create,
- .init_target = cortex_a8_init_target,
- .examine = cortex_a8_examine,
+ .init_target = cortex_a_init_target,
+ .examine = cortex_a_examine,
};
Code Review / openocd.git / commitdiff