tcl/target/stm32f3: fix reset init for stlink

Use mmw to manipulate only selected bits of the word. msb and mwb verify the
memory location and may error on PLLRDY set as a result of PLLON written.

Change-Id: I9a4c1e58f002a1e5e99be1bd34aac27ba65d111d
Reported-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2702
Tested-by: jenkins

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index f3c22af7ae2a9a570f7bdd938053c6976ac9c81e..ca8e6e1d8cb9db92998c15539719d7d694e5bfc5 100644 (file)
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -104,11 +104,11 @@ proc stm32f3x_default_examine_end {} {
 
 proc stm32f3x_default_reset_init {} {
        # Configure PLL to boost clock to HSI x 8 (64 MHz)
-       mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
-       mwh 0x40021002 0x0100     ;# RCC_CR[31:16] = PLLON
-       mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
-       sleep 10                  ;# Wait for PLL to lock
-       mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1]
+       mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+       mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
+       mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
+       sleep 10                    ;# Wait for PLL to lock
+       mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
        # Boost JTAG frequency
        adapter_khz 8000