Signed-off-by: Yauheni Kaliuta <y.kaliuta@gmail.com>
| ((len > 1) ? val[1] << 16: 0x0000);
dbg_write(dcc_data);
| ((len > 1) ? val[1] << 16: 0x0000);
dbg_write(dcc_data);
| ((len > 2) ? msg[2] << 16 : 0x00)
| ((len > 3) ? msg[3] << 24 : 0x00);
dbg_write(dcc_data);
| ((len > 2) ? msg[2] << 16 : 0x00)
| ((len > 3) ? msg[3] << 24 : 0x00);
dbg_write(dcc_data);
#include "dcc_stdio.h"
/* enable openocd debugmsg at the gdb prompt:
#include "dcc_stdio.h"
/* enable openocd debugmsg at the gdb prompt:
- * monitor target_request debugmsgs enable
- *
+ * monitor target_request debugmsgs enable
+ *
* create a trace point:
* monitor trace point 1
* create a trace point:
* monitor trace point 1
* to show how often the trace point was hit:
* monitor trace point
*/
* to show how often the trace point was hit:
* monitor trace point
*/
*t=0;
}
return flash_init((_printf *)&myprintf);
*t=0;
}
return flash_init((_printf *)&myprintf);
-int erase(void *address, int len)
+int erase(void *address, int len)
{
int retval;
void *failAddress;
{
int retval;
void *failAddress;
retval=checkFlash(address, len);
if (retval!=0)
return retval;
retval=checkFlash(address, len);
if (retval!=0)
return retval;
retval=init();
if (retval!=0)
return retval;
retval=init();
if (retval!=0)
return retval;
extern char _end;
// Data follows immediately after program, long word aligned.
extern char _end;
// Data follows immediately after program, long word aligned.
-int program(void *buffer, void *address, int len)
+int program(void *buffer, void *address, int len)
{
int retval;
void *failAddress;
retval=checkFlash(address, len);
if (retval!=0)
return retval;
{
int retval;
void *failAddress;
retval=checkFlash(address, len);
if (retval!=0)
return retval;
retval=init();
if (retval!=0)
return retval;
retval=init();
if (retval!=0)
return retval;
* FPTR.TR = -------------------------------
* 512
*
* FPTR.TR = -------------------------------
* 512
*
*/
uint32_t tr_val = (uint32_t)((((time / 1e6) * clock) + 511.0) / 512.0);
*/
uint32_t tr_val = (uint32_t)((((time / 1e6) * clock) + 511.0) / 512.0);
/* FIX! we really should assert srst here, but
* how do we reset the target into the halted state?
/* FIX! we really should assert srst here, but
* how do we reset the target into the halted state?
* Also arm11 behaves "funny" when srst is asserted
* (as of writing the rules are not understood).
*/
* Also arm11 behaves "funny" when srst is asserted
* (as of writing the rules are not understood).
*/
void armv7a_show_fault_registers(target_t *target)
{
uint32_t dfsr, ifsr, dfar, ifar;
void armv7a_show_fault_registers(target_t *target)
{
uint32_t dfsr, ifsr, dfar, ifar;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
armv7a->read_cp15(target, 0, 0, 6, 0, &dfar);
armv7a->read_cp15(target, 0, 2, 6, 0, &ifar);
armv7a->read_cp15(target, 0, 0, 6, 0, &dfar);
armv7a->read_cp15(target, 0, 2, 6, 0, &ifar);
- LOG_USER("Data fault registers DFSR: %8.8" PRIx32
+ LOG_USER("Data fault registers DFSR: %8.8" PRIx32
", DFAR: %8.8" PRIx32, dfsr, dfar);
", DFAR: %8.8" PRIx32, dfsr, dfar);
- LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+ LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
", IFAR: %8.8" PRIx32, ifsr, ifar);
}
", IFAR: %8.8" PRIx32, ifsr, ifar);
}
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
- /* Enabling of instruction execution in debug mode is done in debug_entry code */
-
+ /* Enabling of instruction execution in debug mode is done in debug_entry code */
+
/* Resync breakpoint registers */
/* Resync breakpoint registers */
/* Since this is likley called from init or reset, update targtet state information*/
cortex_a8_poll(target);
/* Since this is likley called from init or reset, update targtet state information*/
cortex_a8_poll(target);
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
}
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
}
retval = mem_ap_write_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRRX, value);
/* Move DTRRX to r0 */
retval = mem_ap_write_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRRX, value);
/* Move DTRRX to r0 */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
}
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
}
if (Rd > 16)
return retval;
if (Rd > 16)
return retval;
armv4_5_invalidate_core_regs(target);
target->state = TARGET_RESET;
armv4_5_invalidate_core_regs(target);
target->state = TARGET_RESET;
uint32_t didr, ctypr, ttypr, cpuid;
LOG_DEBUG("TODO");
uint32_t didr, ctypr, ttypr, cpuid;
LOG_DEBUG("TODO");
/* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE;
/* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE;
/* Configure core debug access */
cortex_a8_init_debug_access(target);
/* Configure core debug access */
cortex_a8_init_debug_access(target);
target->type->examined = 1;
return retval;
target->type->examined = 1;
return retval;
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