Seems after a reset the stlink is not clearing the vector catch (VC_CORERESET)
in the Debug Control Register.
This has the side effect if the user presses an external reset the core will
halt, this patch fixes that.
Change-Id: Ic3b2c3991b79cacbbd901c02b79613c2e204e71f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/905
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
static int stlink_debug_entry(struct target *target)
{
static int stlink_debug_entry(struct target *target)
{
+ struct stlink_interface_s *stlink_if = target_to_stlink(target);
struct armv7m_common *armv7m = target_to_armv7m(target);
struct arm *arm = &armv7m->arm;
struct reg *r;
struct armv7m_common *armv7m = target_to_armv7m(target);
struct arm *arm = &armv7m->arm;
struct reg *r;
stm32_stlink_load_context(target);
stm32_stlink_load_context(target);
+ /* make sure we clear the vector catch bit */
+ stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0);
+
r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
xPSR = buf_get_u32(r->value, 0, 32);
r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
xPSR = buf_get_u32(r->value, 0, 32);
}
stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN);
}
stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN);
- stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET);
+
+ /* only set vector catch if halt is requested */
+ if (target->reset_halt)
+ stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET);
+ else
+ stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0);
if (jtag_reset_config & RESET_HAS_SRST) {
if (!srst_asserted) {
if (jtag_reset_config & RESET_HAS_SRST) {
if (!srst_asserted) {
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