Change [1] introduced a regression that results in comparison
in arm_jtag_set_instr() to be always true if the length of the
IR register is not 8 bit. The value on the left side
of the != operator contains only tap->ir_length number of
bits while value on the right is full 8-bit instruction code.
This forces OpenOCD to update the JTAG IR register on each
transaction even if the instruction in the JTAG IR register
is correct. This causes noticeable performance degradation,
especially with slow JTAG adapters.
[1] https://review.openocd.org/c/openocd/+/6285
time ./src/openocd -s tcl/ -f interface/cmsis-dap.cfg \
-c "transport select jtag" -f target/psoc6.cfg \
-c "init; load_image data.bin 0x08000000; exit"
Without this change:
real 0m4,863s
user 0m0,074s
sys 0m0,128s
With this change:
real 0m3,083s
user 0m0,038s
sys 0m0,098s
Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Change-Id: Iaded83a04ecc7e65f18256afae582267ccc1fc59
Reviewed-on: https://review.openocd.org/c/openocd/+/6762
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
#define OPENOCD_TARGET_ARM_JTAG_H
#include <jtag/jtag.h>
#define OPENOCD_TARGET_ARM_JTAG_H
#include <jtag/jtag.h>
+#include <helper/bits.h>
struct arm_jtag {
struct jtag_tap *tap;
struct arm_jtag {
struct jtag_tap *tap;
uint32_t new_instr, void *no_verify_capture, tap_state_t end_state)
{
/* inline most common code path */
uint32_t new_instr, void *no_verify_capture, tap_state_t end_state)
{
/* inline most common code path */
- if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (new_instr & (BIT(tap->ir_length) - 1)))
return arm_jtag_set_instr_inner(tap, new_instr, no_verify_capture, end_state);
return ERROR_OK;
return arm_jtag_set_instr_inner(tap, new_instr, no_verify_capture, end_state);
return ERROR_OK;
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