MAINFILE = main.c
endif
-openocd_SOURCES = $(MAINFILE)
+openocd_SOURCES = $(MAINFILE)
openocd_LDADD = libopenocd.la
libopenocd_la_SOURCES = openocd.c
libopenocd_la_CPPFLAGS += $(AM_CPPFLAGS) $(CPPFLAGS)
# the library search path.
-libopenocd_la_LDFLAGS = $(all_libraries)
+libopenocd_la_LDFLAGS = $(all_libraries)
if IS_MINGW
MINGWLDADD = -lwsock32
# assumption is: You are only rebuilding the EXE.... and everything
# else is/was previously installed.
#
-# use at your own risk
+# use at your own risk
quick: all install-binPROGRAMS
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
* are met:
-*
-* 1. Redistributions of source code must retain the above copyright
+*
+* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
+* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
-* 3. Neither the name of the author nor the names of its contributors may
-* be used to endorse or promote products derived from this software
+* 3. Neither the name of the author nor the names of its contributors may
+* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
-* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*(COMMON)
. = ALIGN(4);
PROVIDE (__bss_end = .);
-
+
. = ALIGN(256);
-
+
PROVIDE (__stack_start = .);
-
+
PROVIDE (__stack_fiq_start = .);
. += FIQ_STACK_SIZE;
. = ALIGN(4);
. = ALIGN(4);
PROVIDE (__stack_svc_end = .);
PROVIDE (__stack_end = .);
- PROVIDE (__heap_start = .);
+ PROVIDE (__heap_start = .);
} > ram
-
+
}
/*** EOF ***/
/****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
* are met:
-*
-* 1. Redistributions of source code must retain the above copyright
+*
+* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
+* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
-* 3. Neither the name of the author nor the names of its contributors may
-* be used to endorse or promote products derived from this software
+* 3. Neither the name of the author nor the names of its contributors may
+* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
-* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* 18.12.06 mifi First Version
* The hardware initialization is based on the startup file
-* crtat91sam7x256_rom.S from NutOS 4.2.1.
+* crtat91sam7x256_rom.S from NutOS 4.2.1.
* Therefore partial copyright by egnite Software GmbH.
****************************************************************************/
/*
* Some defines for the program status registers
*/
- ARM_MODE_USER = 0x10 /* Normal User Mode */
+ ARM_MODE_USER = 0x10 /* Normal User Mode */
ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
ARM_MODE_MASK = 0x1F
-
+
I_BIT = 0x80 /* disable IRQ when I bit is set */
F_BIT = 0x40 /* disable IRQ when I bit is set */
-
+
/*
* Register Base Address
*/
MC_BASE = 0xFFFFFF00
MC_FMR_OFF = 0x00000060
MC_FWS_1FWS = 0x00480100
-
+
.section .vectors,"ax"
.code 32
-
+
/****************************************************************************/
/* Vector table and reset entry */
/****************************************************************************/
.section .init, "ax"
.code 32
-
+
.global ResetHandler
.global ExitFunction
.extern main
ldr r0, =WDT_WDDIS
str r0, [r1, #WDT_MR_OFF]
-
+
/*
* Enable user reset: assertion length programmed to 1ms
*/
ldr r1, =RSTC_MR
str r0, [r1, #0]
-
+
/*
* Use 2 cycles for flash access.
*/
str r0, [r1, #AIC_EOICR_OFF]
str r0, [r1, #AIC_IDCR_OFF]
-
+
/*
* Setup a stack for each mode
- */
- msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
+ */
+ msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
ldr sp, =__stack_und_end
-
+
msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
ldr sp, =__stack_abt_end
-
- msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
+
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
ldr sp, =__stack_fiq_end
-
- msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
+
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
ldr sp, =__stack_irq_end
-
+
msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
ldr sp, =__stack_svc_end
cmp r1, r2
strne r3, [r1], #+4
bne bss_clear_loop
-
-
+
+
/*
* Jump to main
*/
mrs r0, cpsr
bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
msr cpsr, r0
-
+
mov r0, #0 /* No arguments */
mov r1, #0 /* No arguments */
ldr r2, =main
mov lr, pc
bx r2 /* And jump... */
-
+
ExitFunction:
nop
nop
nop
- b ExitFunction
-
+ b ExitFunction
+
/****************************************************************************/
/* Default interrupt handler */
UndefHandler:
b UndefHandler
-
+
SWIHandler:
b SWIHandler
DAbortHandler:
b DAbortHandler
-
+
IRQHandler:
b IRQHandler
-
+
FIQHandler:
b FIQHandler
-
+
.weak ExitFunction
.weak UndefHandler, PAbortHandler, DAbortHandler
.weak IRQHandler, FIQHandler
MCU = arm7tdmi
# List all default C defines here, like -D_DEBUG=1
-DDEFS =
+DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
-DADEFS =
+DADEFS =
# List all default directories to look for include files here
-DINCDIR =
+DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
-DLIBS =
+DLIBS =
#
# End of default section
LDSCRIPT= at91sam7x_ram.ld
# List all user C define here, like -D_DEBUG=1
-UDEFS =
+UDEFS =
# Define ASM defines here
-UADEFS =
+UADEFS =
# List C source files here
SRC = main.c dcc.c samflash.c
ULIBDIR =
# List all user libraries here
-ULIBS =
+ULIBS =
# Define optimisation level here
OPT = -O2
-rm -f $(ASRC:.s=.lst)
-rm -fR .dep
-#
+#
# Include the dependency files, should be the last of the makefile
#
#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
noinst_LTLIBRARIES = libhelper.la
if ECOSBOARD
-CONFIGFILES =
+CONFIGFILES =
else
-CONFIGFILES = options.c jim.c jim-eventloop.c
+CONFIGFILES = options.c jim.c jim-eventloop.c
endif
# Show flash in human readable form
# This is an example of a human readable form of a low level fn
-proc flash_banks {} {
- set i 0
+proc flash_banks {} {
+ set i 0
set result ""
foreach {a} [ocd_flash_banks] {
if {$i > 0} {
set result "$result\n"
}
set result [format "$result#%d: %s at 0x%08x, size 0x%08x, buswidth %d, chipwidth %d" $i $a(name) $a(base) $a(size) $a(bus_width) $a(chip_width)]
- set i [expr $i+1]
- }
+ set i [expr $i+1]
+ }
return $result
}
set n 0
while 1 {
if {$n > [string length $h]} {break}
-
+
set next_a [expr $n+$w]
if {[string length $h]>$n+$w} {
set xxxx [string range $h $n [expr $n+$w]]
set next_a [expr $lastpos+$n+1]
}
}
-
-
+
+
puts [format "%-25s %s" $cmdname [string range $h $n [expr $next_a-1]] ]
set cmdname ""
set n [expr $next_a]
set in_process_reset 0
return -code error "'reset' can not be invoked recursively"
}
-
+
set in_process_reset 1
- set success [expr [catch {ocd_process_reset_inner $MODE} result]==0]
+ set success [expr [catch {ocd_process_reset_inner $MODE} result]==0]
set in_process_reset 0
-
+
if {$success} {
return $result
} else {
# the JTAG tap reset signal might be hooked to a slow
# resistor/capacitor circuit - and it might take a while
# to charge
-
+
# Catch, but ignore any errors.
catch { $t arp_waitstate halted 1000 }
-
+
# Did we succeed?
set s [$t curstate]
-
+
if { 0 != [string compare $s "halted" ] } {
return -error [format "TARGET: %s - Not halted" $t]
}
set err [catch "$t arp_waitstate halted 5000"]
# Did it halt?
if { $err == 0 } {
- $t invoke-event reset-init
+ $t invoke-event reset-init
}
}
}
# A list of names of CPU and options required
set ocd_cpu_list {
{
- name IXP42x
- options {xscale -variant IXP42x}
+ name IXP42x
+ options {xscale -variant IXP42x}
comment {IXP42x cpu}
}
{
- name arm7
- options {arm7tdmi -variant arm7tdmi}
+ name arm7
+ options {arm7tdmi -variant arm7tdmi}
comment {vanilla ARM7}
}
}
global ocd_cpu_list
foreach a [lsort $ocd_cpu_list] {
if {[string length $args]==0||[string first [string toupper $name] [string toupper "$a(name)$a(options)$a(comment)"]]!=-1} {
- lappend result $a
+ lappend result $a
}
}
return $result
catch {
capture {uplevel $a}
} result
- return $result
+ return $result
}
LOG_ERROR("Cannot find jlink Interface! Please check connection and permissions.");
return ERROR_JTAG_INIT_FAILED;
}
-
+
/*
* The next three instructions were added after discovering a problem while using an oscilloscope. For the V8
* SAM-ICE dongle (and likely other j-link device variants), the reset line to the target microprocessor was found to
* following a new USB session. Keeping the processor in reset during the first read collecting version information
* seems to prevent errant "J-Link command EMU_CMD_VERSION failed" issues.
*/
-
+
LOG_INFO("J-Link initialization started / target CPU reset initiated");
jlink_simple_command(EMU_CMD_HW_TRST0);
jlink_simple_command(EMU_CMD_HW_RESET0);
if (result->usb_handle)
{
-
+
/* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS AREA!!!!!!!!!!!
* The behavior of libusb is not completely consistent across Windows, Linux, and Mac OS X platforms. The actions taken
* in the following compiler conditionals may not agree with published documentation for libusb, but were found
A.L = m4_low_nybble(`('$1`) / 2')
Y = A
)')
-
+
m4_define(`m4_delay_loop',
`; delay loop (m4_eval($1) cycles)'
`m4_ifelse(m4_eval(`('$1`) < 6'), 1,
)')
m4_dnl These are utility macros for use with delays. Specifically, there is code below which needs some predictability in code size for relative jumps to reach. The m4_delay macro generates an extra NOP when an even delay is needed, and the m4_delay_loop macro generates an extra NOP when an odd delay is needed. Using this for the argument to the respective macro rounds up the argument so that the extra NOP will not be generated. There is also logic built in to cancel the rounding when the result is small enough that a loop would not be generated.
-
+
m4_define(`m4_delay_loop_round_up', `m4_ifelse(m4_eval($1` < 6'), 1, $1, m4_eval(`(('$1`) + 1) / 2 * 2'))')
m4_define(`m4_delay_round_up', `m4_ifelse(m4_eval($1` < 6'), 1, $1, m4_eval(`(('$1`) / 2 * 2) + 1'))')
A.H = 0xc ; lookup table at 0x1550 + 0xc0 = 0x1610
; branch to address in lookup table
- Y = A
+ Y = A
A = <Y>
BRANCH
; ; Ack buffer 0 in download mode
; A.L = 0x1
; BUFFER_MNGT = A
-;
+;
; STATUS STOP
A = CMP01 ; bits 3..0 contain the number of bytes to shift - 1
A.H = 0
- Y = A ; loop counter
+ Y = A ; loop counter
A = CMP01
EXCHANGE
A = CMP01 ; bits 3..0 contain the number of bytes to shift - 1
A.H = 0
- Y = A ; loop counter
+ Y = A ; loop counter
opcode_shift_tdo_bytes__loop:
SHIFT MPEG PIN0=>IN
JP sub_shift_tdio_bits
opcode_shift_tdio_bytes__sub_return:
-
+
A = CMP10 ; byte loop counter
CP A=>X
CLC
A = CMP01 ; bits 2..0 contain the number of bits to shift - 1
A.H = 0
BCLR 3 ; set TMS=1 if bit 3 was set
- CMP11 = A ; bit loop counter
+ CMP11 = A ; bit loop counter
A.H = opcode_shift_tdio_bits__sub_return
A.L = opcode_shift_tdio_bits__sub_return
DR_CARD = A
JP sub_shift_tdio_bits
opcode_shift_tdio_bits__sub_return:
-
+
A = X
;DR_MPEG = A ; return TCK low, as str912 reset halt seems to require it
BRANCH
m4_delay_loop(m4_delay_loop_round_up(SETUP_DELAY_CYCLES - 1))
BSET 2 ; TCK high
- DR_MPEG = A
+ DR_MPEG = A
- A = DR_MPEG ; set carry bit to TDO
+ A = DR_MPEG ; set carry bit to TDO
CLC
BCLR 0
JP +2
BSET 3 ; bit says whether to return TDO
JP +2
ADR_BUFFER1 -= X ; subroutine returns it, so undo that
-
+
A = X
DR_MPEG = A ; return TCK low, as str912 reset halt seems to require it
BRANCH
A = CMP01 ; bits 3..0 contain the number of bits to shift - 1 (only 1-8 bits is valid... no checking, just improper operation)
A.H = 0
- CMP11 = A ; bit loop counter
+ CMP11 = A ; bit loop counter
A = DATA_BUFFER0 ; get byte from input buffer
ADR_BUFFER0 += X
m4_delay_loop(SETUP_DELAY_CYCLES - 1)
BSET 2 ; TCK high
- DR_MPEG = A
+ DR_MPEG = A
m4_delay(HOLD_DELAY_CYCLES - 10)
log_remove_callback(gdb_log_callback, connection);
gdb_actual_connections--;
- LOG_DEBUG("GDB Close, Target: %s, state: %s, gdb_actual_connections=%d",
+ LOG_DEBUG("GDB Close, Target: %s, state: %s, gdb_actual_connections=%d",
gdb_service->target->cmd_name,
target_state_name(gdb_service->target),
gdb_actual_connections);
avrt.h
nobase_dist_pkglib_DATA =
-nobase_dist_pkglib_DATA += xscale/debug_handler.bin
+nobase_dist_pkglib_DATA += xscale/debug_handler.bin
nobase_dist_pkglib_DATA += ecos/at91eb40a.elf
MAINTAINERCLEANFILES = $(srcdir)/Makefile.in
retval = arm11_simulate_step(target, &next_pc);
if (retval != ERROR_OK)
return retval;
-
+
brp[0].value = next_pc;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
}
{
LOG_ERROR("BUG: no hardware comparator available");
}
- LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
+ LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
breakpoint->unique_id,
breakpoint->address,
breakpoint->set );
LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
return ERROR_FAIL;
}
- LOG_DEBUG("SW BP using hw wp: %d",
+ LOG_DEBUG("SW BP using hw wp: %d",
arm7_9->sw_breakpoints_added );
return jtag_execute_queue();
if (breakpoint->type == BKPT_HARD)
{
- LOG_DEBUG("BPID: %d Releasing hw wp: %d",
+ LOG_DEBUG("BPID: %d Releasing hw wp: %d",
breakpoint->unique_id,
breakpoint->set );
if (breakpoint->set == 1)
{
return retval;
}
-
+
if (buf_get_u32(&access, 0, 1) == 1)
{
break;
}
-
+
/* 10ms timeout */
if ((timeval_ms()-then)>10)
{
{
n++;
if (breakpoint->address == address){
- LOG_DEBUG("Duplicate Breakpoint address: 0x%08" PRIx32 " (BP %d)",
+ LOG_DEBUG("Duplicate Breakpoint address: 0x%08" PRIx32 " (BP %d)",
address, breakpoint->unique_id );
return ERROR_OK;
}
switch (retval)
{
case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
- LOG_INFO("can't add %s breakpoint, resource not available (BPID=%d)",
+ LOG_INFO("can't add %s breakpoint, resource not available (BPID=%d)",
breakpoint_type_strings[(*breakpoint_p)->type],
(*breakpoint_p)->unique_id );
-
+
free((*breakpoint_p)->orig_instr);
free(*breakpoint_p);
*breakpoint_p = NULL;
break;
case ERROR_TARGET_NOT_HALTED:
LOG_INFO("can't add breakpoint while target is running (BPID: %d)",
- (*breakpoint_p)->unique_id );
+ (*breakpoint_p)->unique_id );
free((*breakpoint_p)->orig_instr);
free(*breakpoint_p);
*breakpoint_p = NULL;
switch (retval)
{
case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
- LOG_INFO("can't add %s watchpoint, resource not available (WPID: %d)",
+ LOG_INFO("can't add %s watchpoint, resource not available (WPID: %d)",
watchpoint_rw_strings[(*watchpoint_p)->rw],
(*watchpoint_p)->unique_id );
free (*watchpoint_p);
LOG_DEBUG("added %s watchpoint at 0x%8.8" PRIx32 " of length 0x%8.8x (WPID: %d)",
watchpoint_rw_strings[(*watchpoint_p)->rw],
- (*watchpoint_p)->address,
+ (*watchpoint_p)->address,
(*watchpoint_p)->length,
(*watchpoint_p)->unique_id );
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
- /* Enabling of instruction execution in debug mode is done in debug_entry code */
-
+ /* Enabling of instruction execution in debug mode is done in debug_entry code */
+
return retval;
}
uint32_t didr, ctypr, ttypr, cpuid;
LOG_DEBUG("TODO");
-
+
/* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE;
/* Configure core debug access */
cortex_a8_init_debug_access(target);
-
+
target->type->examined = 1;
return retval;
target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
- LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
+ LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
breakpoint->unique_id,
bp_num, comparator_list[bp_num].bp_value);
}
comparator_list[bp_num].used = 0;
comparator_list[bp_num].bp_value = 0;
target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
-
+
}
else
{
* and exclude both load and store accesses from watchpoint
* condition evaluation
*/
- int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
+ int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
(0xff << EJTAG_DBCn_BLM_SHIFT);
-
+
if (watchpoint->set)
{
LOG_WARNING("watchpoint already set");
target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
-
+
return ERROR_OK;
}
/* get pointers to arch-specific information */
mips32_common_t *mips32 = target->arch_info;
mips32_comparator_t * comparator_list = mips32->data_break_list;
-
+
if (!watchpoint->set)
{
LOG_WARNING("watchpoint not set");
LOG_INFO("no hardware watchpoints available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
mips32->num_data_bpoints_avail--;
mips_m4k_set_watchpoint(target, watchpoint);
address += aligned;
size -= aligned;
}
-
+
/*prevent byte access when possible (avoid AHB access limitations in some cases)*/
if(size >=2)
{
* TARGET_RESET = 3: the target is being held in reset (only a temporary state,
* not sure how this is used with all the recent changes)
* TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
- * behalf of the debugger (e.g. algorithm for flashing)
+ * behalf of the debugger (e.g. algorithm for flashing)
*
* also see: target_state_name();
*/
1:
mrc p14, 0, r15, c14, c0, 0
bvs 1b
- mcr p14, 0, \reg, c8, c0, 0
+ mcr p14, 0, \reg, c8, c0, 0
.endm
@ receive word from debugger
1:
mrc p14, 0, r15, c14, c0, 0
bpl 1b
- mrc p14, 0, \reg, c9, c0, 0
+ mrc p14, 0, \reg, c9, c0, 0
.endm
@ save register on debugger, small
mrc p14, 0, r13, c10, c0
@ check if global enable bit (GE) is set
ands r13, r13, #0x80000000
-
+
bne debug_handler
@ set global enable bit (GE)
cmp r1, #MODE_USR
bne not_user_mode
-
+
@ replace USR mode with SYS
bic r0, r0, #MODE_MASK
orr r0, r0, #MODE_SYS
@ wait for command from debugger, than execute desired function
get_command:
bl receive_from_debugger
-
+
@ 0x0n - register access
cmp r0, #0x0
beq get_banked_registers
@ 0x2n - write memory
cmp r0, #0x21
beq write_byte
-
+
cmp r0, #0x22
beq write_half_word
-
+
cmp r0, #0x24
beq write_word
cmp r0, #0x51
beq invalidate_d_cache
-
+
cmp r0, #0x52
beq invalidate_i_cache
cmp r0, #0x61
beq read_trace_buffer
-
+
cmp r0, #0x62
beq clean_trace_buffer
-
+
@ return (back to get_command)
b get_command
m_receive_from_debugger lr
@ branch back to application code, restoring CPSR
- subs pc, lr, #0
+ subs pc, lr, #0
@ get banked registers
-@ receive mode bits from host, then run into save_banked_registers to
-
+@ receive mode bits from host, then run into save_banked_registers to
+
get_banked_registers:
bl receive_from_debugger
@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
-
+
@ backup banked registers
m_send_to_debugger r8
m_send_to_debugger r9
@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
-
+
beq no_spsr_to_save
@ backup SPSR
@ set banked registers
-@ receive mode bits from host, then run into save_banked_registers to
-
+@ receive mode bits from host, then run into save_banked_registers to
+
set_banked_registers:
bl receive_from_debugger
@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
-
+
@ set banked registers
m_receive_from_debugger r8
m_receive_from_debugger r9
@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
-
+
beq no_spsr_to_restore
@ set SPSR
rb_loop:
ldrb r0, [r2], #1
-
+
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
subs r1, r1, #1
bne rb_loop
-
+
@ return
b get_command
rh_loop:
ldrh r0, [r2], #2
-
+
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
subs r1, r1, #1
bne rh_loop
-
+
@ return
b get_command
rw_loop:
ldr r0, [r2], #4
-
+
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
subs r1, r1, #1
bne rw_loop
-
+
@ return
b get_command
subs r1, r1, #1
bne wb_loop
-
+
@ return
b get_command
subs r1, r1, #1
bne wh_loop
-
+
@ return
b get_command
subs r1, r1, #1
bne ww_loop
-
+
@ return
b get_command
clear_sa:
@ read DCSR
mrc p14, 0, r0, c10, c0
-
+
@ clear SA bit
bic r0, r0, #0x20
clean_d_cache:
@ r0: cache clean area
bl receive_from_debugger
-
+
mov r1, #1024
clean_loop:
mcr p15, 0, r0, c7, c2, 5
b read_cp_reg_reply
read_cp_reg_reply:
- bl send_to_debugger
+ bl send_to_debugger
@ return
b get_command
@ dump checkpoint register 0
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
bl send_to_debugger
-
+
@ dump checkpoint register 1
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
bl send_to_debugger
@ return
b get_command
-
+
@ ----
clean_trace_buffer:
@ return
b get_command
-
+
@ ----
mcr p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
@ branch back to application code, restoring CPSR
- subs pc, lr, #0
+ subs pc, lr, #0
undef_handler:
swi_handler:
ENTRY(reset_handler)
/* specify the mini-ICache memory areas */
-MEMORY
+MEMORY
{
mini_icache_0 (x) : ORIGIN = 0x0, LENGTH = 1024 /* first part of mini icache (sets 0-31) */
mini_icache_1 (x) : ORIGIN = 0x400, LENGTH = 1024 /* second part of mini icache (sets 0-31) */
}
/* now define the output sections */
-SECTIONS
+SECTIONS
{
.part1 :
{
Code Review / openocd.git / commitdiff