Change-Id: I0c15acc1278d2972269d294078495e6b069c830b
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/969
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
{
int i;
struct armv7m_common *armv7m = target_to_armv7m(target);
{
int i;
struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct reg_cache *cache = armv7m->arm.core_cache;
armv7m->pre_restore_context(target);
for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
armv7m->pre_restore_context(target);
for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
- if (armv7m->arm.core_cache->reg_list[i].dirty)
- armv7m->write_core_reg(target, i);
+ if (cache->reg_list[i].dirty) {
+ uint32_t value = buf_get_u32(cache->reg_list[i].value, 0, 32);
+ armv7m->arm.write_core_reg(target, &cache->reg_list[i], i, ARM_MODE_ANY, value);
+ }
int retval;
struct arm_reg *armv7m_reg = reg->arch_info;
struct target *target = armv7m_reg->target;
int retval;
struct arm_reg *armv7m_reg = reg->arch_info;
struct target *target = armv7m_reg->target;
- struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct arm *arm = target_to_arm(target);
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- retval = armv7m->read_core_reg(target, armv7m_reg->num);
+ retval = arm->read_core_reg(target, reg, armv7m_reg->num, arm->core_mode);
-static int armv7m_read_core_reg(struct target *target, unsigned num)
+static int armv7m_read_core_reg(struct target *target, struct reg *r,
+ int num, enum arm_mode mode)
{
uint32_t reg_value;
int retval;
struct arm_reg *armv7m_core_reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
{
uint32_t reg_value;
int retval;
struct arm_reg *armv7m_core_reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
- if (num >= ARMV7M_NUM_REGS)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ assert(num < (int)armv7m->arm.core_cache->num_regs);
armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
retval = armv7m->load_core_reg_u32(target,
armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
retval = armv7m->load_core_reg_u32(target,
- armv7m_core_reg->num,
- ®_value);
+ armv7m_core_reg->num, ®_value);
+
buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
armv7m->arm.core_cache->reg_list[num].valid = 1;
armv7m->arm.core_cache->reg_list[num].dirty = 0;
buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
armv7m->arm.core_cache->reg_list[num].valid = 1;
armv7m->arm.core_cache->reg_list[num].dirty = 0;
-static int armv7m_write_core_reg(struct target *target, unsigned num)
+static int armv7m_write_core_reg(struct target *target, struct reg *r,
+ int num, enum arm_mode mode, uint32_t value)
{
int retval;
uint32_t reg_value;
struct arm_reg *armv7m_core_reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
{
int retval;
uint32_t reg_value;
struct arm_reg *armv7m_core_reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
- if (num >= ARMV7M_NUM_REGS)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ assert(num < (int)armv7m->arm.core_cache->num_regs);
reg_value = buf_get_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32);
armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
reg_value = buf_get_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32);
armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
armv7m->arm.core_cache->reg_list[num].dirty = armv7m->arm.core_cache->reg_list[num].valid;
return ERROR_JTAG_DEVICE_ERROR;
}
armv7m->arm.core_cache->reg_list[num].dirty = armv7m->arm.core_cache->reg_list[num].valid;
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
armv7m->arm.core_cache->reg_list[num].valid = 1;
armv7m->arm.core_cache->reg_list[num].dirty = 0;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
armv7m->arm.core_cache->reg_list[num].valid = 1;
armv7m->arm.core_cache->reg_list[num].dirty = 0;
/* refresh core register cache
* Not needed if core register cache is always consistent with target process state */
for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) {
/* refresh core register cache
* Not needed if core register cache is always consistent with target process state */
for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) {
- if (!armv7m->arm.core_cache->reg_list[i].valid)
- armv7m->read_core_reg(target, i);
armv7m_algorithm_info->context[i] = buf_get_u32(
armv7m->arm.core_cache->reg_list[i].value,
0,
armv7m_algorithm_info->context[i] = buf_get_u32(
armv7m->arm.core_cache->reg_list[i].value,
0,
arm->arch_info = armv7m;
arm->setup_semihosting = armv7m_setup_semihosting;
arm->arch_info = armv7m;
arm->setup_semihosting = armv7m_setup_semihosting;
- /* FIXME remove v7m-specific r/w core_reg functions;
- * use the generic ARM core support..
- */
- armv7m->read_core_reg = armv7m_read_core_reg;
- armv7m->write_core_reg = armv7m_write_core_reg;
+ arm->read_core_reg = armv7m_read_core_reg;
+ arm->write_core_reg = armv7m_write_core_reg;
return arm_init_arch_info(target, arm);
}
return arm_init_arch_info(target, arm);
}
int (*load_core_reg_u32)(struct target *target, uint32_t num, uint32_t *value);
int (*store_core_reg_u32)(struct target *target, uint32_t num, uint32_t value);
int (*load_core_reg_u32)(struct target *target, uint32_t num, uint32_t *value);
int (*store_core_reg_u32)(struct target *target, uint32_t num, uint32_t value);
- /* register cache to processor synchronization */
- int (*read_core_reg)(struct target *target, unsigned num);
- int (*write_core_reg)(struct target *target, unsigned num);
-
int (*examine_debug_reason)(struct target *target);
int (*post_debug_entry)(struct target *target);
int (*examine_debug_reason)(struct target *target);
int (*post_debug_entry)(struct target *target);
int num_regs = arm->core_cache->num_regs;
for (i = 0; i < num_regs; i++) {
int num_regs = arm->core_cache->num_regs;
for (i = 0; i < num_regs; i++) {
- if (!armv7m->arm.core_cache->reg_list[i].valid)
- armv7m->read_core_reg(target, i);
+ r = &armv7m->arm.core_cache->reg_list[i];
+ if (!r->valid)
+ arm->read_core_reg(target, r, i, ARM_MODE_ANY);
}
r = arm->core_cache->reg_list + ARMV7M_xPSR;
}
r = arm->core_cache->reg_list + ARMV7M_xPSR;
int num_regs = armv7m->arm.core_cache->num_regs;
for (int i = 0; i < num_regs; i++) {
int num_regs = armv7m->arm.core_cache->num_regs;
for (int i = 0; i < num_regs; i++) {
- if (!armv7m->arm.core_cache->reg_list[i].valid)
- armv7m->read_core_reg(target, i);
+
+ struct reg *r = &armv7m->arm.core_cache->reg_list[i];
+ if (!r->valid)
+ armv7m->arm.read_core_reg(target, r, i, ARM_MODE_ANY);
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