gitignore: Add GNU Global tag files 41/6541/3 master
authorYasushi SHOJI <yashi@spacecubics.com>
Sun, 5 Sep 2021 12:59:57 +0000 (21:59 +0900)
committerAntonio Borneo <borneo.antonio@gmail.com>
Sat, 2 Oct 2021 13:18:34 +0000 (13:18 +0000)
This commit adds GNU Global[1] tag files to .gitignore.

[1]: https://www.gnu.org/software/global/

Change-Id: Ia09fb359cfdfeadd9538cf6352d353e6475e85c7
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6541
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
53 files changed:
.gitignore
Makefile.am
contrib/60-openocd.rules
doc/openocd.texi
src/flash/nor/at91sam4l.c
src/flash/nor/at91samd.c
src/flash/nor/atsame5.c
src/flash/nor/bluenrg-x.c
src/flash/nor/cc3220sf.c
src/flash/nor/kinetis.c
src/flash/nor/kinetis_ke.c
src/flash/nor/max32xxx.c
src/flash/nor/nrf5.c
src/flash/nor/psoc6.c
src/flash/nor/sim3x.c
src/flash/nor/stellaris.c
src/flash/nor/stm32l4x.c
src/flash/nor/stmqspi.c
src/helper/command.h
src/helper/jim-nvp.c
src/jtag/drivers/libusb_helper.c
src/jtag/drivers/linuxgpiod.c
src/jtag/drivers/remote_bitbang.c
src/jtag/drivers/stlink_usb.c
src/rtos/rtos.c
src/rtos/rtos.h
src/rtos/rtos_riot_stackings.c
src/rtos/rtos_standard_stackings.c
src/rtos/rtos_standard_stackings.h
src/rtos/zephyr.c
src/server/server.c
src/target/Makefile.am
src/target/aarch64.c
src/target/arm_adi_v5.c
src/target/arm_adi_v5.h
src/target/arm_coresight.h [new file with mode: 0644]
src/target/arm_cti.c
src/target/arm_dap.c
src/target/arm_tpiu_swo.c
src/target/armv7m.c
src/target/armv7m.h
src/target/armv7m_trace.h
src/target/cortex_a.c
src/target/cortex_m.c
src/target/hla_target.c
src/target/mips64_pracc.c
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv_semihosting.c
src/target/target.c
src/target/target_type.h
tcl/target/stm32wlx.cfg

index e25d1ba96dfe200af840e848e8b81b1d33e7e730..955ca3c2e0acc8dc7faa08d37267999d943649f7 100644 (file)
@@ -95,3 +95,8 @@ TAGS
 
 # ctags tag files
 tags
+
+# GNU Global tag files
+GPATH
+GRTAGS
+GTAGS
index 3858093b66f43009e3432ddf6d88f271fcdfd5ed..7e5e22973768324ffbc239b5b7988f3ea0209fa4 100644 (file)
@@ -36,7 +36,6 @@ AM_CFLAGS = $(GCC_WARNINGS)
 AM_CPPFLAGS = $(HOST_CPPFLAGS)\
                          -I$(top_srcdir)/src \
                          -I$(top_builddir)/src \
-                         -I$(top_srcdir)/src/helper \
                          -DPKGDATADIR=\"$(pkgdatadir)\" \
                          -DBINDIR=\"$(bindir)\"
 
index 94573a83a69123114e58d92151a832f1706546b1..4ecb485b1ebff2b0cbb207b153fd874cfd6c6114 100644 (file)
@@ -68,6 +68,9 @@ ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c141", MODE="660", GROUP="plugdev",
 # Amontec JTAGkey and JTAGkey-tiny
 ATTRS{idVendor}=="0403", ATTRS{idProduct}=="cff8", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
+# ASIX Presto programmer
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="f1a0", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
 # Nuvoton NuLink
 ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511b", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511c", MODE="660", GROUP="plugdev", TAG+="uaccess"
index 8572ce4a7f628572bc35cb4cef10a371dd567634..7bf0fe98b97e548ff26f7292870daabf5827deb7 100644 (file)
@@ -3131,6 +3131,26 @@ Specifies the serial number of the adapter.
 @deffn {Config Command} {st-link vid_pid} [vid pid]+
 Pairs of vendor IDs and product IDs of the device.
 @end deffn
+
+@deffn {Command} {st-link cmd} rx_n (tx_byte)+
+Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
+and receives @var{rx_n} bytes.
+
+For example, the command to read the target's supply voltage is one byte 0xf7 followed
+by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
+of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
+the target's supply voltage.
+@example
+> st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
+@end example
+The result can be converted to Volts (ignoring the most significant bytes, always zero)
+@example
+> set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
+> echo [expr 2*1.2*([lindex $a 4]+256*[lindex $a 5])/([lindex $a 0]+256*[lindex $a 1])]
+3.24891518738
+@end example
+@end deffn
 @end deffn
 
 @deffn {Interface Driver} {opendous}
@@ -7359,13 +7379,6 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
 @end deffn
 
-@deffn Command {stm32l4x flashloader} num [@option{enable} | @option{disable}]
-Enables or disables the flashloader usage (enabled by default),
-when disabled it will fall back to direct memory access to program the Flash or OTP memories.
-if neither @option{enabled} nor @option{disable} are specified, the command will display
-the current configuration.
-@end deffn
-
 @deffn {Command} {stm32l4x mass_erase} num
 Mass erases the entire stm32l4x device.
 The @var{num} parameter is a value shown by @command{flash banks}.
index f8c6f6490644c384cc2375ff9427116a952230d3..77dc07f7c6d5a2598f623353df29587e96c40a14 100644 (file)
@@ -22,6 +22,7 @@
 
 #include "imp.h"
 
+#include <jtag/jtag.h>
 #include <target/cortex_m.h>
 
 /* At this time, the SAM4L Flash is available in these capacities:
index d4ac4c9981565749d03d9a937dd842d486086414..5cefd1766e57eb571dc4c111d63d4a5c4fb0ad28 100644 (file)
@@ -23,6 +23,7 @@
 #include "imp.h"
 #include "helper/binarybuffer.h"
 
+#include <jtag/jtag.h>
 #include <target/cortex_m.h>
 
 #define SAMD_NUM_PROT_BLOCKS   16
index 203c470cab1b85593fb035d2f957725e96ebcd2a..9ab0e811303cea2b9d3e29ecc4b003cfd01c8ba2 100644 (file)
@@ -28,6 +28,7 @@
 #include "helper/binarybuffer.h"
 
 #include <helper/time_support.h>
+#include <jtag/jtag.h>
 #include <target/cortex_m.h>
 
 /* A note to prefixing.
index a686e83d3920ba40f4e3fa2f0fda5a0428ddbe3c..60eccefaf04baeb3326d508919b2fe2d7426b385 100644 (file)
@@ -20,6 +20,7 @@
 #include "config.h"
 #endif
 
+#include <helper/binarybuffer.h>
 #include "helper/types.h"
 #include <target/algorithm.h>
 #include <target/armv7m.h>
index b296538414f8cd6a3caaef1d6414f309387f7877..723e605c706567d32362ed3ab5f07bfc0b4e96c0 100644 (file)
@@ -21,6 +21,7 @@
 
 #include "imp.h"
 #include "cc3220sf.h"
+#include <helper/binarybuffer.h>
 #include <helper/time_support.h>
 #include <target/algorithm.h>
 #include <target/armv7m.h>
index 3aa4c6bb529059654137e8e550da7004c6c05897..edb4eb58fedddc8fac483a0d33e9769745eecf04 100644 (file)
@@ -38,6 +38,7 @@
 #include <helper/time_support.h>
 #include <target/target_type.h>
 #include <target/algorithm.h>
+#include <target/arm_adi_v5.h>
 #include <target/armv7m.h>
 #include <target/cortex_m.h>
 
index 513b072dde068692bbb7a02ff8166f52c6bf3ac2..dc3b37ecb1c9f9de96b6606ca02039b3a4e10877 100644 (file)
@@ -41,6 +41,7 @@
 #include "imp.h"
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
+#include <target/arm_adi_v5.h>
 #include <target/armv7m.h>
 #include <target/cortex_m.h>
 
index d11af909463b48b60182bcc802c8b587403d2544..e7a690d3a58922dceaa4d8d24160ac398b4ddaec 100644 (file)
@@ -21,6 +21,7 @@
 #endif
 
 #include "imp.h"
+#include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 #include <target/armv7m.h>
 
index 8870164d286a2fcd62ac9465abae3bbc66ea51d5..c96415547b5c1c171c1cf6a19d167baf7a1e5684 100644 (file)
@@ -23,6 +23,7 @@
 #endif
 
 #include "imp.h"
+#include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 #include <target/armv7m.h>
 #include <helper/types.h>
index b8b520237e61def82a22d2449e686e3b9f3b120f..8a4121950d0ac47fdeefe160fff3e4c7077df5d4 100644 (file)
 #include <time.h>
 
 #include "imp.h"
+#include "helper/time_support.h"
+#include "target/arm_adi_v5.h"
 #include "target/target.h"
 #include "target/cortex_m.h"
 #include "target/breakpoints.h"
 #include "target/target_type.h"
-#include "time_support.h"
 #include "target/algorithm.h"
 
 /**************************************************************************************************
index 20b5e397282f8726a9c7df251684ea7148fede69..2938ed1ab4e2a21937031218852f19bf148f612f 100644 (file)
@@ -27,6 +27,7 @@
 #include <helper/binarybuffer.h>
 #include <helper/time_support.h>
 #include <target/algorithm.h>
+#include <target/arm_adi_v5.h>
 #include <target/cortex_m.h>
 
 /* SI32_DEVICEID0 */
index d2638c152dd9e5672314d7c7c24e8cf7d65b0f3e..6135c957452bbaea22efde3abc961145f95c0365 100644 (file)
@@ -30,6 +30,7 @@
 #include "jtag/interface.h"
 #include "imp.h"
 #include <target/algorithm.h>
+#include <target/arm_adi_v5.h>
 #include <target/armv7m.h>
 
 #define DID0_VER(did0) ((did0 >> 28)&0x07)
index 8c292e76d5be7318aefbfef880433dc7b1a70c2f..e5100a0159bcba06b3e9053db54231c32ccc08db 100644 (file)
 #include "imp.h"
 #include <helper/align.h>
 #include <helper/binarybuffer.h>
+#include <helper/bits.h>
 #include <target/algorithm.h>
+#include <target/arm_adi_v5.h>
 #include <target/cortex_m.h>
-#include "bits.h"
 #include "stm32l4x.h"
 
 /* STM32L4xxx series for reference.
@@ -252,7 +253,6 @@ struct stm32l4_flash_bank {
        uint32_t flash_regs_base;
        const uint32_t *flash_regs;
        bool otp_enabled;
-       bool use_flashloader;
        enum stm32l4_rdp rdp;
        bool tzen;
        uint32_t optr;
@@ -619,7 +619,6 @@ FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
        stm32l4_info->probed = false;
        stm32l4_info->otp_enabled = false;
        stm32l4_info->user_bank_size = bank->size;
-       stm32l4_info->use_flashloader = true;
 
        return ERROR_OK;
 }
@@ -1595,20 +1594,21 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
        if (retval != ERROR_OK)
                goto err_lock;
 
-       if (stm32l4_info->use_flashloader) {
-               /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
-                * the debug is possible only in non-secure state.
-                * Thus means the flashloader will run in non-secure mode,
-                * and the workarea need to be in non-secure RAM */
-               if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
-                       LOG_INFO("RDP level is 0.5, the work-area should reside in non-secure RAM");
 
-               retval = stm32l4_write_block(bank, buffer, offset,
-                               count / stm32l4_info->data_width);
-       }
+       /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
+        * the debug is possible only in non-secure state.
+        * Thus means the flashloader will run in non-secure mode,
+        * and the workarea need to be in non-secure RAM */
+       if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
+               LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
+
+       /* first try to write using the loader, for better performance */
+       retval = stm32l4_write_block(bank, buffer, offset,
+                       count / stm32l4_info->data_width);
 
-       if (!stm32l4_info->use_flashloader || retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
-               LOG_INFO("falling back to single memory accesses");
+       /* if resources are not available write without a loader */
+       if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+               LOG_WARNING("falling back to programming without a flash loader (slower)");
                retval = stm32l4_write_block_without_loader(bank, buffer, offset,
                                count / stm32l4_info->data_width);
        }
@@ -2266,26 +2266,6 @@ COMMAND_HANDLER(stm32l4_handle_trustzone_command)
        return stm32l4_perform_obl_launch(bank);
 }
 
-COMMAND_HANDLER(stm32l4_handle_flashloader_command)
-{
-       if (CMD_ARGC < 1 || CMD_ARGC > 2)
-               return ERROR_COMMAND_SYNTAX_ERROR;
-
-       struct flash_bank *bank;
-       int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
-       if (retval != ERROR_OK)
-               return retval;
-
-       struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
-
-       if (CMD_ARGC == 2)
-               COMMAND_PARSE_ENABLE(CMD_ARGV[1], stm32l4_info->use_flashloader);
-
-       command_print(CMD, "FlashLoader usage is %s", stm32l4_info->use_flashloader ? "enabled" : "disabled");
-
-       return ERROR_OK;
-}
-
 COMMAND_HANDLER(stm32l4_handle_option_load_command)
 {
        if (CMD_ARGC != 1)
@@ -2491,13 +2471,6 @@ static const struct command_registration stm32l4_exec_command_handlers[] = {
                .usage = "bank_id",
                .help = "Unlock entire protected flash device.",
        },
-       {
-               .name = "flashloader",
-               .handler = stm32l4_handle_flashloader_command,
-               .mode = COMMAND_EXEC,
-               .usage = "<bank_id> [enable|disable]",
-               .help = "Configure the flashloader usage",
-       },
        {
                .name = "mass_erase",
                .handler = stm32l4_handle_mass_erase_command,
index 0abd8449b782d6da5aa31422d919e6aa1ad9954b..8278601db2a104ea25faeea886a3cb4d2dc394d6 100644 (file)
@@ -40,6 +40,7 @@
 #endif
 
 #include "imp.h"
+#include <helper/binarybuffer.h>
 #include <helper/bits.h>
 #include <helper/time_support.h>
 #include <target/algorithm.h>
index f3870198369dc69877655f2bc4fe0be3c5d5a4cc..fb9e50c85e86728ad4b0c7f8512b11d73a103828 100644 (file)
@@ -24,8 +24,8 @@
 
 #include <stdint.h>
 #include <stdbool.h>
-#include <jim-nvp.h>
 
+#include <helper/jim-nvp.h>
 #include <helper/list.h>
 #include <helper/types.h>
 
index e21bc680d8349871c8509ef1a0639ecfee3b80b0..738ed7943ef82163509d6b7f609833625bb2fbe0 100644 (file)
@@ -41,8 +41,8 @@
  * official policies, either expressed or implied, of the Jim Tcl Project.
  */
 
+#include "jim-nvp.h"
 #include <string.h>
-#include <jim-nvp.h>
 
 int jim_get_nvp(Jim_Interp *interp,
        Jim_Obj *objptr, const struct jim_nvp *nvp_table, const struct jim_nvp **result)
index f285bdcac6097846438f25e84d3db035568cbe08..3308d8742c805d1e0ad08b3a45eda54d5bbb1381 100644 (file)
@@ -20,9 +20,9 @@
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
+#include <helper/log.h>
 #include <jtag/drivers/jtag_usb_common.h>
 #include "libusb_helper.h"
-#include "log.h"
 
 /*
  * comment from libusb:
index 42c8a31408d6c9af1b55c3b8407ee580cc314e2c..dd50b44066616b207c745cdc1c43d743cd20e1d1 100644 (file)
@@ -278,7 +278,7 @@ static int linuxgpiod_quit(void)
        return ERROR_OK;
 }
 
-static struct gpiod_line *helper_get_input_line(const char *label, unsigned int offset)
+static struct gpiod_line *helper_get_line(const char *label, unsigned int offset, int val, int dir, int flags)
 {
        struct gpiod_line *line;
        int retval;
@@ -289,33 +289,34 @@ static struct gpiod_line *helper_get_input_line(const char *label, unsigned int
                return NULL;
        }
 
-       retval = gpiod_line_request_input(line, "OpenOCD");
+       struct gpiod_line_request_config config = {
+               .consumer = "OpenOCD",
+               .request_type = dir,
+               .flags = flags,
+       };
+
+       retval = gpiod_line_request(line, &config, val);
        if (retval < 0) {
-               LOG_ERROR("Error request_input line %s", label);
+               LOG_ERROR("Error requesting gpio line %s", label);
                return NULL;
        }
 
        return line;
 }
 
-static struct gpiod_line *helper_get_output_line(const char *label, unsigned int offset, int val)
+static struct gpiod_line *helper_get_input_line(const char *label, unsigned int offset)
 {
-       struct gpiod_line *line;
-       int retval;
-
-       line = gpiod_chip_get_line(gpiod_chip, offset);
-       if (!line) {
-               LOG_ERROR("Error get line %s", label);
-               return NULL;
-       }
+       return helper_get_line(label, offset, 0, GPIOD_LINE_REQUEST_DIRECTION_INPUT, 0);
+}
 
-       retval = gpiod_line_request_output(line, "OpenOCD", val);
-       if (retval < 0) {
-               LOG_ERROR("Error request_output line %s", label);
-               return NULL;
-       }
+static struct gpiod_line *helper_get_output_line(const char *label, unsigned int offset, int val)
+{
+       return helper_get_line(label, offset, val, GPIOD_LINE_REQUEST_DIRECTION_OUTPUT, 0);
+}
 
-       return line;
+static struct gpiod_line *helper_get_open_drain_output_line(const char *label, unsigned int offset, int val)
+{
+       return helper_get_line(label, offset, val, GPIOD_LINE_REQUEST_DIRECTION_OUTPUT, GPIOD_LINE_REQUEST_FLAG_OPEN_DRAIN);
 }
 
 static int linuxgpiod_init(void)
@@ -381,7 +382,11 @@ static int linuxgpiod_init(void)
        }
 
        if (is_gpio_valid(srst_gpio)) {
-               gpiod_srst = helper_get_output_line("srst", srst_gpio, 1);
+               if (jtag_get_reset_config() & RESET_SRST_PUSH_PULL)
+                       gpiod_srst = helper_get_output_line("srst", srst_gpio, 1);
+               else
+                       gpiod_srst = helper_get_open_drain_output_line("srst", srst_gpio, 1);
+
                if (!gpiod_srst)
                        goto out_error;
        }
index ce1a065445c795db5bd9c552834dc01e2ecae29f..6ab7cc9c59a851ef56839a788aa43c8878b5f6fa 100644 (file)
@@ -23,6 +23,7 @@
 #ifndef _WIN32
 #include <sys/un.h>
 #include <netdb.h>
+#include <netinet/tcp.h>
 #endif
 #include "helper/system.h"
 #include "helper/replacements.h"
@@ -40,35 +41,87 @@ static uint8_t remote_bitbang_send_buf[512];
 static unsigned int remote_bitbang_send_buf_used;
 
 /* Circular buffer. When start == end, the buffer is empty. */
-static char remote_bitbang_recv_buf[64];
+static char remote_bitbang_recv_buf[256];
 static unsigned int remote_bitbang_recv_buf_start;
 static unsigned int remote_bitbang_recv_buf_end;
 
-static bool remote_bitbang_buf_full(void)
+static bool remote_bitbang_recv_buf_full(void)
 {
        return remote_bitbang_recv_buf_end ==
                ((remote_bitbang_recv_buf_start + sizeof(remote_bitbang_recv_buf) - 1) %
                 sizeof(remote_bitbang_recv_buf));
 }
 
-/* Read any incoming data, placing it into the buffer. */
-static int remote_bitbang_fill_buf(void)
+static bool remote_bitbang_recv_buf_empty(void)
 {
-       socket_nonblock(remote_bitbang_fd);
-       while (!remote_bitbang_buf_full()) {
-               unsigned int contiguous_available_space;
-               if (remote_bitbang_recv_buf_end >= remote_bitbang_recv_buf_start) {
-                       contiguous_available_space = sizeof(remote_bitbang_recv_buf) -
-                               remote_bitbang_recv_buf_end;
-                       if (remote_bitbang_recv_buf_start == 0)
-                               contiguous_available_space -= 1;
-               } else {
-                       contiguous_available_space = remote_bitbang_recv_buf_start -
-                               remote_bitbang_recv_buf_end - 1;
+       return remote_bitbang_recv_buf_start == remote_bitbang_recv_buf_end;
+}
+
+static unsigned int remote_bitbang_recv_buf_contiguous_available_space(void)
+{
+       if (remote_bitbang_recv_buf_end >= remote_bitbang_recv_buf_start) {
+               unsigned int space = sizeof(remote_bitbang_recv_buf) -
+                                    remote_bitbang_recv_buf_end;
+               if (remote_bitbang_recv_buf_start == 0)
+                       space -= 1;
+               return space;
+       } else {
+               return remote_bitbang_recv_buf_start -
+                      remote_bitbang_recv_buf_end - 1;
+       }
+}
+
+static int remote_bitbang_flush(void)
+{
+       if (remote_bitbang_send_buf_used <= 0)
+               return ERROR_OK;
+
+       unsigned int offset = 0;
+       while (offset < remote_bitbang_send_buf_used) {
+               ssize_t written = write_socket(remote_bitbang_fd, remote_bitbang_send_buf + offset,
+                                                                          remote_bitbang_send_buf_used - offset);
+               if (written < 0) {
+                       log_socket_error("remote_bitbang_putc");
+                       remote_bitbang_send_buf_used = 0;
+                       return ERROR_FAIL;
                }
+               offset += written;
+       }
+       remote_bitbang_send_buf_used = 0;
+       return ERROR_OK;
+}
+
+enum block_bool {
+       NO_BLOCK,
+       BLOCK
+};
+
+/* Read any incoming data, placing it into the buffer. */
+static int remote_bitbang_fill_buf(enum block_bool block)
+{
+       if (remote_bitbang_recv_buf_empty()) {
+               /* If the buffer is empty, reset it to 0 so we get more
+                * contiguous space. */
+               remote_bitbang_recv_buf_start = 0;
+               remote_bitbang_recv_buf_end = 0;
+       }
+
+       if (block == BLOCK) {
+               if (remote_bitbang_flush() != ERROR_OK)
+                       return ERROR_FAIL;
+               socket_block(remote_bitbang_fd);
+       }
+
+       bool first = true;
+       while (!remote_bitbang_recv_buf_full()) {
+               unsigned int contiguous_available_space =
+                               remote_bitbang_recv_buf_contiguous_available_space();
                ssize_t count = read_socket(remote_bitbang_fd,
                                remote_bitbang_recv_buf + remote_bitbang_recv_buf_end,
                                contiguous_available_space);
+               if (first && block == BLOCK)
+                       socket_nonblock(remote_bitbang_fd);
+               first = false;
                if (count > 0) {
                        remote_bitbang_recv_buf_end += count;
                        if (remote_bitbang_recv_buf_end == sizeof(remote_bitbang_recv_buf))
@@ -92,26 +145,6 @@ static int remote_bitbang_fill_buf(void)
        return ERROR_OK;
 }
 
-static int remote_bitbang_flush(void)
-{
-       if (remote_bitbang_send_buf_used <= 0)
-               return ERROR_OK;
-
-       unsigned int offset = 0;
-       while (offset < remote_bitbang_send_buf_used) {
-               ssize_t written = write_socket(remote_bitbang_fd, remote_bitbang_send_buf + offset,
-                                                                          remote_bitbang_send_buf_used - offset);
-               if (written < 0) {
-                       log_socket_error("remote_bitbang_putc");
-                       remote_bitbang_send_buf_used = 0;
-                       return ERROR_FAIL;
-               }
-               offset += written;
-       }
-       remote_bitbang_send_buf_used = 0;
-       return ERROR_OK;
-}
-
 typedef enum {
        NO_FLUSH,
        FLUSH_SEND_BUF
@@ -157,47 +190,25 @@ static bb_value_t char_to_int(int c)
        }
 }
 
-/* Get the next read response. */
-static bb_value_t remote_bitbang_rread(void)
-{
-       if (remote_bitbang_flush() != ERROR_OK)
-               return ERROR_FAIL;
-
-       /* Enable blocking access. */
-       socket_block(remote_bitbang_fd);
-       char c;
-       ssize_t count = read_socket(remote_bitbang_fd, &c, 1);
-       if (count == 1) {
-               return char_to_int(c);
-       } else {
-               remote_bitbang_quit();
-               LOG_ERROR("read_socket: count=%d", (int) count);
-               log_socket_error("read_socket");
-               return BB_ERROR;
-       }
-}
-
 static int remote_bitbang_sample(void)
 {
-       if (remote_bitbang_fill_buf() != ERROR_OK)
+       if (remote_bitbang_fill_buf(NO_BLOCK) != ERROR_OK)
                return ERROR_FAIL;
-       assert(!remote_bitbang_buf_full());
+       assert(!remote_bitbang_recv_buf_full());
        return remote_bitbang_queue('R', NO_FLUSH);
 }
 
 static bb_value_t remote_bitbang_read_sample(void)
 {
-       if (remote_bitbang_recv_buf_start == remote_bitbang_recv_buf_end) {
-               if (remote_bitbang_fill_buf() != ERROR_OK)
-                       return ERROR_FAIL;
-       }
-       if (remote_bitbang_recv_buf_start != remote_bitbang_recv_buf_end) {
-               int c = remote_bitbang_recv_buf[remote_bitbang_recv_buf_start];
-               remote_bitbang_recv_buf_start =
-                       (remote_bitbang_recv_buf_start + 1) % sizeof(remote_bitbang_recv_buf);
-               return char_to_int(c);
+       if (remote_bitbang_recv_buf_empty()) {
+               if (remote_bitbang_fill_buf(BLOCK) != ERROR_OK)
+                       return BB_ERROR;
        }
-       return remote_bitbang_rread();
+       assert(!remote_bitbang_recv_buf_empty());
+       int c = remote_bitbang_recv_buf[remote_bitbang_recv_buf_start];
+       remote_bitbang_recv_buf_start =
+               (remote_bitbang_recv_buf_start + 1) % sizeof(remote_bitbang_recv_buf);
+       return char_to_int(c);
 }
 
 static int remote_bitbang_write(int tck, int tms, int tdi)
@@ -261,6 +272,13 @@ static int remote_bitbang_init_tcp(void)
                close(fd);
        }
 
+       /* We work hard to collapse the writes into the minimum number, so when
+        * we write something we want to get it to the other end of the
+        * connection as fast as possible. */
+       int one = 1;
+       /* On Windows optval has to be a const char *. */
+       setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (const char *)&one, sizeof(one));
+
        freeaddrinfo(result); /* No longer needed */
 
        if (!rp) { /* No address succeeded */
@@ -314,6 +332,8 @@ static int remote_bitbang_init(void)
        if (remote_bitbang_fd < 0)
                return remote_bitbang_fd;
 
+       socket_nonblock(remote_bitbang_fd);
+
        LOG_INFO("remote_bitbang driver initialized");
        return ERROR_OK;
 }
index e8e2472eeeabf7559e2329ef2837d20b665a63f3..a523708638654a27318612d670f3c25f43cb61cd 100644 (file)
@@ -41,6 +41,7 @@
 #include <jtag/hla/hla_transport.h>
 #include <jtag/hla/hla_interface.h>
 #include <jtag/swim.h>
+#include <target/arm_adi_v5.h>
 #include <target/target.h>
 #include <transport/transport.h>
 
@@ -4221,6 +4222,43 @@ COMMAND_HANDLER(stlink_dap_backend_command)
        return ERROR_OK;
 }
 
+#define BYTES_PER_LINE 16
+COMMAND_HANDLER(stlink_dap_cmd_command)
+{
+       unsigned int rx_n, tx_n;
+       struct stlink_usb_handle_s *h = stlink_dap_handle;
+
+       if (CMD_ARGC < 2)
+               return ERROR_COMMAND_SYNTAX_ERROR;
+
+       COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], rx_n);
+       tx_n = CMD_ARGC - 1;
+       if (tx_n > STLINK_SG_SIZE || rx_n > STLINK_DATA_SIZE) {
+               LOG_ERROR("max %x byte sent and %d received", STLINK_SG_SIZE, STLINK_DATA_SIZE);
+               return ERROR_COMMAND_SYNTAX_ERROR;
+       }
+
+       stlink_usb_init_buffer(h, h->rx_ep, rx_n);
+
+       for (unsigned int i = 0; i < tx_n; i++) {
+               uint8_t byte;
+               COMMAND_PARSE_NUMBER(u8, CMD_ARGV[i + 1], byte);
+               h->cmdbuf[h->cmdidx++] = byte;
+       }
+
+       int retval = stlink_usb_xfer_noerrcheck(h, h->databuf, rx_n);
+       if (retval != ERROR_OK) {
+               LOG_ERROR("Error %d", retval);
+               return retval;
+       }
+
+       for (unsigned int i = 0; i < rx_n; i++)
+               command_print_sameline(CMD, "0x%02x%c", h->databuf[i],
+                       ((i == (rx_n - 1)) || ((i % BYTES_PER_LINE) == (BYTES_PER_LINE - 1))) ? '\n' : ' ');
+
+       return ERROR_OK;
+}
+
 /** */
 static const struct command_registration stlink_dap_subcommand_handlers[] = {
        {
@@ -4244,6 +4282,13 @@ static const struct command_registration stlink_dap_subcommand_handlers[] = {
                .help = "select which ST-Link backend to use",
                .usage = "usb | tcp [port]",
        },
+       {
+               .name = "cmd",
+               .handler = stlink_dap_cmd_command,
+               .mode = COMMAND_EXEC,
+               .help = "send arbitrary command",
+               .usage = "rx_n (tx_byte)+",
+       },
        COMMAND_REGISTRATION_DONE
 };
 
index eaad5e50c9fd3432d305b32d8eb2ff0f3db1fc9c..f401c3d30bdacfe7b07b6c1d5f6324b35ff64c6c 100644 (file)
@@ -616,7 +616,7 @@ int rtos_generic_stack_read(struct target *target,
                LOG_OUTPUT("\r\n");
 #endif
 
-       int64_t new_stack_ptr;
+       target_addr_t new_stack_ptr;
        if (stacking->calculate_process_stack) {
                new_stack_ptr = stacking->calculate_process_stack(target,
                                stack_data, stacking, stack_ptr);
index 81751fe0a80ea2200478a4da7f085c82b522f237..8309de4028272bd6746b6c5def735cb07f9d9daa 100644 (file)
@@ -21,7 +21,7 @@
 
 #include "server/server.h"
 #include "target/target.h"
-#include <jim-nvp.h>
+#include <helper/jim-nvp.h>
 
 typedef int64_t threadid_t;
 typedef int64_t symbol_address_t;
@@ -108,10 +108,10 @@ struct rtos_register_stacking {
         * just use stacking->stack_registers_size * stack_growth_direction
         * to calculate adjustment.
         */
-       int64_t (*calculate_process_stack)(struct target *target,
+       target_addr_t (*calculate_process_stack)(struct target *target,
                const uint8_t *stack_data,
                const struct rtos_register_stacking *stacking,
-               int64_t stack_ptr);
+               target_addr_t stack_ptr);
        const struct stack_register_offset *register_offsets;
 };
 
index 98e02edfcbdfbc0354cd960d3a4a50eae8829f63..abf08c8ff4f889e53de633420b896655fd89a834 100644 (file)
@@ -27,9 +27,9 @@
 /* This works for the M0 and M34 stackings as xPSR is in a fixed
  * location
  */
-static int64_t rtos_riot_cortex_m_stack_align(struct target *target,
+static target_addr_t rtos_riot_cortex_m_stack_align(struct target *target,
        const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
-       int64_t stack_ptr)
+       target_addr_t stack_ptr)
 {
        const int XPSR_OFFSET = 0x40;
        return rtos_cortex_m_stack_align(target, stack_data, stacking,
index 90c642a0070e95ed50e5752b4dbf256bf9696735..c3eef5c068e11ed19fdfc08316655c78f027bfb3 100644 (file)
@@ -152,29 +152,29 @@ static const struct stack_register_offset rtos_standard_nds32_n1068_stack_offset
        { 35, 0x10, 32 },               /* IFC_LP */
 };
 
-static int64_t rtos_generic_stack_align(struct target *target,
+static target_addr_t rtos_generic_stack_align(struct target *target,
        const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
-       int64_t stack_ptr, int align)
+       target_addr_t stack_ptr, int align)
 {
-       int64_t new_stack_ptr;
-       int64_t aligned_stack_ptr;
+       target_addr_t new_stack_ptr;
+       target_addr_t aligned_stack_ptr;
        new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
                stacking->stack_registers_size;
-       aligned_stack_ptr = new_stack_ptr & ~((int64_t)align - 1);
+       aligned_stack_ptr = new_stack_ptr & ~((target_addr_t)align - 1);
        if (aligned_stack_ptr != new_stack_ptr &&
                stacking->stack_growth_direction == -1) {
                /* If we have a downward growing stack, the simple alignment code
                 * above results in a wrong result (since it rounds down to nearest
                 * alignment).  We want to round up so add an extra align.
                 */
-               aligned_stack_ptr += (int64_t)align;
+               aligned_stack_ptr += (target_addr_t)align;
        }
        return aligned_stack_ptr;
 }
 
-int64_t rtos_generic_stack_align8(struct target *target,
+target_addr_t rtos_generic_stack_align8(struct target *target,
        const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
-       int64_t stack_ptr)
+       target_addr_t stack_ptr)
 {
        return rtos_generic_stack_align(target, stack_data,
                        stacking, stack_ptr, 8);
@@ -199,13 +199,13 @@ int64_t rtos_generic_stack_align8(struct target *target,
  * This is just a helper function for use in the calculate_process_stack
  * function for a given architecture/rtos.
  */
-int64_t rtos_cortex_m_stack_align(struct target *target,
+target_addr_t rtos_cortex_m_stack_align(struct target *target,
        const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
-       int64_t stack_ptr, size_t xpsr_offset)
+       target_addr_t stack_ptr, size_t xpsr_offset)
 {
        const uint32_t ALIGN_NEEDED = (1 << 9);
        uint32_t xpsr;
-       int64_t new_stack_ptr;
+       target_addr_t new_stack_ptr;
 
        new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
                stacking->stack_registers_size;
@@ -220,27 +220,27 @@ int64_t rtos_cortex_m_stack_align(struct target *target,
        return new_stack_ptr;
 }
 
-static int64_t rtos_standard_cortex_m3_stack_align(struct target *target,
+static target_addr_t rtos_standard_cortex_m3_stack_align(struct target *target,
        const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
-       int64_t stack_ptr)
+       target_addr_t stack_ptr)
 {
        const int XPSR_OFFSET = 0x3c;
        return rtos_cortex_m_stack_align(target, stack_data, stacking,
                stack_ptr, XPSR_OFFSET);
 }
 
-static int64_t rtos_standard_cortex_m4f_stack_align(struct target *target,
+static target_addr_t rtos_standard_cortex_m4f_stack_align(struct target *target,
        const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
-       int64_t stack_ptr)
+       target_addr_t stack_ptr)
 {
        const int XPSR_OFFSET = 0x40;
        return rtos_cortex_m_stack_align(target, stack_data, stacking,
                stack_ptr, XPSR_OFFSET);
 }
 
-static int64_t rtos_standard_cortex_m4f_fpu_stack_align(struct target *target,
+static target_addr_t rtos_standard_cortex_m4f_fpu_stack_align(struct target *target,
        const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
-       int64_t stack_ptr)
+       target_addr_t stack_ptr)
 {
        const int XPSR_OFFSET = 0x80;
        return rtos_cortex_m_stack_align(target, stack_data, stacking,
index ad319d2a086aaf1971c95a4da4987519a4db3a1c..d18f1797c68e54c124deb6b18bde207cd33fb04f 100644 (file)
@@ -30,11 +30,11 @@ extern const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking;
 extern const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking;
 extern const struct rtos_register_stacking rtos_standard_cortex_r4_stacking;
 extern const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking;
-int64_t rtos_generic_stack_align8(struct target *target,
+target_addr_t rtos_generic_stack_align8(struct target *target,
        const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
-       int64_t stack_ptr);
-int64_t rtos_cortex_m_stack_align(struct target *target,
+       target_addr_t stack_ptr);
+target_addr_t rtos_cortex_m_stack_align(struct target *target,
        const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
-       int64_t stack_ptr, size_t xpsr_offset);
+       target_addr_t stack_ptr, size_t xpsr_offset);
 
 #endif /* OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H */
index a5967355706e90764ab68ca02129cf2486749d55..630511636babb41ee6137e2e8c1005f7213093c6 100644 (file)
@@ -189,9 +189,9 @@ enum zephyr_symbol_values {
        ZEPHYR_VAL_COUNT
 };
 
-static int64_t zephyr_cortex_m_stack_align(struct target *target,
+static target_addr_t zephyr_cortex_m_stack_align(struct target *target,
                const uint8_t *stack_data,
-               const struct rtos_register_stacking *stacking, int64_t stack_ptr)
+               const struct rtos_register_stacking *stacking, target_addr_t stack_ptr)
 {
        return rtos_cortex_m_stack_align(target, stack_data, stacking,
                        stack_ptr, ARM_XPSR_OFFSET);
index 64acd36894ab666f82c1667cf32a7d07baa213d0..3f579bfc641a79bf02477d03389b34360d7674ad 100644 (file)
 #endif
 
 #include "server.h"
+#include <helper/time_support.h>
 #include <target/target.h>
 #include <target/target_request.h>
 #include <target/openrisc/jsp_server.h>
 #include "openocd.h"
 #include "tcl_server.h"
 #include "telnet_server.h"
-#include "time_support.h"
 
 #include <signal.h>
 
index 34a78517aa6539a240249b181a160c1d110343e1..49e882fe6c6a5e2c062525eb4fb75e0356b5796a 100644 (file)
@@ -165,6 +165,7 @@ ARC_SRC = \
 %C%_libtarget_la_SOURCES += \
        %D%/algorithm.h \
        %D%/arm.h \
+       %D%/arm_coresight.h \
        %D%/arm_dpm.h \
        %D%/arm_jtag.h \
        %D%/arm_adi_v5.h \
index 70e727cf9d42334a2d304ceeba4607446ca800f5..fc6bd6b3012dd24d2de0942c9901a4e6e611cca9 100644 (file)
@@ -29,6 +29,7 @@
 #include "target_type.h"
 #include "armv8_opcodes.h"
 #include "armv8_cache.h"
+#include "arm_coresight.h"
 #include "arm_semihosting.h"
 #include "jtag/interface.h"
 #include "smp.h"
@@ -2578,8 +2579,8 @@ static int aarch64_examine_first(struct target *target)
                retval = dap_get_debugbase(armv8->debug_ap, &dbgbase, &apid);
                if (retval != ERROR_OK)
                        return retval;
-               /* Lookup 0x15 -- Processor DAP */
-               retval = dap_lookup_cs_component(armv8->debug_ap, dbgbase, 0x15,
+               /* Lookup Processor DAP */
+               retval = dap_lookup_cs_component(armv8->debug_ap, dbgbase, ARM_CS_C9_DEVTYPE_CORE_DEBUG,
                                &armv8->debug_base, &coreidx);
                if (retval != ERROR_OK)
                        return retval;
index c29554239b9d6cbbb2eeae05b358ea0b677eec75..8d6d6618bca1c689c574dcec2d45d0ba7397ac37 100644 (file)
 #include "jtag/interface.h"
 #include "arm.h"
 #include "arm_adi_v5.h"
+#include "arm_coresight.h"
 #include "jtag/swd.h"
 #include "transport/transport.h"
+#include <helper/align.h>
 #include <helper/jep106.h>
 #include <helper/time_support.h>
 #include <helper/list.h>
@@ -891,9 +893,28 @@ static const char *class_description[16] = {
        [0xF] = "CoreLink, PrimeCell or System component",
 };
 
-static bool is_dap_cid_ok(uint32_t cid)
+static const struct {
+       enum ap_type type;
+       const char *description;
+} ap_types[] = {
+       { AP_TYPE_JTAG_AP,  "JTAG-AP" },
+       { AP_TYPE_COM_AP,   "COM-AP" },
+       { AP_TYPE_AHB3_AP,  "MEM-AP AHB3" },
+       { AP_TYPE_APB_AP,   "MEM-AP APB2 or APB3" },
+       { AP_TYPE_AXI_AP,   "MEM-AP AXI3 or AXI4" },
+       { AP_TYPE_AHB5_AP,  "MEM-AP AHB5" },
+       { AP_TYPE_APB4_AP,  "MEM-AP APB4" },
+       { AP_TYPE_AXI5_AP,  "MEM-AP AXI5" },
+       { AP_TYPE_AHB5H_AP, "MEM-AP AHB5 with enhanced HPROT" },
+};
+
+static const char *ap_type_to_description(enum ap_type type)
 {
-       return (cid & 0xffff0fff) == 0xb105000d;
+       for (unsigned int i = 0; i < ARRAY_SIZE(ap_types); i++)
+               if (type == ap_types[i].type)
+                       return ap_types[i].description;
+
+       return "Unknown";
 }
 
 /*
@@ -915,29 +936,12 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_a
 
                retval = dap_run(dap);
 
-               /* IDR bits:
-                * 31-28 : Revision
-                * 27-24 : JEDEC bank (0x4 for ARM)
-                * 23-17 : JEDEC code (0x3B for ARM)
-                * 16-13 : Class (0b1000=Mem-AP)
-                * 12-8  : Reserved
-                *  7-4  : AP Variant (non-zero for JTAG-AP)
-                *  3-0  : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
-                */
-
                /* Reading register for a non-existent AP should not cause an error,
                 * but just to be sure, try to continue searching if an error does happen.
                 */
-               if ((retval == ERROR_OK) &&                  /* Register read success */
-                       ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
-                       ((id_val & IDR_TYPE) == type_to_find)) {      /* type matches*/
-
+               if (retval == ERROR_OK && (id_val & AP_TYPE_MASK) == type_to_find) {
                        LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
-                                               (type_to_find == AP_TYPE_AHB3_AP)  ? "AHB3-AP"  :
-                                               (type_to_find == AP_TYPE_AHB5_AP)  ? "AHB5-AP"  :
-                                               (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
-                                               (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
-                                               (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
+                                               ap_type_to_description(type_to_find),
                                                ap_num, id_val);
 
                        *ap_out = &dap->ap[ap_num];
@@ -945,12 +949,7 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_a
                }
        }
 
-       LOG_DEBUG("No %s found",
-                               (type_to_find == AP_TYPE_AHB3_AP)  ? "AHB3-AP"  :
-                               (type_to_find == AP_TYPE_AHB5_AP)  ? "AHB5-AP"  :
-                               (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
-                               (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
-                               (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
+       LOG_DEBUG("No %s found", ap_type_to_description(type_to_find));
        return ERROR_FAIL;
 }
 
@@ -1006,17 +1005,18 @@ int dap_lookup_cs_component(struct adiv5_ap *ap,
                if (retval != ERROR_OK)
                        return retval;
 
-               component_base = dbgbase + (target_addr_t)(romentry & 0xFFFFF000);
+               component_base = dbgbase + (target_addr_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK);
 
-               if (romentry & 0x1) {
+               if (romentry & ARM_CS_ROMENTRY_PRESENT) {
                        uint32_t c_cid1;
-                       retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
+                       retval = mem_ap_read_atomic_u32(ap, component_base + ARM_CS_CIDR1, &c_cid1);
                        if (retval != ERROR_OK) {
                                LOG_ERROR("Can't read component with base address " TARGET_ADDR_FMT
                                          ", the corresponding core might be turned off", component_base);
                                return retval;
                        }
-                       if (((c_cid1 >> 4) & 0x0f) == 1) {
+                       unsigned int class = (c_cid1 & ARM_CS_CIDR1_CLASS_MASK) >> ARM_CS_CIDR1_CLASS_SHIFT;
+                       if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
                                retval = dap_lookup_cs_component(ap, component_base,
                                                        type, addr, idx);
                                if (retval == ERROR_OK)
@@ -1025,10 +1025,10 @@ int dap_lookup_cs_component(struct adiv5_ap *ap,
                                        return retval;
                        }
 
-                       retval = mem_ap_read_atomic_u32(ap, component_base | 0xfcc, &devtype);
+                       retval = mem_ap_read_atomic_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &devtype);
                        if (retval != ERROR_OK)
                                return retval;
-                       if ((devtype & 0xff) == type) {
+                       if ((devtype & ARM_CS_C9_DEVTYPE_MASK) == type) {
                                if (!*idx) {
                                        *addr = component_base;
                                        break;
@@ -1047,7 +1047,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap,
 
 static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, uint32_t *cid, uint64_t *pid)
 {
-       assert((component_base & 0xFFF) == 0);
+       assert(IS_ALIGNED(component_base, ARM_CS_ALIGN));
        assert(ap && cid && pid);
 
        uint32_t cid0, cid1, cid2, cid3;
@@ -1055,31 +1055,31 @@ static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, u
        int retval;
 
        /* IDs are in last 4K section */
-       retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
+       retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR0, &pid0);
        if (retval != ERROR_OK)
                return retval;
-       retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
+       retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR1, &pid1);
        if (retval != ERROR_OK)
                return retval;
-       retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
+       retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR2, &pid2);
        if (retval != ERROR_OK)
                return retval;
-       retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
+       retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR3, &pid3);
        if (retval != ERROR_OK)
                return retval;
-       retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
+       retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR4, &pid4);
        if (retval != ERROR_OK)
                return retval;
-       retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
+       retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR0, &cid0);
        if (retval != ERROR_OK)
                return retval;
-       retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
+       retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR1, &cid1);
        if (retval != ERROR_OK)
                return retval;
-       retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
+       retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR2, &cid2);
        if (retval != ERROR_OK)
                return retval;
-       retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
+       retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR3, &cid3);
        if (retval != ERROR_OK)
                return retval;
 
@@ -1100,14 +1100,6 @@ static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, u
        return ERROR_OK;
 }
 
-/* The designer identity code is encoded as:
- * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
- * bit 7     : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
- *             a legacy ASCII Identity Code.
- * bits 6:0  : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
- * JEP106 is a standard available from jedec.org
- */
-
 /* Part number interpretations are from Cortex
  * core specs, the CoreSight components TRM
  * (ARM DDI 0314H), CoreSight System Design
@@ -1115,22 +1107,12 @@ static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, u
  * from chip observation (e.g. TI SDTI).
  */
 
-/* The legacy code only used the part number field to identify CoreSight peripherals.
- * This meant that the same part number from two different manufacturers looked the same.
- * It is desirable for all future additions to identify with both part number and JEP106.
- * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
- */
-
-#define ANY_ID 0x1000
-
-#define ARM_ID 0x23B
-
-static const struct {
+static const struct dap_part_nums {
        uint16_t designer_id;
        uint16_t part_num;
        const char *type;
        const char *full;
-} dap_partnums[] = {
+} dap_part_nums[] = {
        { ARM_ID, 0x000, "Cortex-M3 SCS",              "(System Control Space)", },
        { ARM_ID, 0x001, "Cortex-M3 ITM",              "(Instrumentation Trace Module)", },
        { ARM_ID, 0x002, "Cortex-M3 DWT",              "(Data Watchpoint and Trace)", },
@@ -1141,9 +1123,12 @@ static const struct {
        { ARM_ID, 0x00c, "Cortex-M4 SCS",              "(System Control Space)", },
        { ARM_ID, 0x00d, "CoreSight ETM11",            "(Embedded Trace)", },
        { ARM_ID, 0x00e, "Cortex-M7 FPB",              "(Flash Patch and Breakpoint)", },
+       { ARM_ID, 0x193, "SoC-600 TSGEN",              "(Timestamp Generator)", },
        { ARM_ID, 0x470, "Cortex-M1 ROM",              "(ROM Table)", },
        { ARM_ID, 0x471, "Cortex-M0 ROM",              "(ROM Table)", },
        { ARM_ID, 0x490, "Cortex-A15 GIC",             "(Generic Interrupt Controller)", },
+       { ARM_ID, 0x492, "Cortex-R52 GICD",            "(Distributor)", },
+       { ARM_ID, 0x493, "Cortex-R52 GICR",            "(Redistributor)", },
        { ARM_ID, 0x4a1, "Cortex-A53 ROM",             "(v8 Memory Map ROM Table)", },
        { ARM_ID, 0x4a2, "Cortex-A57 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4a3, "Cortex-A53 ROM",             "(v7 Memory Map ROM Table)", },
@@ -1152,6 +1137,7 @@ static const struct {
        { ARM_ID, 0x4aa, "Cortex-A35 ROM",             "(v8 Memory Map ROM Table)", },
        { ARM_ID, 0x4af, "Cortex-A15 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4b5, "Cortex-R5 ROM",              "(ROM Table)", },
+       { ARM_ID, 0x4b8, "Cortex-R52 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4c0, "Cortex-M0+ ROM",             "(ROM Table)", },
        { ARM_ID, 0x4c3, "Cortex-M3 ROM",              "(ROM Table)", },
        { ARM_ID, 0x4c4, "Cortex-M4 ROM",              "(ROM Table)", },
@@ -1197,11 +1183,25 @@ static const struct {
        { ARM_ID, 0x9a9, "Cortex-M7 TPIU",             "(Trace Port Interface Unit)", },
        { ARM_ID, 0x9ae, "Cortex-A17 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9af, "Cortex-A15 PMU",             "(Performance Monitor Unit)", },
+       { ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
        { ARM_ID, 0x9b7, "Cortex-R7 PMU",              "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d3, "Cortex-A53 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d7, "Cortex-A57 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d8, "Cortex-A72 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
+       { ARM_ID, 0x9e2, "SoC-600 APB-AP",             "(APB4 Memory Access Port)", },
+       { ARM_ID, 0x9e3, "SoC-600 AHB-AP",             "(AHB5 Memory Access Port)", },
+       { ARM_ID, 0x9e4, "SoC-600 AXI-AP",             "(AXI Memory Access Port)", },
+       { ARM_ID, 0x9e5, "SoC-600 APv1 Adapter",       "(Access Port v1 Adapter)", },
+       { ARM_ID, 0x9e6, "SoC-600 JTAG-AP",            "(JTAG Access Port)", },
+       { ARM_ID, 0x9e7, "SoC-600 TPIU",               "(Trace Port Interface Unit)", },
+       { ARM_ID, 0x9e8, "SoC-600 TMC ETR/ETS",        "(Embedded Trace Router/Streamer)", },
+       { ARM_ID, 0x9e9, "SoC-600 TMC ETB",            "(Embedded Trace Buffer)", },
+       { ARM_ID, 0x9ea, "SoC-600 TMC ETF",            "(Embedded Trace FIFO)", },
+       { ARM_ID, 0x9eb, "SoC-600 ATB Funnel",         "(Trace Funnel)", },
+       { ARM_ID, 0x9ec, "SoC-600 ATB Replicator",     "(Trace Replicator)", },
+       { ARM_ID, 0x9ed, "SoC-600 CTI",                "(Cross Trigger)", },
+       { ARM_ID, 0x9ee, "SoC-600 CATU",               "(Address Translation Unit)", },
        { ARM_ID, 0xc05, "Cortex-A5 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc07, "Cortex-A7 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc08, "Cortex-A8 Debug",            "(Debug Unit)", },
@@ -1216,6 +1216,11 @@ static const struct {
        { ARM_ID, 0xd07, "Cortex-A57 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd08, "Cortex-A72 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd0b, "Cortex-A76 Debug",           "(Debug Unit)", },
+       { ARM_ID, 0xd0c, "Neoverse N1",                "(Debug Unit)", },
+       { ARM_ID, 0xd13, "Cortex-R52 Debug",           "(Debug Unit)", },
+       { ARM_ID, 0xd49, "Neoverse N2",                "(Debug Unit)", },
+       { 0x017,  0x120, "TI SDTI",                    "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
+       { 0x017,  0x343, "TI DAPCTL",                  "", }, /* from OMAP3 memmap */
        { 0x017,  0x9af, "MSP432 ROM",                 "(ROM Table)" },
        { 0x01f,  0xcd0, "Atmel CPU with DSU",         "(CPU)" },
        { 0x041,  0x1db, "XMC4500 ROM",                "(ROM Table)" },
@@ -1232,11 +1237,166 @@ static const struct {
        { 0x1eb,  0x211, "Tegra 210 ROM",              "(ROM Table)", },
        { 0x1eb,  0x302, "Denver Debug",               "(Debug Unit)", },
        { 0x1eb,  0x402, "Denver PMU",                 "(Performance Monitor Unit)", },
-       /* legacy comment: 0x113: what? */
-       { ANY_ID, 0x120, "TI SDTI",                    "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
-       { ANY_ID, 0x343, "TI DAPCTL",                  "", }, /* from OMAP3 memmap */
 };
 
+static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
+{
+       static const struct dap_part_nums unknown = {
+               .type = "Unrecognized",
+               .full = "",
+       };
+
+       for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++)
+               if (dap_part_nums[i].designer_id == designer_id && dap_part_nums[i].part_num == part_num)
+                       return &dap_part_nums[i];
+
+       return &unknown;
+}
+
+static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
+{
+       const char *major = "Reserved", *subtype = "Reserved";
+       const unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
+       const unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
+       switch (devtype_major) {
+       case 0:
+               major = "Miscellaneous";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 4:
+                       subtype = "Validation component";
+                       break;
+               }
+               break;
+       case 1:
+               major = "Trace Sink";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Port";
+                       break;
+               case 2:
+                       subtype = "Buffer";
+                       break;
+               case 3:
+                       subtype = "Router";
+                       break;
+               }
+               break;
+       case 2:
+               major = "Trace Link";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Funnel, router";
+                       break;
+               case 2:
+                       subtype = "Filter";
+                       break;
+               case 3:
+                       subtype = "FIFO, buffer";
+                       break;
+               }
+               break;
+       case 3:
+               major = "Trace Source";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Processor";
+                       break;
+               case 2:
+                       subtype = "DSP";
+                       break;
+               case 3:
+                       subtype = "Engine/Coprocessor";
+                       break;
+               case 4:
+                       subtype = "Bus";
+                       break;
+               case 6:
+                       subtype = "Software";
+                       break;
+               }
+               break;
+       case 4:
+               major = "Debug Control";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Trigger Matrix";
+                       break;
+               case 2:
+                       subtype = "Debug Auth";
+                       break;
+               case 3:
+                       subtype = "Power Requestor";
+                       break;
+               }
+               break;
+       case 5:
+               major = "Debug Logic";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Processor";
+                       break;
+               case 2:
+                       subtype = "DSP";
+                       break;
+               case 3:
+                       subtype = "Engine/Coprocessor";
+                       break;
+               case 4:
+                       subtype = "Bus";
+                       break;
+               case 5:
+                       subtype = "Memory";
+                       break;
+               }
+               break;
+       case 6:
+               major = "Performance Monitor";
+               switch (minor) {
+               case 0:
+                       subtype = "other";
+                       break;
+               case 1:
+                       subtype = "Processor";
+                       break;
+               case 2:
+                       subtype = "DSP";
+                       break;
+               case 3:
+                       subtype = "Engine/Coprocessor";
+                       break;
+               case 4:
+                       subtype = "Bus";
+                       break;
+               case 5:
+                       subtype = "Memory";
+                       break;
+               }
+               break;
+       }
+       command_print(cmd, "\t\tType is 0x%02x, %s, %s",
+                       devtype & ARM_CS_C9_DEVTYPE_MASK,
+                       major, subtype);
+       return ERROR_OK;
+}
+
 static int dap_rom_display(struct command_invocation *cmd,
                                struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
 {
@@ -1262,61 +1422,44 @@ static int dap_rom_display(struct command_invocation *cmd,
                return ERROR_OK; /* Don't abort recursion */
        }
 
-       if (!is_dap_cid_ok(cid)) {
+       if (!is_valid_arm_cs_cidr(cid)) {
                command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
                return ERROR_OK; /* Don't abort recursion */
        }
 
        /* component may take multiple 4K pages */
-       uint32_t size = (pid >> 36) & 0xf;
+       uint32_t size = ARM_CS_PIDR_SIZE(pid);
        if (size > 0)
                command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_addr - 0x1000 * size);
 
        command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
 
-       uint8_t class = (cid >> 12) & 0xf;
-       uint16_t part_num = pid & 0xfff;
-       uint16_t designer_id = ((pid >> 32) & 0xf) << 7 | ((pid >> 12) & 0x7f);
+       const unsigned int class = (cid & ARM_CS_CIDR_CLASS_MASK) >> ARM_CS_CIDR_CLASS_SHIFT;
+       const unsigned int part_num = ARM_CS_PIDR_PART(pid);
+       unsigned int designer_id = ARM_CS_PIDR_DESIGNER(pid);
 
-       if (pid & 0x00080000) {
+       if (pid & ARM_CS_PIDR_JEDEC) {
                /* JEP106 code */
-               command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
+               command_print(cmd, "\t\tDesigner is 0x%03x, %s",
                                designer_id, jep106_manufacturer(designer_id));
        } else {
                /* Legacy ASCII ID, clear invalid bits */
                designer_id &= 0x7f;
-               command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
+               command_print(cmd, "\t\tDesigner ASCII code 0x%02x, %s",
                                designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
        }
 
-       /* default values to be overwritten upon finding a match */
-       const char *type = "Unrecognized";
-       const char *full = "";
-
-       /* search dap_partnums[] array for a match */
-       for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
-
-               if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
-                       continue;
-
-               if (dap_partnums[entry].part_num != part_num)
-                       continue;
-
-               type = dap_partnums[entry].type;
-               full = dap_partnums[entry].full;
-               break;
-       }
+       const struct dap_part_nums *partnum = pidr_to_part_num(designer_id, part_num);
+       command_print(cmd, "\t\tPart is 0x%03x, %s %s", part_num, partnum->type, partnum->full);
+       command_print(cmd, "\t\tComponent class is 0x%x, %s", class, class_description[class]);
 
-       command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
-       command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
-
-       if (class == 1) { /* ROM Table */
+       if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
                uint32_t memtype;
-               retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
+               retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C1_MEMTYPE, &memtype);
                if (retval != ERROR_OK)
                        return retval;
 
-               if (memtype & 0x01)
+               if (memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
                        command_print(cmd, "\t\tMEMTYPE system memory present on bus");
                else
                        command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
@@ -1329,9 +1472,10 @@ static int dap_rom_display(struct command_invocation *cmd,
                                return retval;
                        command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
                                        tabs, entry_offset, romentry);
-                       if (romentry & 0x01) {
+                       if (romentry & ARM_CS_ROMENTRY_PRESENT) {
                                /* Recurse. "romentry" is signed */
-                               retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & 0xFFFFF000), depth + 1);
+                               retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK),
+                                                                                depth + 1);
                                if (retval != ERROR_OK)
                                        return retval;
                        } else if (romentry != 0) {
@@ -1341,151 +1485,17 @@ static int dap_rom_display(struct command_invocation *cmd,
                                break;
                        }
                }
-       } else if (class == 9) { /* CoreSight component */
-               const char *major = "Reserved", *subtype = "Reserved";
-
+       } else if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
                uint32_t devtype;
-               retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
+               retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVTYPE, &devtype);
                if (retval != ERROR_OK)
                        return retval;
-               unsigned minor = (devtype >> 4) & 0x0f;
-               switch (devtype & 0x0f) {
-               case 0:
-                       major = "Miscellaneous";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 4:
-                               subtype = "Validation component";
-                               break;
-                       }
-                       break;
-               case 1:
-                       major = "Trace Sink";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Port";
-                               break;
-                       case 2:
-                               subtype = "Buffer";
-                               break;
-                       case 3:
-                               subtype = "Router";
-                               break;
-                       }
-                       break;
-               case 2:
-                       major = "Trace Link";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Funnel, router";
-                               break;
-                       case 2:
-                               subtype = "Filter";
-                               break;
-                       case 3:
-                               subtype = "FIFO, buffer";
-                               break;
-                       }
-                       break;
-               case 3:
-                       major = "Trace Source";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Processor";
-                               break;
-                       case 2:
-                               subtype = "DSP";
-                               break;
-                       case 3:
-                               subtype = "Engine/Coprocessor";
-                               break;
-                       case 4:
-                               subtype = "Bus";
-                               break;
-                       case 6:
-                               subtype = "Software";
-                               break;
-                       }
-                       break;
-               case 4:
-                       major = "Debug Control";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Trigger Matrix";
-                               break;
-                       case 2:
-                               subtype = "Debug Auth";
-                               break;
-                       case 3:
-                               subtype = "Power Requestor";
-                               break;
-                       }
-                       break;
-               case 5:
-                       major = "Debug Logic";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Processor";
-                               break;
-                       case 2:
-                               subtype = "DSP";
-                               break;
-                       case 3:
-                               subtype = "Engine/Coprocessor";
-                               break;
-                       case 4:
-                               subtype = "Bus";
-                               break;
-                       case 5:
-                               subtype = "Memory";
-                               break;
-                       }
-                       break;
-               case 6:
-                       major = "Performance Monitor";
-                       switch (minor) {
-                       case 0:
-                               subtype = "other";
-                               break;
-                       case 1:
-                               subtype = "Processor";
-                               break;
-                       case 2:
-                               subtype = "DSP";
-                               break;
-                       case 3:
-                               subtype = "Engine/Coprocessor";
-                               break;
-                       case 4:
-                               subtype = "Bus";
-                               break;
-                       case 5:
-                               subtype = "Memory";
-                               break;
-                       }
-                       break;
-               }
-               command_print(cmd, "\t\tType is 0x%02" PRIx8 ", %s, %s",
-                               (uint8_t)(devtype & 0xff),
-                               major, subtype);
-               /* REVISIT also show 0xfc8 DevId */
+
+               retval = dap_devtype_display(cmd, devtype);
+               if (retval != ERROR_OK)
+                       return retval;
+
+               /* REVISIT also show ARM_CS_C9_DEVID */
        }
 
        return ERROR_OK;
@@ -1498,7 +1508,6 @@ int dap_info_command(struct command_invocation *cmd,
        uint32_t apid;
        target_addr_t dbgbase;
        target_addr_t dbgaddr;
-       uint8_t mem_ap;
 
        /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
        retval = dap_get_debugbase(ap, &dbgbase, &apid);
@@ -1511,32 +1520,14 @@ int dap_info_command(struct command_invocation *cmd,
                return ERROR_FAIL;
        }
 
-       switch (apid & (IDR_JEP106 | IDR_TYPE)) {
-       case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
-               command_print(cmd, "\tType is JTAG-AP");
-               break;
-       case IDR_JEP106_ARM | AP_TYPE_AHB3_AP:
-               command_print(cmd, "\tType is MEM-AP AHB3");
-               break;
-       case IDR_JEP106_ARM | AP_TYPE_AHB5_AP:
-               command_print(cmd, "\tType is MEM-AP AHB5");
-               break;
-       case IDR_JEP106_ARM | AP_TYPE_APB_AP:
-               command_print(cmd, "\tType is MEM-AP APB");
-               break;
-       case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
-               command_print(cmd, "\tType is MEM-AP AXI");
-               break;
-       default:
-               command_print(cmd, "\tUnknown AP type");
-               break;
-       }
+       command_print(cmd, "\tType is %s", ap_type_to_description(apid & AP_TYPE_MASK));
 
        /* NOTE: a MEM-AP may have a single CoreSight component that's
         * not a ROM table ... or have no such components at all.
         */
-       mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
-       if (mem_ap) {
+       const unsigned int class = (apid & AP_REG_IDR_CLASS_MASK) >> AP_REG_IDR_CLASS_SHIFT;
+
+       if (class == AP_REG_IDR_CLASS_MEM_AP) {
                if (is_64bit_ap(ap))
                        dbgaddr = 0xFFFFFFFFFFFFFFFFull;
                else
index 73ceea03f0718914f0f84e302b355f1080863205..0e1b95f50a4a443c607d0f4113efab7070ed53ce 100644 (file)
@@ -33,6 +33,9 @@
 #include "arm_jtag.h"
 #include "helper/bits.h"
 
+/* JEP106 ID for ARM */
+#define ARM_ID 0x23B
+
 /* three-bit ACK values for SWD access (sent LSB first) */
 #define SWD_ACK_OK    0x1
 #define SWD_ACK_WAIT  0x2
 #define MEM_AP_REG_CFG_INVALID  0xFFFFFFF8
 
 /* Fields of the MEM-AP's IDR register */
-#define IDR_REV     (0xFUL << 28)
-#define IDR_JEP106  (0x7FFUL << 17)
-#define IDR_CLASS   (0xFUL << 13)
-#define IDR_VARIANT (0xFUL << 4)
-#define IDR_TYPE    (0xFUL << 0)
-
-#define IDR_JEP106_ARM 0x04760000
+#define AP_REG_IDR_REVISION_MASK        (0xF0000000)
+#define AP_REG_IDR_REVISION_SHIFT       (28)
+#define AP_REG_IDR_DESIGNER_MASK        (0x0FFE0000)
+#define AP_REG_IDR_DESIGNER_SHIFT       (17)
+#define AP_REG_IDR_CLASS_MASK           (0x0001E000)
+#define AP_REG_IDR_CLASS_SHIFT          (13)
+#define AP_REG_IDR_VARIANT_MASK         (0x000000F0)
+#define AP_REG_IDR_VARIANT_SHIFT        (4)
+#define AP_REG_IDR_TYPE_MASK            (0x0000000F)
+#define AP_REG_IDR_TYPE_SHIFT           (0)
+
+#define AP_REG_IDR_CLASS_NONE           (0x0)
+#define AP_REG_IDR_CLASS_COM            (0x1)
+#define AP_REG_IDR_CLASS_MEM_AP         (0x8)
+
+#define AP_REG_IDR_VALUE(d, c, t) (\
+       (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
+       (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
+       (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
+)
+
+#define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
 
 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
 enum swd_special_seq {
@@ -349,23 +367,19 @@ struct dap_ops {
        void (*quit)(struct adiv5_dap *dap);
 };
 
-/*
- * Access Port classes
- */
-enum ap_class {
-       AP_CLASS_NONE   = 0x00000,  /* No class defined */
-       AP_CLASS_MEM_AP = 0x10000,  /* MEM-AP */
-};
-
 /*
  * Access Port types
  */
 enum ap_type {
-       AP_TYPE_JTAG_AP = 0x0,  /* JTAG-AP - JTAG master for controlling other JTAG devices */
-       AP_TYPE_AHB3_AP = 0x1,  /* AHB3 Memory-AP */
-       AP_TYPE_APB_AP  = 0x2,  /* APB Memory-AP */
-       AP_TYPE_AXI_AP  = 0x4,  /* AXI Memory-AP */
-       AP_TYPE_AHB5_AP = 0x5,  /* AHB5 Memory-AP. */
+       AP_TYPE_JTAG_AP  = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_NONE,   0),  /* JTAG-AP */
+       AP_TYPE_COM_AP   = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_COM,    0),  /* COM-AP */
+       AP_TYPE_AHB3_AP  = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 1),  /* AHB3 Memory-AP */
+       AP_TYPE_APB_AP   = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 2),  /* APB2 or APB3 Memory-AP */
+       AP_TYPE_AXI_AP   = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 4),  /* AXI3 or AXI4 Memory-AP */
+       AP_TYPE_AHB5_AP  = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 5),  /* AHB5 Memory-AP */
+       AP_TYPE_APB4_AP  = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 6),  /* APB4 Memory-AP */
+       AP_TYPE_AXI5_AP  = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 7),  /* AXI5 Memory-AP */
+       AP_TYPE_AHB5H_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 8),  /* AHB5 with enhanced HPROT Memory-AP */
 };
 
 /* Check the ap->cfg_reg Long Address field (bit 1)
diff --git a/src/target/arm_coresight.h b/src/target/arm_coresight.h
new file mode 100644 (file)
index 0000000..42e6c5e
--- /dev/null
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * General info from:
+ * ARM CoreSight Architecture Specification v3.0 IHI0029E
+ */
+
+#ifndef OPENOCD_TARGET_ARM_CORESIGHT_H
+#define OPENOCD_TARGET_ARM_CORESIGHT_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <src/helper/bits.h>
+
+#define ARM_CS_ALIGN                            (0x1000)
+
+/* mandatory registers */
+#define ARM_CS_PIDR0                            (0xFE0)
+#define ARM_CS_PIDR1                            (0xFE4)
+#define ARM_CS_PIDR2                            (0xFE8)
+#define ARM_CS_PIDR3                            (0xFEC)
+#define ARM_CS_PIDR4                            (0xFD0)
+#define ARM_CS_PIDR5                            (0xFD4)
+#define ARM_CS_PIDR6                            (0xFD8)
+#define ARM_CS_PIDR7                            (0xFDC)
+
+/*
+ * When PIDR bit JEDEC is zero, only the lowers 7 bits of DESIGNER are valid
+ * and represent a legacy ASCII Identity Code.
+ */
+#define ARM_CS_PIDR_PART(pidr)                  ((pidr) & 0x0FFF)
+#define ARM_CS_PIDR_DESIGNER(pidr)              \
+({                                              \
+       typeof(pidr) _x = (pidr);                   \
+       ((_x >> 25) & 0x780) | ((_x >> 12) & 0x7F); \
+})
+#define ARM_CS_PIDR_JEDEC                       BIT(19)
+#define ARM_CS_PIDR_SIZE(pidr)                  (((pidr) >> 36) & 0x000F)
+
+#define ARM_CS_CIDR0                            (0xFF0)
+#define ARM_CS_CIDR1                            (0xFF4)
+#define ARM_CS_CIDR2                            (0xFF8)
+#define ARM_CS_CIDR3                            (0xFFC)
+
+#define ARM_CS_CIDR_CLASS_MASK                  (0x0000F000)
+#define ARM_CS_CIDR_CLASS_SHIFT                 (12)
+#define ARM_CS_CLASS_0X1_ROM_TABLE              (0x1)
+#define ARM_CS_CLASS_0X9_CS_COMPONENT           (0x9)
+
+#define ARM_CS_CIDR1_CLASS_MASK                 (0x000000F0)
+#define ARM_CS_CIDR1_CLASS_SHIFT                (4)
+
+static inline bool is_valid_arm_cs_cidr(uint32_t cidr)
+{
+       return (cidr & ~ARM_CS_CIDR_CLASS_MASK) == 0xB105000D;
+}
+
+/* Class 0x9 only registers */
+#define ARM_CS_C9_DEVARCH                       (0xFBC)
+
+#define ARM_CS_C9_DEVARCH_ARCHID_MASK           (0x0000FFFF)
+#define ARM_CS_C9_DEVARCH_ARCHID_SHIFT          (0)
+#define ARM_CS_C9_DEVARCH_REVISION_MASK         (0x000F0000)
+#define ARM_CS_C9_DEVARCH_REVISION_SHIFT        (16)
+#define ARM_CS_C9_DEVARCH_PRESENT               BIT(20)
+#define ARM_CS_C9_DEVARCH_ARCHITECT_MASK        (0xFFE00000)
+#define ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT       (21)
+
+#define ARM_CS_C9_DEVID                         (0xFC8)
+
+#define ARM_CS_C9_DEVID_FORMAT_MASK             (0x0000000F)
+#define ARM_CS_C9_DEVID_FORMAT_32BIT            (0)
+#define ARM_CS_C9_DEVID_FORMAT_64BIT            (1)
+#define ARM_CS_C9_DEVID_SYSMEM_MASK             BIT(4)
+#define ARM_CS_C9_DEVID_PRR_MASK                BIT(5)
+#define ARM_CS_C9_DEVID_CP_MASK                 BIT(5)
+
+#define ARM_CS_C9_DEVTYPE                       (0xFCC)
+
+#define ARM_CS_C9_DEVTYPE_MAJOR_MASK            (0x0000000F)
+#define ARM_CS_C9_DEVTYPE_MAJOR_SHIFT           (0)
+#define ARM_CS_C9_DEVTYPE_SUB_MASK              (0x000000F0)
+#define ARM_CS_C9_DEVTYPE_SUB_SHIFT             (4)
+
+#define ARM_CS_C9_DEVTYPE_MASK                  (0x000000FF)
+#define ARM_CS_C9_DEVTYPE_CORE_DEBUG            (0x00000015)
+
+/* Class 0x1 only registers */
+#define ARM_CS_C1_MEMTYPE                       ARM_CS_C9_DEVTYPE
+
+#define ARM_CS_C1_MEMTYPE_SYSMEM_MASK           BIT(0)
+
+/* The coding of ROM entry present differs between Class 0x9 and Class 0x1,
+ * but we can simplify the whole management */
+#define ARM_CS_ROMENTRY_PRESENT                 BIT(0)
+#define ARM_CS_ROMENTRY_OFFSET_MASK             (0xFFFFF000U)
+
+#endif /* OPENOCD_TARGET_ARM_CORESIGHT_H */
index 7d005e2b127752d4387eba40423333ff06122e23..c776e9c2a5c35e967b87e494e4c8f74321eef8db 100644 (file)
@@ -465,7 +465,7 @@ static int cti_create(struct jim_getopt_info *goi)
        /* COMMAND */
        jim_getopt_obj(goi, &new_cmd);
        /* does this command exist? */
-       cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_ERRMSG);
+       cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_NONE);
        if (cmd) {
                cp = Jim_GetString(new_cmd, NULL);
                Jim_SetResultFormatted(goi->interp, "Command: %s Exists", cp);
index 2f21aa170d4b125e539be8ed7ad7fdc715548f2a..94edfc09d14116859955ffc3a263b5aad612b71d 100644 (file)
@@ -230,7 +230,7 @@ static int dap_create(struct jim_getopt_info *goi)
        /* COMMAND */
        jim_getopt_obj(goi, &new_cmd);
        /* does this command exist? */
-       cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_ERRMSG);
+       cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_NONE);
        if (cmd) {
                cp = Jim_GetString(new_cmd, NULL);
                Jim_SetResultFormatted(goi->interp, "Command: %s Exists", cp);
index 746ab393ee0acca0070468da6a1f49cccb5a7791..f2b514826eaafd29e28e78105a07f7e1c6cb665f 100644 (file)
@@ -764,6 +764,10 @@ static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const
 
        arm_tpiu_swo_handle_event(obj, TPIU_SWO_EVENT_POST_ENABLE);
 
+       /* START_DEPRECATED_TPIU */
+       target_handle_event(target, TARGET_EVENT_TRACE_CONFIG);
+       /* END_DEPRECATED_TPIU */
+
        obj->enabled = true;
        return JIM_OK;
 
@@ -817,6 +821,13 @@ static int jim_arm_tpiu_swo_disable(Jim_Interp *interp, int argc, Jim_Obj *const
        }
 
        arm_tpiu_swo_handle_event(obj, TPIU_SWO_EVENT_POST_DISABLE);
+
+       /* START_DEPRECATED_TPIU */
+       struct command_context *cmd_ctx = current_command_context(interp);
+       struct target *target = get_current_target(cmd_ctx);
+       target_handle_event(target, TARGET_EVENT_TRACE_CONFIG);
+       /* END_DEPRECATED_TPIU */
+
        return JIM_OK;
 }
 
@@ -869,7 +880,7 @@ static int arm_tpiu_swo_create(Jim_Interp *interp, struct arm_tpiu_swo_object *o
        assert(cmd_ctx);
 
        /* does this command exist? */
-       cmd = Jim_GetCommand(interp, Jim_NewStringObj(interp, obj->name, -1), JIM_ERRMSG);
+       cmd = Jim_GetCommand(interp, Jim_NewStringObj(interp, obj->name, -1), JIM_NONE);
        if (cmd) {
                Jim_SetResultFormatted(interp, "Command: %s Exists", obj->name);
                return JIM_ERR;
@@ -1112,7 +1123,6 @@ COMMAND_HANDLER(handle_tpiu_deprecated_config_command)
        if (retval != ERROR_OK)
                return retval;
 
-       target_handle_event(target, TARGET_EVENT_TRACE_CONFIG);
        return ERROR_OK;
 }
 
index 68da020a13f8d45d26813bb679b909c40da23d90..ffc8ca875db0675a477fd11142d8ec207efaf41a 100644 (file)
@@ -44,6 +44,8 @@
 #include "algorithm.h"
 #include "register.h"
 #include "semihosting_common.h"
+#include <helper/log.h>
+#include <helper/binarybuffer.h>
 
 #if 0
 #define _DEBUG_INSTRUCTION_EXECUTION_
index f3eb90f248616cfc784f80e67c5beca73e4f1d54..2816a91452404d3c63b22bdcd079932dc3cfb6d3 100644 (file)
 #ifndef OPENOCD_TARGET_ARMV7M_H
 #define OPENOCD_TARGET_ARMV7M_H
 
-#include "arm_adi_v5.h"
 #include "arm.h"
 #include "armv7m_trace.h"
 
+struct adiv5_ap;
+
 extern const int armv7m_psp_reg_map[];
 extern const int armv7m_msp_reg_map[];
 
index eaee6a48f1efab20218d929f321b704bb4a8baa6..7e4977aba72a67f95b91cfca368c93558312bb2c 100644 (file)
@@ -18,8 +18,8 @@
 #ifndef OPENOCD_TARGET_ARMV7M_TRACE_H
 #define OPENOCD_TARGET_ARMV7M_TRACE_H
 
+#include <helper/command.h>
 #include <target/target.h>
-#include <command.h>
 
 /**
  * @file
index 241f2e68444b26f5d0d2c5398b691e85675f1b0c..bf65544f51afa133d33a458ccd51c4adcbc5c6d4 100644 (file)
@@ -56,6 +56,7 @@
 #include "armv7a_mmu.h"
 #include "target_request.h"
 #include "target_type.h"
+#include "arm_coresight.h"
 #include "arm_opcodes.h"
 #include "arm_semihosting.h"
 #include "jtag/interface.h"
@@ -2921,8 +2922,8 @@ static int cortex_a_examine_first(struct target *target)
                retval = dap_get_debugbase(armv7a->debug_ap, &dbgbase, &apid);
                if (retval != ERROR_OK)
                        return retval;
-               /* Lookup 0x15 -- Processor DAP */
-               retval = dap_lookup_cs_component(armv7a->debug_ap, dbgbase, 0x15,
+               /* Lookup Processor DAP */
+               retval = dap_lookup_cs_component(armv7a->debug_ap, dbgbase, ARM_CS_C9_DEVTYPE_CORE_DEBUG,
                                &armv7a->debug_base, &coreidx);
                if (retval != ERROR_OK) {
                        LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
index 08f2eb91176c536e190240874f84bc87f9a667d0..3412c567711dcbdcaf170bbfdf1f1479ed81308b 100644 (file)
@@ -34,6 +34,7 @@
 #include "cortex_m.h"
 #include "target_request.h"
 #include "target_type.h"
+#include "arm_adi_v5.h"
 #include "arm_disassembler.h"
 #include "register.h"
 #include "arm_opcodes.h"
@@ -2081,8 +2082,12 @@ int cortex_m_examine(struct target *target)
 
                armv7m->arm.arch = cortex_m->core_info->arch;
 
-               LOG_DEBUG("%s r%" PRId8 "p%" PRId8 " processor detected",
-                               cortex_m->core_info->name, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
+               LOG_INFO("%s: %s r%" PRId8 "p%" PRId8 " processor detected",
+                               target_name(target),
+                               cortex_m->core_info->name,
+                               (uint8_t)((cpuid >> 20) & 0xf),
+                               (uint8_t)((cpuid >> 0) & 0xf));
+
                cortex_m->maskints_erratum = false;
                if (core_partno == CORTEX_M7_PARTNO) {
                        uint8_t rev, patch;
@@ -2191,7 +2196,7 @@ int cortex_m_examine(struct target *target)
                cortex_m_dwt_setup(cortex_m, target);
 
                /* These hardware breakpoints only work for code in flash! */
-               LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
+               LOG_INFO("%s: target has %d breakpoints, %d watchpoints",
                        target_name(target),
                        cortex_m->fp_num_code,
                        cortex_m->dwt_num_comp);
index 91861054f47d2109e060657da8778ce7adf67511..c67c9cc897633f4827c899c74fb822b4ebb71104 100644 (file)
@@ -37,6 +37,7 @@
 #include "target_type.h"
 #include "armv7m.h"
 #include "cortex_m.h"
+#include "arm_adi_v5.h"
 #include "arm_semihosting.h"
 #include "target_request.h"
 #include <rtt/rtt.h>
index b2af39cede7032b89b937eb9ed9f53e819c941c6..9583ad767edc897fa22dc569877f587f3195880f 100644 (file)
@@ -20,7 +20,7 @@
 #include "mips64.h"
 #include "mips64_pracc.h"
 
-#include "time_support.h"
+#include <helper/time_support.h>
 
 #define STACK_DEPTH    32
 
index 7a5e990ca5735f376b3cbadc39f8c36ab7aa54b4..86a95f63507caf40a01d682f784a51f4c86e72f2 100644 (file)
@@ -16,7 +16,7 @@
 #include "target/target.h"
 #include "target/algorithm.h"
 #include "target/target_type.h"
-#include "log.h"
+#include <helper/log.h>
 #include "jtag/jtag.h"
 #include "target/register.h"
 #include "target/breakpoints.h"
index 24fb79ccf0ec0fc7ca6c1cc3069bf2602145e92c..fdebdd413d9ff0b00960c9a8af210042476e69b2 100644 (file)
@@ -16,7 +16,7 @@
 #include "target/target.h"
 #include "target/algorithm.h"
 #include "target/target_type.h"
-#include "log.h"
+#include <helper/log.h>
 #include "jtag/jtag.h"
 #include "target/register.h"
 #include "target/breakpoints.h"
index 8f1f398b3ea708b8319e1a3c1e06f2224a4a75c3..07fb95550c99cf379753e4b3c37be67f34755425 100644 (file)
@@ -8,14 +8,14 @@
 #include "config.h"
 #endif
 
+#include <helper/log.h>
+#include <helper/time_support.h>
 #include "target/target.h"
 #include "target/algorithm.h"
 #include "target/target_type.h"
-#include "log.h"
 #include "jtag/jtag.h"
 #include "target/register.h"
 #include "target/breakpoints.h"
-#include "helper/time_support.h"
 #include "riscv.h"
 #include "gdb_regs.h"
 #include "rtos/rtos.h"
@@ -1870,10 +1870,10 @@ static int riscv_checksum_memory(struct target *target,
        LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
 
        static const uint8_t riscv32_crc_code[] = {
-#include "../../contrib/loaders/checksum/riscv32_crc.inc"
+#include "contrib/loaders/checksum/riscv32_crc.inc"
        };
        static const uint8_t riscv64_crc_code[] = {
-#include "../../contrib/loaders/checksum/riscv64_crc.inc"
+#include "contrib/loaders/checksum/riscv64_crc.inc"
        };
 
        static const uint8_t *crc_code;
index 90b8ddb4fcb8ac107ebcb0cd244beef2f5aaf7f8..0072b9afe7fbd5fcb6215bd3c2303eeb6fdd7c4e 100644 (file)
@@ -41,7 +41,7 @@
 #include "config.h"
 #endif
 
-#include "log.h"
+#include <helper/log.h>
 
 #include "target/target.h"
 #include "target/semihosting_common.h"
index 6571e9c6fd05244f9f8e8184015865e3263735ec..35e9b533291acdf6a8ed8518857e2ad2cca5a8b7 100644 (file)
@@ -717,6 +717,15 @@ static int no_mmu(struct target *target, int *enabled)
        return ERROR_OK;
 }
 
+/**
+ * Reset the @c examined flag for the given target.
+ * Pure paranoia -- targets are zeroed on allocation.
+ */
+static inline void target_reset_examined(struct target *target)
+{
+       target->examined = false;
+}
+
 static int default_examine(struct target *target)
 {
        target_set_examined(target);
@@ -737,10 +746,12 @@ int target_examine_one(struct target *target)
 
        int retval = target->type->examine(target);
        if (retval != ERROR_OK) {
+               target_reset_examined(target);
                target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_FAIL);
                return retval;
        }
 
+       target_set_examined(target);
        target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_END);
 
        return ERROR_OK;
@@ -1522,15 +1533,6 @@ static int target_profiling(struct target *target, uint32_t *samples,
                        num_samples, seconds);
 }
 
-/**
- * Reset the @c examined flag for the given target.
- * Pure paranoia -- targets are zeroed on allocation.
- */
-static void target_reset_examined(struct target *target)
-{
-       target->examined = false;
-}
-
 static int handle_target(void *priv);
 
 static int target_init_one(struct command_context *cmd_ctx,
@@ -3055,7 +3057,7 @@ static int handle_target(void *priv)
                                /* Target examination could have failed due to unstable connection,
                                 * but we set the examined flag anyway to repoll it later */
                                if (retval != ERROR_OK) {
-                                       target->examined = true;
+                                       target_set_examined(target);
                                        LOG_USER("Examination failed, GDB will be halted. Polling again in %dms",
                                                 target->backoff.times * polling_interval);
                                        return retval;
@@ -4983,7 +4985,7 @@ no_params:
                                if (goi->isconfigure) {
                                        /* START_DEPRECATED_TPIU */
                                        if (n->value == TARGET_EVENT_TRACE_CONFIG)
-                                               LOG_INFO("DEPRECATED target event %s", n->name);
+                                               LOG_INFO("DEPRECATED target event %s; use TPIU events {pre,post}-{enable,disable}", n->name);
                                        /* END_DEPRECATED_TPIU */
 
                                        bool replace = true;
@@ -5308,8 +5310,13 @@ static int jim_target_examine(Jim_Interp *interp, int argc, Jim_Obj *const *argv
        }
 
        int e = target->type->examine(target);
-       if (e != ERROR_OK)
+       if (e != ERROR_OK) {
+               target_reset_examined(target);
                return JIM_ERR;
+       }
+
+       target_set_examined(target);
+
        return JIM_OK;
 }
 
@@ -5715,7 +5722,7 @@ static int target_create(struct jim_getopt_info *goi)
        /* COMMAND */
        jim_getopt_obj(goi, &new_cmd);
        /* does this command exist? */
-       cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_ERRMSG);
+       cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_NONE);
        if (cmd) {
                cp = Jim_GetString(new_cmd, NULL);
                Jim_SetResultFormatted(goi->interp, "Command/target: %s Exists", cp);
index cf30cf8cc69e88b72f6f30fda4baa6a5afd9b884..d6b6086b3c59467305a9db5ae444f71402c1f9f2 100644 (file)
@@ -25,7 +25,7 @@
 #ifndef OPENOCD_TARGET_TARGET_TYPE_H
 #define OPENOCD_TARGET_TARGET_TYPE_H
 
-#include <jim-nvp.h>
+#include <helper/jim-nvp.h>
 
 struct target;
 
index edb3fb32b424461ccaaff8411f2eeae6b66a73b7..fafe9bcbacdc8a15b7a163974c270fe17f23e9c5 100644 (file)
@@ -151,7 +151,7 @@ proc stm32wlx_get_chipname {} {
        if {$sep == -1} {
                return $t
        }
-       return [string range $t 0 [expr $sep - 1]]
+       return [string range $t 0 [expr {$sep - 1}]]
 }
 
 # like mrw, but with target selection

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