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aarch64: implement mmu on/off for aarch32 74/4374/4
authorMatthias Welwarsky <matthias.welwarsky@sysgo.com>
Mon, 22 Jan 2018 11:28:37 +0000 (12:28 +0100)
committerMatthias Welwarsky <matthias@welwarsky.de>
Fri, 26 Jan 2018 10:53:09 +0000 (10:53 +0000)
add decoding of aarch32 core modes (register layout is compatible)

Change-Id: I34c3146a7b1f836d3006be2b76b036da055b3d3e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4374
Tested-by: jenkins
Reviewed-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
src/target/aarch64.c patch | blob | history

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 784274a0e5913415612c3c8f3913add4db38e405..bcfce659244af6ca099623c1a8dc277e3f1d7877 100644 (file)
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -161,8 +161,16 @@ static int aarch64_mmu_modify(struct target *target, int enable)
        case ARMV8_64_EL3T:
                instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
                break;
        case ARMV8_64_EL3T:
                instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
                break;
+
+       case ARM_MODE_SVC:
+       case ARM_MODE_ABT:
+       case ARM_MODE_FIQ:
+       case ARM_MODE_IRQ:
+               instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
+               break;
+
        default:
        default:
-               LOG_DEBUG("unknown cpu state 0x%x" PRIx32, armv8->arm.core_state);
+               LOG_DEBUG("unknown cpu state 0x%" PRIx32, armv8->arm.core_mode);
                break;
        }
 
                break;
        }
 
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