target/armv8_opcodes: use T32 instructions when the PE is in AArch32 state

As stated in ARM v8-A Architecture Reference Manual (ARM DDI 0487E.a)
in Chapter H4.3 DCC and ITR access modes:
    Writes to EDITR trigger the instruction to be executed if the PE
    is in Debug state:
      - If the PE is in AArch64 state, this is an A64 instruction.
      - If the PE is in AArch32 state, this is a T32 instruction

But in armv8_opcodes specifically in t32_opcodes we were using some
A32 instructions for HLT, LDRx and STRx opcodes.

Using the correct LDRx and STRx opcodes, fixes 16 and 8 bits memory access
when the PE is in AArch32 state.

Change-Id: Ib1acbdd4966297e7b069569bcb8deea3c3993615
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5346
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/src/target/armv8_opcodes.c b/src/target/armv8_opcodes.c
index 6887b295399da30c841f72df7ab92ede0c3d61ee..96db728717ba37d8f55cd278c30bd882c8f311df 100644 (file)
--- a/src/target/armv8_opcodes.c
+++ b/src/target/armv8_opcodes.c
@@ -68,13 +68,13 @@ static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
                [ARMV8_OPC_DCCISW]      = ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
                [ARMV8_OPC_DCCIVAC]     = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
                [ARMV8_OPC_ICIVAU]      = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
-               [ARMV8_OPC_HLT]         = ARMV8_HLT_A1(11),
-               [ARMV8_OPC_LDRB_IP]     = ARMV4_5_LDRB_IP(1, 0),
-               [ARMV8_OPC_LDRH_IP]     = ARMV4_5_LDRH_IP(1, 0),
-               [ARMV8_OPC_LDRW_IP]     = ARMV4_5_LDRW_IP(1, 0),
-               [ARMV8_OPC_STRB_IP]     = ARMV4_5_STRB_IP(1, 0),
-               [ARMV8_OPC_STRH_IP]     = ARMV4_5_STRH_IP(1, 0),
-               [ARMV8_OPC_STRW_IP]     = ARMV4_5_STRW_IP(1, 0),
+               [ARMV8_OPC_HLT]         = ARMV8_HLT_T1(11),
+               [ARMV8_OPC_LDRB_IP]     = ARMV8_LDRB_IP_T3(1, 0),
+               [ARMV8_OPC_LDRH_IP]     = ARMV8_LDRH_IP_T3(1, 0),
+               [ARMV8_OPC_LDRW_IP]     = ARMV8_LDRW_IP_T3(1, 0),
+               [ARMV8_OPC_STRB_IP]     = ARMV8_STRB_IP_T3(1, 0),
+               [ARMV8_OPC_STRH_IP]     = ARMV8_STRH_IP_T3(1, 0),
+               [ARMV8_OPC_STRW_IP]     = ARMV8_STRW_IP_T3(1, 0),
 };
 
 void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)

diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index 217cc64c6ce21e1512dd401b60d3f27e50009a18..239c4c5f1807d3cd65977bb1e3cee5f9d92595e7 100644 (file)
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -164,10 +164,18 @@
 #define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd)
 #define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd)
 
+#define ARMV8_LDRB_IP_T3(Rd, Rn) (0xf8100b01 | (Rn << 16) | (Rd << 12))
+#define ARMV8_LDRH_IP_T3(Rd, Rn) (0xf8300b02 | (Rn << 16) | (Rd << 12))
+#define ARMV8_LDRW_IP_T3(Rd, Rn) (0xf8500b04 | (Rn << 16) | (Rd << 12))
+
 #define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd)
 #define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
 #define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
 
+#define ARMV8_STRB_IP_T3(Rd, Rn) (0xf8000b01 | (Rn << 16) | (Rd << 12))
+#define ARMV8_STRH_IP_T3(Rd, Rn) (0xf8200b02 | (Rn << 16) | (Rd << 12))
+#define ARMV8_STRW_IP_T3(Rd, Rn) (0xf8400b04 | (Rn << 16) | (Rd << 12))
+
 #define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd)
 #define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd)