u8500 : config for L2 cache

diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index f6e2091fa5a4e7f7f3c55336b956db34096f0b93..073e01fa480abeded9ef386c52df3137e51b1afa 100644 (file)
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -131,7 +131,9 @@ proc enable_apetap {} {
        set status [$_TARGETNAME_1 curstate]
     if {[string equal "unknown" $status]} {
        $_TARGETNAME_1 arp_examine
+       cache_config l2x 0xa0412000 8
        }
+
        set status [$_TARGETNAME_2 curstate]
     if {[string equal "unknown" $status]} {
        $_TARGETNAME_2 arp_examine
@@ -234,6 +236,9 @@ if { $_SMP == 1} {
 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
 }
 
+
+
+
 proc secsts1 { } {
        global _CHIPNAME
         irscan $_CHIPNAME.jrc 0x3a
@@ -265,6 +270,7 @@ proc att { } {
        } else {
                echo "target secured"
        }
+       
 }