Code Review / openocd.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | patch | inline | side by side (parent: f88a7dd)
bluenrg: add support for bluenrg-lps device and board 28/6928/2
authorSalvatore Giorgio PECORINO <salvatore-giorgio.pecorino@st.com>
Tue, 12 Apr 2022 16:15:42 +0000 (18:15 +0200)
committerAntonio Borneo <borneo.antonio@gmail.com>
Sat, 7 May 2022 11:03:25 +0000 (11:03 +0000)
Added bluenrg-lps support
Added file for the board steval-idb012v1
Fixed size_info information using a mask
Changed the if condition in bluenrg-x.cfg to be valid only for bluenrg-1 and bluenrg-2

Signed-off-by: Salvatore Giorgio PECORINO <salvatore-giorgio.pecorino@st.com>
Change-Id: Ic0777ec0811ee6fac7d5e1d065c4629e47d84a1f
Reviewed-on: https://review.openocd.org/c/openocd/+/6928
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
doc/openocd.texi patch | blob | history
src/flash/nor/bluenrg-x.c patch | blob | history
tcl/board/steval-idb012v1.cfg [new file with mode: 0644] patch | blob
tcl/target/bluenrg-x.cfg patch | blob | history

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 07d4ad70acbe33230a609a90365aacac90482119..8bf0a31f76121a2611d57480e807e0c64b16be88 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6418,7 +6418,7 @@ The AVR 8-bit microcontrollers from Atmel integrate flash memory.
 @end deffn
 
 @deffn {Flash Driver} {bluenrg-x}
 @end deffn
 
 @deffn {Flash Driver} {bluenrg-x}
-STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
+STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP/LPS Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
 The driver automatically recognizes these chips using
 the chip identification registers, and autoconfigures itself.
 
 The driver automatically recognizes these chips using
 the chip identification registers, and autoconfigures itself.
 
diff --git a/src/flash/nor/bluenrg-x.c b/src/flash/nor/bluenrg-x.c
index 60eccefaf04baeb3326d508919b2fe2d7426b385..16075ec4c17b7fd9fc93ff2500ac86e9ab8ce698 100644 (file)
--- a/src/flash/nor/bluenrg-x.c
+++ b/src/flash/nor/bluenrg-x.c
@@ -35,6 +35,8 @@
 #define JTAG_IDCODE_REG(bluenrgx_info)      (bluenrgx_info->flash_ptr->jtag_idcode_reg)
 #define FLASH_PAGE_SIZE(bluenrgx_info)      (bluenrgx_info->flash_ptr->flash_page_size)
 
 #define JTAG_IDCODE_REG(bluenrgx_info)      (bluenrgx_info->flash_ptr->jtag_idcode_reg)
 #define FLASH_PAGE_SIZE(bluenrgx_info)      (bluenrgx_info->flash_ptr->flash_page_size)
 
+#define FLASH_SIZE_REG_MASK (0xFFFF)
+
 struct flash_ctrl_priv_data {
        uint32_t die_id_reg;
        uint32_t jtag_idcode_reg;
 struct flash_ctrl_priv_data {
        uint32_t die_id_reg;
        uint32_t jtag_idcode_reg;
@@ -75,6 +77,16 @@ static const struct flash_ctrl_priv_data flash_priv_data_lp = {
        .part_name = "BLUENRG-LP",
 };
 
        .part_name = "BLUENRG-LP",
 };
 
+static const struct flash_ctrl_priv_data flash_priv_data_lps = {
+       .die_id_reg = 0x40000000,
+       .jtag_idcode_reg = 0x40000004,
+       .flash_base = 0x10040000,
+       .flash_regs_base = 0x40001000,
+       .flash_page_size = 2048,
+       .jtag_idcode = 0x02028041,
+       .part_name = "BLUENRG-LPS",
+};
+
 struct bluenrgx_flash_bank {
        bool probed;
        uint32_t die_id;
 struct bluenrgx_flash_bank {
        bool probed;
        uint32_t die_id;
@@ -84,8 +96,8 @@ struct bluenrgx_flash_bank {
 static const struct flash_ctrl_priv_data *flash_ctrl[] = {
        &flash_priv_data_1,
        &flash_priv_data_2,
 static const struct flash_ctrl_priv_data *flash_ctrl[] = {
        &flash_priv_data_1,
        &flash_priv_data_2,
-       &flash_priv_data_lp
-};
+       &flash_priv_data_lp,
+       &flash_priv_data_lps};
 
 /* flash_bank bluenrg-x 0 0 0 0 <target#> */
 FLASH_BANK_COMMAND_HANDLER(bluenrgx_flash_bank_command)
 
 /* flash_bank bluenrg-x 0 0 0 0 <target#> */
 FLASH_BANK_COMMAND_HANDLER(bluenrgx_flash_bank_command)
@@ -377,7 +389,7 @@ static int bluenrgx_probe(struct flash_bank *bank)
        if (retval != ERROR_OK)
                return retval;
 
        if (retval != ERROR_OK)
                return retval;
 
-       if (idcode != flash_priv_data_lp.jtag_idcode) {
+       if ((idcode != flash_priv_data_lp.jtag_idcode) && (idcode != flash_priv_data_lps.jtag_idcode)) {
                retval = target_read_u32(bank->target, BLUENRG2_JTAG_REG, &idcode);
                if (retval != ERROR_OK)
                        return retval;
                retval = target_read_u32(bank->target, BLUENRG2_JTAG_REG, &idcode);
                if (retval != ERROR_OK)
                        return retval;
@@ -395,6 +407,7 @@ static int bluenrgx_probe(struct flash_bank *bank)
                }
        }
        retval = bluenrgx_read_flash_reg(bank, FLASH_SIZE_REG, &size_info);
                }
        }
        retval = bluenrgx_read_flash_reg(bank, FLASH_SIZE_REG, &size_info);
+       size_info = size_info & FLASH_SIZE_REG_MASK;
        if (retval != ERROR_OK)
                return retval;
 
        if (retval != ERROR_OK)
                return retval;
 
diff --git a/tcl/board/steval-idb012v1.cfg b/tcl/board/steval-idb012v1.cfg
new file mode 100644 (file)
index 0000000..25efc58
--- /dev/null
+++ b/tcl/board/steval-idb012v1.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later.
+# This is an evaluation board with a single BlueNRG-LPS chip.
+set CHIPNAME bluenrg-lps
+source [find interface/cmsis-dap.cfg]
+source [find target/bluenrg-x.cfg]
\ No newline at end of file
diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg
index ea94be9628779608a78c83b98a7836d4019718ce..1eba37616ee17dcee4adbc635b27f1ce9a980e50 100644 (file)
--- a/tcl/target/bluenrg-x.cfg
+++ b/tcl/target/bluenrg-x.cfg
@@ -47,11 +47,14 @@ if {![using_hla]} {
    cortex_m reset_config sysresetreq
 }
 
    cortex_m reset_config sysresetreq
 }
 
+set JTAG_IDCODE_B2 0x0200A041
+set JTAG_IDCODE_B1 0x0
+
 $_TARGETNAME configure -event halted {
     global WDOG_VALUE
     global WDOG_VALUE_SET
     set _JTAG_IDCODE [mrw 0x40000004]
 $_TARGETNAME configure -event halted {
     global WDOG_VALUE
     global WDOG_VALUE_SET
     set _JTAG_IDCODE [mrw 0x40000004]
-    if {$_JTAG_IDCODE != 0x0201E041} {
+    if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
         # Stop watchdog during halt, if enabled. Only Bluenrg-1/2
         set WDOG_VALUE [mrw 0x40700008]
         if [expr {$WDOG_VALUE & (1 << 1)}] {
         # Stop watchdog during halt, if enabled. Only Bluenrg-1/2
         set WDOG_VALUE [mrw 0x40700008]
         if [expr {$WDOG_VALUE & (1 << 1)}] {
@@ -64,7 +67,7 @@ $_TARGETNAME configure -event resumed {
     global WDOG_VALUE
     global WDOG_VALUE_SET
     set _JTAG_IDCODE [mrw 0x40000004]
     global WDOG_VALUE
     global WDOG_VALUE_SET
     set _JTAG_IDCODE [mrw 0x40000004]
-    if {$_JTAG_IDCODE != 0x0201E041} {
+    if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
         if {$WDOG_VALUE_SET} {
             # Restore watchdog enable value after resume. Only Bluenrg-1/2
             mww 0x40700008 $WDOG_VALUE
         if {$WDOG_VALUE_SET} {
             # Restore watchdog enable value after resume. Only Bluenrg-1/2
             mww 0x40700008 $WDOG_VALUE
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)