return None if (len(raw) < 2) else strToHex(raw[1])
def readMemory(self, wordLen, address, n):
- self.send("array unset output") # better to clear the array before
- self.send("mem2array output %d 0x%x %d" % (wordLen, address, n))
-
- output = [*map(int, self.send("return $output").split(" "))]
- d = dict([tuple(output[i:i + 2]) for i in range(0, len(output), 2)])
-
- return [d[k] for k in sorted(d.keys())]
+ output = self.send("read_memory 0x%x %d %d" % (address, wordLen, n))
+ return [*map(lambda x: int(x, 16), output.split(" "))]
def writeVariable(self, address, value):
assert value is not None
self.send("mww 0x%x 0x%x" % (address, value))
- def writeMemory(self, wordLen, address, n, data):
- array = " ".join(["%d 0x%x" % (a, b) for a, b in enumerate(data)])
-
- self.send("array unset 1986ве1т") # better to clear the array before
- self.send("array set 1986ве1т { %s }" % array)
- self.send("array2mem 1986ве1т 0x%x %s %d" % (wordLen, address, n))
+ def writeMemory(self, wordLen, address, data):
+ data = "{" + ' '.join(['0x%x' % x for x in data]) + "}"
+ self.send("write_memory 0x%x %d %s" % (address, wordLen, data))
if __name__ == "__main__":
}
proc peek32 {address} {
- mem2array t 32 $address 1
- return $t(0)
+ return [read_memory $address 32 1]
}
# Wait for an expression to be true with a timeout
at91sam9 ce 0 0xfffff800 14
proc read_register {register} {
- set result ""
- mem2array result 32 $register 1
- return $result(0)
+ return [read_memory $register 32 1]
}
proc at91sam9g20_reset_start { } {
# Helper
#
proc read_register {register} {
- set result ""
- mem2array result 32 $register 1
- return $result(0)
+ return [read_memory $register 32 1]
}
proc init_board {} {
}
proc mread32 {addr} {
- set value(0) 0
- mem2array value 32 $addr 1
- return $value(0)
+ return [read_memory $addr 32 1]
}
proc init_clocks { } {
proc read_register {register} {
- set result ""
- mem2array result 32 $register 1
- return $result(0)
+ return [read_memory $register 32 1]
}
proc at91sam9g45_start { } {
proc show_AIC { } {
global AIC_SMR
- if [catch { mem2array aaa 32 $AIC_SMR [expr {32 * 4}] } msg ] {
+ if [catch { set aaa [read_memory $AIC_SMR 32 [expr {32 * 4}]] } msg ] {
error [format "%s (%s)" $msg AIC_SMR]
}
echo "AIC_SMR: Mode & Type"
global AT91C_ID
for { set x 0 } { $x < 32 } { } {
echo -n " "
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+ echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
incr x
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+ echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
incr x
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+ echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
incr x
- echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
+ echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) [lindex $aaa $x]]
incr x
}
global AIC_SVR
- if [catch { mem2array aaa 32 $AIC_SVR [expr {32 * 4}] } msg ] {
+ if [catch { set aaa [read_memory $AIC_SVR 32 [expr {32 * 4}]] } msg ] {
error [format "%s (%s)" $msg AIC_SVR]
}
echo "AIC_SVR: Vectors"
for { set x 0 } { $x < 32 } { } {
echo -n " "
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+ echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
incr x
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+ echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
incr x
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
+ echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]]
incr x
- echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
+ echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) [lindex $aaa $x]]
incr x
}
# vector located at the interrupt vector base address, which is the first
# entry (offset 0x00) in the vector table.
set int_vector_base [arc jtag get-aux-reg 0x25]
- set start_pc ""
- mem2array start_pc 32 $int_vector_base 1
- arc jtag set-aux-reg 0x6 $start_pc(0)
+ set start_pc [read_memory $int_vector_base 32 1]
+ arc jtag set-aux-reg 0x6 $start_pc
# It is OK to do uncached writes - register cache will be invalidated by
# the reset_assert() function.
# mrw: "memory read word", returns value of $reg
proc mrw {reg} {
- set value ""
- mem2array value 32 $reg 1
- return $value(0)
+ return [read_memory $reg 32 1]
}
add_usage_text mrw "address"
# mrh: "memory read halfword", returns value of $reg
proc mrh {reg} {
- set value ""
- mem2array value 16 $reg 1
- return $value(0)
+ return [read_memory $reg 16 1]
}
add_usage_text mrh "address"
# mrb: "memory read byte", returns value of $reg
proc mrb {reg} {
- set value ""
- mem2array value 8 $reg 1
- return $value(0)
+ return [read_memory $reg 8 1]
}
add_usage_text mrb "address"
}
proc memread32 {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 32 $ADDR 1 } msg ] {
- return $foo(0)
+ if ![ catch { set foo [read_memory $ADDR 32 1] } msg ] {
+ return $foo
} else {
error "memread32: $msg"
}
}
proc memread16 {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 16 $ADDR 1 } msg ] {
- return $foo(0)
+ if ![ catch { set foo [read_memory $ADDR 16 1] } msg ] {
+ return $foo
} else {
error "memread16: $msg"
}
}
proc memread8 {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 8 $ADDR 1 } msg ] {
- return $foo(0)
+ if ![ catch { set foo [read_memory $ADDR 8 1] } msg ] {
+ return $foo
} else {
error "memread8: $msg"
}
}
proc memwrite32 {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 32 $ADDR 1 } msg ] {
- return $foo(0)
+ if ![ catch { write_memory $ADDR 32 $DATA } msg ] {
+ return $DATA
} else {
error "memwrite32: $msg"
}
}
proc memwrite16 {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 16 $ADDR 1 } msg ] {
- return $foo(0)
+ if ![ catch { write_memory $ADDR 16 $DATA } msg ] {
+ return $DATA
} else {
error "memwrite16: $msg"
}
}
proc memwrite8 {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 8 $ADDR 1 } msg ] {
- return $foo(0)
+ if ![ catch { write_memory $ADDR 8 $DATA } msg ] {
+ return $DATA
} else {
error "memwrite8: $msg"
}
}
proc memread32_phys {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 32 $ADDR 1 phys } msg ] {
- return $foo(0)
+ if ![ catch { set foo [read_memory $ADDR 32 1 phys] } msg ] {
+ return $foo
} else {
error "memread32: $msg"
}
}
proc memread16_phys {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 16 $ADDR 1 phys } msg ] {
- return $foo(0)
+ if ![ catch { set foo [read_memory $ADDR 16 1 phys] } msg ] {
+ return $foo
} else {
error "memread16: $msg"
}
}
proc memread8_phys {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 8 $ADDR 1 phys } msg ] {
- return $foo(0)
+ if ![ catch { set foo [read_memory $ADDR 8 1 phys] } msg ] {
+ return $foo
} else {
error "memread8: $msg"
}
}
proc memwrite32_phys {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 32 $ADDR 1 phys } msg ] {
- return $foo(0)
+ if ![ catch { write_memory $ADDR 32 $DATA phys } msg ] {
+ return $DATA
} else {
error "memwrite32: $msg"
}
}
proc memwrite16_phys {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 16 $ADDR 1 phys } msg ] {
- return $foo(0)
+ if ![ catch { write_memory $ADDR 16 $DATA phys } msg ] {
+ return $DATA
} else {
error "memwrite16: $msg"
}
}
proc memwrite8_phys {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 8 $ADDR 1 phys } msg ] {
- return $foo(0)
+ if ![ catch { write_memory $ADDR 8 $DATA phys } msg ] {
+ return $DATA
} else {
error "memwrite8: $msg"
}
# read a 64-bit register (memory mapped)
proc mr64bit {reg} {
- set value ""
- mem2array value 32 $reg 2
- return $value
+ return [read_memory $reg 32 2]
}
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
- mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
+ set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1]
# see if the PLL is in bypass mode
- set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}]
+ set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
- set x [expr {($value(0) & 0x0001F0000) >> 16}]
+ set x [expr {($value & 0x0001F0000) >> 16}]
echo [format "x: %d" $x]
- set y [expr {($value(0) & 0x00000007F)}]
+ set y [expr {($value & 0x00000007F)}]
echo [format "y: %d" $y]
- set w [expr {($value(0) & 0x000000300) >> 8}]
+ set w [expr {($value & 0x000000300) >> 8}]
echo [format "w: %d" $w]
echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
}
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
- mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
+ set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1]
# see if the PLL is in bypass mode
- set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}]
+ set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
- set x [expr {($value(0) & 0x0001F0000) >> 16}]
+ set x [expr {($value & 0x0001F0000) >> 16}]
echo [format "x: %d" $x]
- set y [expr {($value(0) & 0x00000007F)}]
+ set y [expr {($value & 0x00000007F)}]
echo [format "y: %d" $y]
- set w [expr {($value(0) & 0x000000300) >> 8}]
+ set w [expr {($value & 0x000000300) >> 8}]
echo [format "w: %d" $w]
echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
}
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
proc mread32 {addr} {
- set value(0) 0
- mem2array value 32 $addr 1
- return $value(0)
+ return [read_memory $addr 32 1]
}
# This function must be called on netX100/500 right after halt
}
proc psoc4_get_family_id {} {
- set err [catch "mem2array romtable_pid 32 0xF0000FE0 3"]
+ set err [catch {set romtable_pid [read_memory 0xF0000FE0 32 3]}]
if { $err } {
return 0
}
- if { [expr {$romtable_pid(0) & 0xffffff00 }]
- || [expr {$romtable_pid(1) & 0xffffff00 }]
- || [expr {$romtable_pid(2) & 0xffffff00 }] } {
+ if { [expr {[lindex $romtable_pid 0] & 0xffffff00 }]
+ || [expr {[lindex $romtable_pid 1] & 0xffffff00 }]
+ || [expr {[lindex $romtable_pid 2] & 0xffffff00 }] } {
echo "Unexpected data in ROMTABLE"
return 0
}
- set designer_id [expr {(( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) }]
+ set designer_id [expr {(( [lindex $romtable_pid 1] & 0xf0 ) >> 4) | (( [lindex $romtable_pid 2] & 0xf ) << 4 ) }]
if { $designer_id != 0xb4 } {
echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id]
return 0
}
- set family_id [expr {( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) }]
+ set family_id [expr {( [lindex $romtable_pid 0] & 0xff ) | (( [lindex $romtable_pid 1] & 0xf ) << 8 ) }]
return $family_id
}
}
# Set registers to reset vector values
- mem2array value 32 0 2
- reg pc [expr {$value(1) & 0xfffffffe} ]
- reg msp $value(0)
+ set value [read_memory 0x0 32 2]
+ reg pc [expr {[lindex $value 1] & 0xfffffffe}]
+ reg msp [lindex $value 0]
if { $PSOC4_TEST_MODE_WORKAROUND } {
catch { mww $TEST_MODE 0 }
# like mrw, but with target selection
proc stm32h7x_mrw {used_target reg} {
- set value ""
- $used_target mem2array value 32 $reg 1
- return $value(0)
+ return [$used_target read_memory $reg 32 1]
}
# like mmw, but with target selection
}
proc detect_cpu1 {} {
- $::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
- set dual_core [expr {$cpu1_prsr(0) & 1}]
+ set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
+ set dual_core [expr {$cpu1_prsr & 1}]
if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
}
# like mrw, but with target selection
proc stm32wlx_mrw {used_target reg} {
- set value ""
- $used_target mem2array value 32 $reg 1
- return $value(0)
+ return [$used_target read_memory $reg 32 1]
}
# like mmw, but with target selection
soft_reset_halt
# Initialize MSP, PSP, and PC from vector table at flash 0x01000800
- mem2array boot 32 0x01000800 2
+ set boot [read_memory 0x01000800 32 2]
- reg msp $boot(0)
- reg psp $boot(0)
- reg pc $boot(1)
+ reg msp [lindex $boot 0]
+ reg psp [lindex $boot 0]
+ reg pc [lindex $boot 1]
if { 0 == [string compare $MODE run ] } {
resume
echo "# code to trigger $name vector"
set addr 0x20000000
- # array2mem should be faster, though we'd need to
+ # write_memory should be faster, though we'd need to
# compute the resulting $addr ourselves
foreach opcode $halfwords {
mwh $addr $opcode
Code Review / openocd.git / commitdiff