This should allow users to configure flash at >32-bit addresses.
Change-Id: I7c9d3c5762579011a2d9708e5317e5765349845c
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4919
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
}
snprintf(buf, buf_size,
- "%s bank %d: %d kB at 0x%08" PRIx32,
+ "%s bank %d: %d kB at " TARGET_ADDR_FMT,
pPrivate->pChip->details.name,
pPrivate->bank_number,
k,
for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
bank->size = pPrivate->pChip->details.bank[x].size_bytes;
- LOG_DEBUG("SAM4 Set flash bank to %08X - %08X, idx %d", bank->base, bank->base + bank->size, x);
+ LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
+ TARGET_ADDR_FMT ", idx %d", bank->base,
+ bank->base + bank->size, x);
break;
}
}
FLASH_BANK_COMMAND_HANDLER(sam4l_flash_bank_command)
{
if (bank->base != SAM4L_FLASH) {
- LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
+ LOG_ERROR("Address " TARGET_ADDR_FMT
+ " invalid bank address (try 0x%08" PRIx32
"[at91sam4l series] )",
bank->base, SAM4L_FLASH);
return ERROR_FAIL;
FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
{
if (bank->base != SAMD_FLASH) {
- LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
+ LOG_ERROR("Address " TARGET_ADDR_FMT
+ " invalid bank address (try 0x%08" PRIx32
"[at91samd series] )",
bank->base, SAMD_FLASH);
return ERROR_FAIL;
ath79_info->io_base = target_device->io_base;
- LOG_DEBUG("Found device %s at address 0x%" PRIx32,
+ LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
retval = read_flash_id(bank, &id);
FLASH_BANK_COMMAND_HANDLER(same5_flash_bank_command)
{
if (bank->base != SAMD_FLASH) {
- LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
- "[same5] )",
- bank->base, SAMD_FLASH);
+ LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try "
+ "0x%08" PRIx32 "[same5] )", bank->base, SAMD_FLASH);
return ERROR_FAIL;
}
/* Stack pointer for program working area */
buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_sp->address);
- LOG_DEBUG("source->address = %08" TARGET_PRIxADDR, source->address);
- LOG_DEBUG("source->address+ source->size = %08" TARGET_PRIxADDR, source->address+source->size);
- LOG_DEBUG("write_algorithm_sp->address = %08" TARGET_PRIxADDR, write_algorithm_sp->address);
+ LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
+ LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
+ LOG_DEBUG("write_algorithm_sp->address = " TARGET_ADDR_FMT, write_algorithm_sp->address);
LOG_DEBUG("address = %08x", address+pre_size);
LOG_DEBUG("count = %08x", count);
if (retval != ERROR_OK)
return retval;
- LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
- PRIx32, i, bank->base);
+ LOG_ERROR("couldn't erase block %i of flash bank at base "
+ TARGET_ADDR_FMT, i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
if (retval != ERROR_OK)
return retval;
- LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
- PRIx32, i, bank->base);
+ LOG_ERROR("couldn't erase block %i of flash bank at base "
+ TARGET_ADDR_FMT, i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
if (retval != ERROR_OK)
return retval;
- LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address 0x%" PRIx32,
- bank->base, address);
+ LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
+ ", address 0x%" PRIx32,
+ bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
/* Check for valid range */
if (address & buffermask) {
- LOG_ERROR("Write address at base 0x%" PRIx32 ", address 0x%" PRIx32
- " not aligned to 2^%d boundary",
- bank->base, address, cfi_info->max_buf_write_size);
+ LOG_ERROR("Write address at base " TARGET_ADDR_FMT ", address 0x%"
+ PRIx32 " not aligned to 2^%d boundary",
+ bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
}
return retval;
LOG_ERROR(
- "couldn't start buffer write operation at base 0x%" PRIx32 ", address 0x%" PRIx32,
+ "couldn't start buffer write operation at base " TARGET_ADDR_FMT
+ ", address 0x%" PRIx32,
bank->base,
address);
return ERROR_FLASH_OPERATION_FAILED;
if (retval != ERROR_OK)
return retval;
- LOG_ERROR("Buffer write at base 0x%" PRIx32
+ LOG_ERROR("Buffer write at base " TARGET_ADDR_FMT
", address 0x%" PRIx32 " failed.", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
if (retval != ERROR_OK)
return retval;
- LOG_ERROR("couldn't write word at base 0x%" PRIx32
+ LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
", address 0x%" PRIx32, bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
/* Check for valid range */
if (address & buffermask) {
- LOG_ERROR("Write address at base 0x%" PRIx32
+ LOG_ERROR("Write address at base " TARGET_ADDR_FMT
", address 0x%" PRIx32 " not aligned to 2^%d boundary",
bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
if (retval != ERROR_OK)
return retval;
- LOG_ERROR("couldn't write block at base 0x%" PRIx32
+ LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT
", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address,
bufferwsize);
return ERROR_FLASH_OPERATION_FAILED;
retval = bank->driver->write(bank, buffer, offset, count);
if (retval != ERROR_OK) {
LOG_ERROR(
- "error writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32,
+ "error writing to flash at address " TARGET_ADDR_FMT
+ " at offset 0x%8.8" PRIx32,
bank->base,
offset);
}
retval = bank->driver->read(bank, buffer, offset, count);
if (retval != ERROR_OK) {
LOG_ERROR(
- "error reading to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32,
+ "error reading to flash at address " TARGET_ADDR_FMT
+ " at offset 0x%8.8" PRIx32,
bank->base,
offset);
}
/* lookup flash bank by address, bank not found is success, but
* result_bank is set to NULL. */
int get_flash_bank_by_addr(struct target *target,
- uint32_t addr,
+ target_addr_t addr,
bool check,
struct flash_bank **result_bank)
{
}
*result_bank = NULL;
if (check) {
- LOG_ERROR("No flash at address 0x%08" PRIx32, addr);
+ LOG_ERROR("No flash at address " TARGET_ADDR_FMT, addr);
return ERROR_FAIL;
}
return ERROR_OK;
* warning about those additions.
*/
static int flash_iterate_address_range_inner(struct target *target,
- char *pad_reason, uint32_t addr, uint32_t length,
+ char *pad_reason, target_addr_t addr, uint32_t length,
bool iterate_protect_blocks,
int (*callback)(struct flash_bank *bank, int first, int last))
{
struct flash_bank *c;
struct flash_sector *block_array;
- uint32_t last_addr = addr + length; /* first address AFTER end */
+ target_addr_t last_addr = addr + length; /* first address AFTER end */
int first = -1;
int last = -1;
int i;
else if (addr < end && pad_reason) {
/* FIXME say how many bytes (e.g. 80 KB) */
LOG_WARNING("Adding extra %s range, "
- "%#8.8x to %#8.8x",
+ "%#8.8x to " TARGET_ADDR_FMT,
pad_reason,
(unsigned) f->offset,
- (unsigned) addr - 1);
+ addr - 1);
first = i;
} else
continue;
/* invalid start or end address? */
if (first == -1 || last == -1) {
- LOG_ERROR("address range 0x%8.8x .. 0x%8.8x "
- "is not sector-aligned",
- (unsigned) (c->base + addr),
- (unsigned) (c->base + last_addr - 1));
+ LOG_ERROR("address range " TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT
+ " is not sector-aligned",
+ c->base + addr,
+ c->base + last_addr - 1);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
* multiple chips.
*/
static int flash_iterate_address_range(struct target *target,
- char *pad_reason, uint32_t addr, uint32_t length,
+ char *pad_reason, target_addr_t addr, uint32_t length,
bool iterate_protect_blocks,
int (*callback)(struct flash_bank *bank, int first, int last))
{
}
int flash_erase_address_range(struct target *target,
- bool pad, uint32_t addr, uint32_t length)
+ bool pad, target_addr_t addr, uint32_t length)
{
return flash_iterate_address_range(target, pad ? "erase" : NULL,
addr, length, false, &flash_driver_erase);
return flash_driver_protect(bank, 0, first, last);
}
-int flash_unlock_address_range(struct target *target, uint32_t addr, uint32_t length)
+int flash_unlock_address_range(struct target *target, target_addr_t addr,
+ uint32_t length)
{
/* By default, pad to sector boundaries ... the real issue here
* is that our (only) caller *permanently* removes protection,
void *driver_priv; /**< Private driver storage pointer */
int bank_number; /**< The 'bank' (or chip number) of this instance. */
- uint32_t base; /**< The base address of this bank */
+ target_addr_t base; /**< The base address of this bank */
uint32_t size; /**< The size of this chip bank, in bytes */
int chip_width; /**< Width of the chip in bytes (1,2,4 bytes) */
* @returns ERROR_OK if successful; otherwise, an error code.
*/
int flash_erase_address_range(struct target *target,
- bool pad, uint32_t addr, uint32_t length);
+ bool pad, target_addr_t addr, uint32_t length);
-int flash_unlock_address_range(struct target *target, uint32_t addr,
+int flash_unlock_address_range(struct target *target, target_addr_t addr,
uint32_t length);
/**
* @param check return ERROR_OK and result_bank NULL if the bank does not exist
* @returns The struct flash_bank located at @a addr, or NULL.
*/
-int get_flash_bank_by_addr(struct target *target, uint32_t addr, bool check,
+int get_flash_bank_by_addr(struct target *target, target_addr_t addr, bool check,
struct flash_bank **result_bank);
/**
* Allocate and fill an array of sectors or protection blocks.
int temp;
COMMAND_PARSE_NUMBER(int, CMD_ARGV[6], temp);
fespi_info->ctrl_base = (uint32_t) temp;
- LOG_DEBUG("ASSUMING FESPI device at ctrl_base = 0x%" TARGET_PRIxADDR,
+ LOG_DEBUG("ASSUMING FESPI device at ctrl_base = " TARGET_ADDR_FMT,
fespi_info->ctrl_base);
}
int result = target_read_u32(target, fespi_info->ctrl_base + address, value);
if (result != ERROR_OK) {
- LOG_ERROR("fespi_read_reg() error at 0x%" TARGET_PRIxADDR,
+ LOG_ERROR("fespi_read_reg() error at " TARGET_ADDR_FMT,
fespi_info->ctrl_base + address);
return result;
}
int result = target_write_u32(target, fespi_info->ctrl_base + address, value);
if (result != ERROR_OK) {
- LOG_ERROR("fespi_write_reg() error writing 0x%x to 0x%" TARGET_PRIxADDR,
+ LOG_ERROR("fespi_write_reg() error writing 0x%x to " TARGET_ADDR_FMT,
value, fespi_info->ctrl_base + address);
return result;
}
data_buf);
free(data_buf);
if (retval != ERROR_OK) {
- LOG_ERROR("Failed to write data to 0x%" TARGET_PRIxADDR ": %d",
+ LOG_ERROR("Failed to write data to " TARGET_ADDR_FMT ": %d",
data_wa->address, retval);
goto exit;
}
algorithm_wa->address, algorithm_wa->address + 4,
10000, NULL);
if (retval != ERROR_OK) {
- LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d",
+ LOG_ERROR("Failed to execute algorithm at " TARGET_ADDR_FMT ": %d",
algorithm_wa->address, retval);
goto exit;
}
retval = target_write_buffer(target, algorithm_wa->address,
sizeof(algorithm_bin), algorithm_bin);
if (retval != ERROR_OK) {
- LOG_ERROR("Failed to write code to 0x%" TARGET_PRIxADDR ": %d",
+ LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
algorithm_wa->address, retval);
target_free_working_area(target, algorithm_wa);
algorithm_wa = NULL;
fespi_info->ctrl_base = target_device->ctrl_base;
- LOG_DEBUG("Valid FESPI on device %s at address 0x%" PRIx32,
+ LOG_DEBUG("Valid FESPI on device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
} else {
- LOG_DEBUG("Assuming FESPI as specified at address 0x%" TARGET_PRIxADDR
- " with ctrl at 0x%x", fespi_info->ctrl_base, bank->base);
+ LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
+ " with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
+ bank->base);
}
/* read and decode flash ID; returns in SW mode */
uint32_t halfwords = MIN(halfword_count, data_workarea->size / 2);
uint32_t addr = bank->base + offset;
- LOG_DEBUG("copying %" PRId32 " bytes to SRAM 0x%08" TARGET_PRIxADDR,
+ LOG_DEBUG("copying %" PRId32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(halfwords * 2, byte_count), data_workarea->address);
retval = target_write_buffer(target, data_workarea->address,
result = target_write_memory(bank->target, k_chip->progr_accel_ram,
4, size_aligned / 4, buffer_aligned);
- LOG_DEBUG("section @ %08" PRIx32 " aligned begin %" PRIu32 ", end %" PRIu32,
+ LOG_DEBUG("section @ " TARGET_ADDR_FMT " aligned begin %" PRIu32
+ ", end %" PRIu32,
bank->base + offset, align_begin, align_end);
} else
result = target_write_memory(bank->target, k_chip->progr_accel_ram,
4, size_aligned / 4, buffer);
- LOG_DEBUG("write section @ %08" PRIx32 " with length %" PRIu32 " bytes",
+ LOG_DEBUG("write section @ " TARGET_ADDR_FMT " with length %" PRIu32
+ " bytes",
bank->base + offset, size);
if (result != ERROR_OK) {
0, 0, 0, 0, &ftfx_fstat);
if (result != ERROR_OK) {
- LOG_ERROR("Error writing section at %08" PRIx32, bank->base + offset);
+ LOG_ERROR("Error writing section at " TARGET_ADDR_FMT,
+ bank->base + offset);
break;
}
if (ftfx_fstat & 0x01) {
- LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
+ LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
+ bank->base + offset);
if (k_bank->prog_base == 0 && offset == FCF_ADDRESS + FCF_SIZE
&& (k_chip->flash_support & FS_WIDTH_256BIT)) {
LOG_ERROR("Flash write immediately after the end of Flash Config Field shows error");
}
}
- LOG_DEBUG("flash write @ %08" PRIx32, bank->base + offset);
+ LOG_DEBUG("flash write @ " TARGET_ADDR_FMT, bank->base + offset);
if (fallback == 0) {
/* program section command */
0, 0, 0, 0, &ftfx_fstat);
if (result != ERROR_OK) {
- LOG_ERROR("Error writing longword at %08" PRIx32, bank->base + offset);
+ LOG_ERROR("Error writing longword at " TARGET_ADDR_FMT,
+ bank->base + offset);
break;
}
if (ftfx_fstat & 0x01)
- LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
+ LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
+ bank->base + offset);
buffer += 4;
offset += 4;
uint32_t size_k = bank->size / 1024;
snprintf(buf, buf_size,
- "%s %s: %" PRIu32 "k %s bank %s at 0x%08" PRIx32,
+ "%s %s: %" PRIu32 "k %s bank %s at " TARGET_ADDR_FMT,
bank->driver->name, k_chip->name,
size_k, bank_class_names[k_bank->flash_class],
bank->name, bank->base);
static int kinetis_ke_info(struct flash_bank *bank, char *buf, int buf_size)
{
(void) snprintf(buf, buf_size,
- "%s driver for flash bank %s at 0x%8.8" PRIx32 "",
+ "%s driver for flash bank %s at " TARGET_ADDR_FMT,
bank->driver->name, bank->name, bank->base);
return ERROR_OK;
int retval = target_write_memory(target, (*iap_working_area)->address, 4, 2, jump_gate);
if (retval != ERROR_OK) {
- LOG_ERROR("Write memory at address 0x%8.8" TARGET_PRIxADDR " failed (check work_area definition)",
+ LOG_ERROR("Write memory at address " TARGET_ADDR_FMT " failed (check work_area definition)",
(*iap_working_area)->address);
target_free_working_area(target, *iap_working_area);
}
free(last_buffer);
}
- LOG_DEBUG("writing 0x%" PRIx32 " bytes to address 0x%" PRIx32, thisrun_bytes,
- bank->base + offset + bytes_written);
+ LOG_DEBUG("writing 0x%" PRIx32 " bytes to address " TARGET_ADDR_FMT,
+ thisrun_bytes, bank->base + offset + bytes_written);
/* Write data */
param_table[0] = bank->base + offset + bytes_written;
return retval;
}
- LOG_DEBUG("Writing algorithm to working area at 0x%08" TARGET_PRIxADDR,
+ LOG_DEBUG("Writing algorithm to working area at " TARGET_ADDR_FMT,
spifi_init_algorithm->address);
/* Write algorithm to working area */
retval = target_write_buffer(target,
char info_bootflash_addr_str[64];
if (niietcm4_info->bflash_info_remap)
- snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str), "0x%08x base adress", bank->base);
+ snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
+ TARGET_ADDR_FMT " base adress", bank->base);
else
- snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str), "not maped to global adress space");
+ snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
+ "not mapped to global adress space");
snprintf(niietcm4_info->chip_brief,
sizeof(niietcm4_info->chip_brief),
bank->bank_number = 1;
break;
default:
- LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
+ LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
return ERROR_FAIL;
}
return retval;
for (i = first; i <= last; i++) {
- LOG_DEBUG("erasing sector %d at address 0x%" PRIx32 "", i, bank->base + bank->sectors[i].offset);
+ LOG_DEBUG("erasing sector %d at address " TARGET_ADDR_FMT, i,
+ bank->base + bank->sectors[i].offset);
retval = target_write_u32(target, NUMICRO_FLASH_ISPADR, bank->base + bank->sectors[i].offset);
if (retval != ERROR_OK)
return retval;
for (size_t i = 0; i < cpu->n_banks; i++) {
if (bank->base == cpu->bank[i].base) {
*flash_size = cpu->bank[i].size;
- LOG_INFO("bank base = 0x%08" PRIx32 ", size = 0x%08" PRIx32 "", bank->base, *flash_size);
+ LOG_INFO("bank base = " TARGET_ADDR_FMT ", size = 0x%08"
+ PRIx32, bank->base, *flash_size);
return ERROR_OK;
}
}
return ERROR_TARGET_NOT_HALTED;
}
- LOG_DEBUG("writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32
+ LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
if (offset & 0x3) {
struct working_area *data_area = even_row ? even_row_area : odd_row_area;
unsigned len = MIN(ROW_SIZE, byte_count);
- LOG_DEBUG("Writing load command for array %u row %u at 0x%08" TARGET_PRIxADDR,
+ LOG_DEBUG("Writing load command for array %u row %u at " TARGET_ADDR_FMT,
array_id, row, data_area->address);
psoc5lp_spc_write_opcode_buffer(target, buf, SPC_LOAD_ROW);
/* This is the first bank */
flash_size_in_kb = stm32x_info->part_info->first_bank_size_kb;
} else {
- LOG_WARNING("STM32H flash bank base address config is incorrect."
- " 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
+ LOG_WARNING("STM32H flash bank base address config is incorrect. "
+ TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
bank->base, base_address, second_bank_base);
return ERROR_FAIL;
}
/* This is the first bank */
flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
} else {
- LOG_WARNING("STM32L flash bank base address config is incorrect."
- " 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
+ LOG_WARNING("STM32L flash bank base address config is incorrect. "
+ TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
+ " or 0x%" PRIx32,
bank->base, base_address, second_bank_base);
return ERROR_FAIL;
}
stmsmi_info->bank_num = SMI_SEL_BANK3;
break;
default:
- LOG_ERROR("Invalid SMI base address 0x%" PRIx32, bank->base);
+ LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base);
return ERROR_FAIL;
}
io_base = target_device->io_base;
stmsmi_info->io_base = io_base;
- LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32,
+ LOG_DEBUG("Valid SMI on device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
/* read and decode flash ID; returns in SW mode */
LOG_WARNING("Flash protection check is not implemented.");
command_print(CMD_CTX,
- "#%d : %s at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32
+ "#%d : %s at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32
", buswidth %i, chipwidth %i",
p->bank_number,
p->driver->name,
retval = p->driver->probe(p);
if (retval == ERROR_OK)
command_print(CMD_CTX,
- "flash '%s' found at 0x%8.8" PRIx32,
+ "flash '%s' found at " TARGET_ADDR_FMT,
p->driver->name,
p->base);
} else {
command_print(CMD_CTX, "successfully checked erase state");
else {
command_print(CMD_CTX,
- "unknown error when checking erase state of flash bank #%s at 0x%8.8" PRIx32,
+ "unknown error when checking erase state of flash bank #%s at "
+ TARGET_ADDR_FMT,
CMD_ARGV[0],
p->base);
}
{
struct flash_bank *p;
int retval = ERROR_OK;
- uint32_t address;
+ target_addr_t address;
uint32_t length;
bool do_pad = false;
bool do_unlock = false;
if (CMD_ARGC != 2)
return ERROR_COMMAND_SYNTAX_ERROR;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
if (length <= 0) {
retval = flash_erase_address_range(target, do_pad, address, length);
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
- command_print(CMD_CTX, "erased address 0x%8.8" PRIx32 " (length %" PRIi32 ")"
+ command_print(CMD_CTX, "erased address " TARGET_ADDR_FMT " (length %"
+ PRIi32 ")"
" in %fs (%0.3f KiB/s)", address, length,
duration_elapsed(&bench), duration_kbps(&bench, length));
}
c->name = strdup(bank_name);
c->target = target;
c->driver = driver;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], c->base);
+ COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[1], c->base);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], c->size);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], c->chip_width);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], c->bus_width);
int retval;
retval = CALL_COMMAND_HANDLER(driver->flash_bank_command, c);
if (ERROR_OK != retval) {
- LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" PRIx32 "; usage: %s",
- driver_name, c->base, driver->usage);
+ LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT
+ "; usage: %s", driver_name, c->base, driver->usage);
free(c);
return retval;
}
unsigned n = 0;
for (struct flash_bank *p = flash_bank_list(); p; p = p->next, n++) {
- LOG_USER("#%d : %s (%s) at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 ", "
+ LOG_USER("#%d : %s (%s) at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32 ", "
"buswidth %u, chipwidth %u", p->bank_number,
p->name, p->driver->name, p->base, p->size,
p->bus_width, p->chip_width);
part_name = "TMS470R1A256";
if (bank->base >= 0x00040000) {
- LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
+ LOG_ERROR("No %s flash bank contains base address "
+ TARGET_ADDR_FMT ".",
part_name,
bank->base);
return ERROR_FLASH_OPERATION_FAILED;
(void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS,
sizeof(TMS470R1A288_BANK1_SECTORS));
} else {
- LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
+ LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
(void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS,
sizeof(TMS470R1A384_BANK2_SECTORS));
} else {
- LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".",
+ LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
tms470_read_part_info(bank);
- LOG_INFO("Writing %" PRId32 " bytes starting at 0x%08" PRIx32 "", count, bank->base +
- offset);
+ LOG_INFO("Writing %" PRId32 " bytes starting at " TARGET_ADDR_FMT,
+ count, bank->base + offset);
/* set GLBCTRL.4 */
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
if (master_bank == NULL)
return ERROR_FLASH_OPERATION_FAILED;
- snprintf(buf, buf_size, "%s driver for flash bank %s at 0x%8.8" PRIx32 "",
+ snprintf(buf, buf_size, "%s driver for flash bank %s at " TARGET_ADDR_FMT,
bank->driver->name, master_bank->name, master_bank->base);
return ERROR_OK;
uint32_t blocks = MIN(block_count, data_workarea->size / NVM_BLOCK_SIZE);
uint32_t addr = bank->base + offset;
- LOG_DEBUG("copying %" PRId32 " bytes to SRAM 0x%08" TARGET_PRIxADDR,
+ LOG_DEBUG("copying %" PRId32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(blocks * NVM_BLOCK_SIZE, byte_count),
data_workarea->address);
memcpy(&tmp_buf[start_pad], buffer, remaining);
if (end_pad) {
- LOG_INFO("Padding end of page @%08"PRIx32" by %d bytes",
+ LOG_INFO("Padding end of page @" TARGET_ADDR_FMT " by %d bytes",
bank->base + offset, end_pad);
memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
}
Code Review / openocd.git / commitdiff