The initialization of memory port 1 is required by
SPEAr310 only
Change-Id: I9d655da1026795f02ff2f82aed36441068cf266d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/225
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
mww 0xfca80040 0x00000000 ;# remove all RAS resets
mww 0xb4000008 0x00002ff4 ;# RAS function enable
mww 0xfca80040 0x00000000 ;# remove all RAS resets
mww 0xb4000008 0x00002ff4 ;# RAS function enable
+ mww 0xfca80050 0x00000001 ;# Enable clk mem port 1
+
mww 0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv
mww 0xfca80140 0x017bdef6
}
mww 0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv
mww 0xfca80140 0x017bdef6
}
mww 0xfca800e4 0x78000008 ;# COMP1V8_REG
mww 0xfca800ec 0x78000008 ;# COMP3V3_REG
mww 0xfca800e4 0x78000008 ;# COMP1V8_REG
mww 0xfca800ec 0x78000008 ;# COMP3V3_REG
- mww 0xfca80050 0x00000001 ;# Enable clk mem port 1
-
mww 0xfc000000 0x10000f5f ;# init SMI and set HW mode
mww 0xfc000000 0x00000f5f
mww 0xfc000000 0x10000f5f ;# init SMI and set HW mode
mww 0xfc000000 0x00000f5f
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