arm_adi_v5: add arm SoC-600 part numbers 50/6450/3
authorAntonio Borneo <borneo.antonio@gmail.com>
Mon, 16 Aug 2021 22:13:05 +0000 (00:13 +0200)
committerAntonio Borneo <borneo.antonio@gmail.com>
Sat, 25 Sep 2021 13:06:53 +0000 (13:06 +0000)
Extract new part numbers from ARM CoreSight System-on-Chip SoC-600
Technical Reference Manual Revision r4p1 and add them to the array
dap_partnums.

Change-Id: I88d8aa3c084f6e832b75032e75bfb6d377a08360
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6450
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
src/target/arm_adi_v5.c

index 0d458e2b5f8066f1c8bdedf8c4f375ddd371a96a..66d084952d5fa3ae9a36127e58133bf804541792 100644 (file)
@@ -1131,6 +1131,7 @@ static const struct dap_part_nums {
        { ARM_ID, 0x00c, "Cortex-M4 SCS",              "(System Control Space)", },
        { ARM_ID, 0x00d, "CoreSight ETM11",            "(Embedded Trace)", },
        { ARM_ID, 0x00e, "Cortex-M7 FPB",              "(Flash Patch and Breakpoint)", },
        { ARM_ID, 0x00c, "Cortex-M4 SCS",              "(System Control Space)", },
        { ARM_ID, 0x00d, "CoreSight ETM11",            "(Embedded Trace)", },
        { ARM_ID, 0x00e, "Cortex-M7 FPB",              "(Flash Patch and Breakpoint)", },
+       { ARM_ID, 0x193, "SoC-600 TSGEN",              "(Timestamp Generator)", },
        { ARM_ID, 0x470, "Cortex-M1 ROM",              "(ROM Table)", },
        { ARM_ID, 0x471, "Cortex-M0 ROM",              "(ROM Table)", },
        { ARM_ID, 0x490, "Cortex-A15 GIC",             "(Generic Interrupt Controller)", },
        { ARM_ID, 0x470, "Cortex-M1 ROM",              "(ROM Table)", },
        { ARM_ID, 0x471, "Cortex-M0 ROM",              "(ROM Table)", },
        { ARM_ID, 0x490, "Cortex-A15 GIC",             "(Generic Interrupt Controller)", },
@@ -1192,6 +1193,19 @@ static const struct dap_part_nums {
        { ARM_ID, 0x9d7, "Cortex-A57 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d8, "Cortex-A72 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
        { ARM_ID, 0x9d7, "Cortex-A57 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d8, "Cortex-A72 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
+       { ARM_ID, 0x9e2, "SoC-600 APB-AP",             "(APB4 Memory Access Port)", },
+       { ARM_ID, 0x9e3, "SoC-600 AHB-AP",             "(AHB5 Memory Access Port)", },
+       { ARM_ID, 0x9e4, "SoC-600 AXI-AP",             "(AXI Memory Access Port)", },
+       { ARM_ID, 0x9e5, "SoC-600 APv1 Adapter",       "(Access Port v1 Adapter)", },
+       { ARM_ID, 0x9e6, "SoC-600 JTAG-AP",            "(JTAG Access Port)", },
+       { ARM_ID, 0x9e7, "SoC-600 TPIU",               "(Trace Port Interface Unit)", },
+       { ARM_ID, 0x9e8, "SoC-600 TMC ETR/ETS",        "(Embedded Trace Router/Streamer)", },
+       { ARM_ID, 0x9e9, "SoC-600 TMC ETB",            "(Embedded Trace Buffer)", },
+       { ARM_ID, 0x9ea, "SoC-600 TMC ETF",            "(Embedded Trace FIFO)", },
+       { ARM_ID, 0x9eb, "SoC-600 ATB Funnel",         "(Trace Funnel)", },
+       { ARM_ID, 0x9ec, "SoC-600 ATB Replicator",     "(Trace Replicator)", },
+       { ARM_ID, 0x9ed, "SoC-600 CTI",                "(Cross Trigger)", },
+       { ARM_ID, 0x9ee, "SoC-600 CATU",               "(Address Translation Unit)", },
        { ARM_ID, 0xc05, "Cortex-A5 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc07, "Cortex-A7 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc08, "Cortex-A8 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc05, "Cortex-A5 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc07, "Cortex-A7 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc08, "Cortex-A8 Debug",            "(Debug Unit)", },

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)