Some boards might have RCLK omitted from the JTAG connector and if the
interface claims support for it, OpenOCD will end up trying to use
RCLK while it's actually impossible.
This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch.
Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1695
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
13 files changed:
# core 1 - 0x80112000
# Slow speed to be sure it will work
# core 1 - 0x80112000
# Slow speed to be sure it will work
set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1
set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80110000
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80110000
-$_TARGETNAME1 configure -event reset-start { jtag_rclk 1000 }
+$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
$_TARGETNAME1 configure -event gdb-attach { halt }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
$_TARGETNAME1 configure -event gdb-attach { halt }
#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0x80112000
#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0x80112000
-#$_TARGETNAME2 configure -event reset-start { jtag_rclk 1000 }
+#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
#$_TARGETNAME2 configure -event gdb-attach { halt }
#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
#$_TARGETNAME2 configure -event gdb-attach { halt }
adapter_nsrst_delay 300
jtag_ntrst_delay 200
adapter_nsrst_delay 300
jtag_ntrst_delay 200
######################
# Target configuration
######################
# Target configuration
reset_config trst_and_srst
reset_config trst_and_srst
adapter_nsrst_delay 200
jtag_ntrst_delay 200
adapter_nsrst_delay 200
jtag_ntrst_delay 200
scan_chain
$_TARGETNAME configure -event reset-start {
# at reset chip runs at 32khz
scan_chain
$_TARGETNAME configure -event reset-start {
# at reset chip runs at 32khz
}
$_TARGETNAME configure -event reset-init {at91sam_init}
}
$_TARGETNAME configure -event reset-init {at91sam_init}
sleep 10 ;# wait 10 ms
# Now run at anything fast... ie: 10mhz!
sleep 10 ;# wait 10 ms
# Now run at anything fast... ie: 10mhz!
- jtag_rclk 10000 ;# Increase JTAG Speed to 6 MHz
+ adapter_khz 10000 ;# Increase JTAG Speed to 6 MHz
mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0
mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0
# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
}
# Slow speed to be sure it will work
}
# Slow speed to be sure it will work
-jtag_rclk 1000
-$_TARGETNAME configure -event reset-start { jtag_rclk 1000 }
+adapter_khz 1000
+$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
$_TARGETNAME configure -event gdb-attach { halt }
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
$_TARGETNAME configure -event gdb-attach { halt }
}
# jtag speed. We need to stick to 16kHz until we've finished reset.
}
# jtag speed. We need to stick to 16kHz until we've finished reset.
reset_config trst_and_srst
reset_config trst_and_srst
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-start { adapter_khz 16 }
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
}
$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
}
$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
jtag_ntrst_delay 200
# rclk hasn't been working well. This maybe the mc13224v or something else.
jtag_ntrst_delay 200
# rclk hasn't been working well. This maybe the mc13224v or something else.
adapter_khz 2000
######################
adapter_khz 2000
######################
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
-jtag_rclk 1000
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+adapter_khz 1000
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter_khz 1500
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
}
# jtag speed. We need to stick to 16kHz until we've finished reset.
}
# jtag speed. We need to stick to 16kHz until we've finished reset.
adapter_nsrst_delay 100
jtag_ntrst_delay 100
adapter_nsrst_delay 100
jtag_ntrst_delay 100
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-start { adapter_khz 16 }
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter_khz 1500
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter_khz 1500
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter_khz 1500
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)