flash/at91sam4: set wait states only once per write

Read-modify-write setting of FMR register requires an USB turnaround.
Setting FMR before each page write is not necessary and decreases the
write speed.

Change-Id: I67844c898aaf117f155c762c979840b603c767ed
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4611
Tested-by: jenkins
Reviewed-by: Svetoslav Enchev <svetoslav.enchev@gmail.com>

diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index b8f4e1622cacf89e7db3d5a306a474e85aedabf5..577360a6ee71d4e8267dbc6da58161ad9d670624 100644 (file)
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -2789,20 +2789,17 @@ static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum,
        return r;
 }
 
        return r;
 }
 

-static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
+static int sam4_set_wait(struct sam4_bank_private *pPrivate)

 {
 {

-       uint32_t adr;
-       uint32_t status;

        uint32_t fmr;   /* EEFC Flash Mode Register */
        int r;
 
        uint32_t fmr;   /* EEFC Flash Mode Register */
        int r;
 

-       adr = pagenum * pPrivate->page_size;
-       adr = (adr + pPrivate->base_address);
-

        /* Get flash mode register value */
        r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
        /* Get flash mode register value */
        r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);

-       if (r != ERROR_OK)
-               LOG_DEBUG("Error Read failed: read flash mode register");
+       if (r != ERROR_OK) {
+               LOG_ERROR("Error Read failed: read flash mode register");
+               return r;
+       }

 
        /* Clear flash wait state field */
        fmr &= 0xfffff0ff;
 
        /* Clear flash wait state field */
        fmr &= 0xfffff0ff;


@@ -2813,7 +2810,19 @@ static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum,
        LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
        r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
        if (r != ERROR_OK)
        LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
        r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
        if (r != ERROR_OK)

-               LOG_DEBUG("Error Write failed: set flash mode register");
+               LOG_ERROR("Error Write failed: set flash mode register");
+
+       return r;
+}
+
+static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
+{
+       uint32_t adr;
+       uint32_t status;
+       int r;
+
+       adr = pagenum * pPrivate->page_size;
+       adr = (adr + pPrivate->base_address);

 
        /* 1st sector 8kBytes - page 0 - 15*/
        /* 2nd sector 8kBytes - page 16 - 30*/
 
        /* 1st sector 8kBytes - page 0 - 15*/
        /* 2nd sector 8kBytes - page 16 - 30*/


@@ -2901,6 +2910,10 @@ static int sam4_write(struct flash_bank *bank,
                goto done;
        }
 
                goto done;
        }
 

+       r = sam4_set_wait(pPrivate);
+       if (r != ERROR_OK)
+               goto done;
+

        /* what page do we start & end in? */
        page_cur = offset / pPrivate->page_size;
        page_end = (offset + count - 1) / pPrivate->page_size;
        /* what page do we start & end in? */
        page_cur = offset / pPrivate->page_size;
        page_end = (offset + count - 1) / pPrivate->page_size;