On a target where AHB AP memory access is unavailable, care should be
taken to avoid treating addresses as virtual if the MMU was disabled
at the time the target was stopped.
Without this it's impossible to peek memory with Gdb when debugging
e.g. a bootloader because cortex_a8_read_memory() unconditionally
tried (and failed because of a sanity check in cortex_a8_mmu_modify)
to enable MMU.
Change-Id: Id7c63f4912920fb71a6104226ec6428d18c96a56
Reported-by: mbm@openwrt.org
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1787
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
static int cortex_a8_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
static int cortex_a8_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
uint32_t virt, phys;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
uint32_t virt, phys;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
/* cortex_a8 handles unaligned memory access */
LOG_DEBUG("Reading memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
size, count);
/* cortex_a8 handles unaligned memory access */
LOG_DEBUG("Reading memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
size, count);
+
+ /* determine if MMU was enabled on target stop */
+ if (!armv7a->is_armv7r) {
+ retval = cortex_a8_mmu(target, &mmu_enabled);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
- if (!armv7a->is_armv7r) {
- retval = cortex_a8_mmu(target, &enabled);
+ if (mmu_enabled) {
+ virt = address;
+ retval = cortex_a8_virt2phys(target, virt, &phys);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
-
- if (enabled) {
- virt = address;
- retval = cortex_a8_virt2phys(target, virt, &phys);
- if (retval != ERROR_OK)
- return retval;
-
- LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
- virt, phys);
- address = phys;
- }
+ LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
+ virt, phys);
+ address = phys;
}
retval = cortex_a8_read_phys_memory(target, address, size, count, buffer);
} else {
}
retval = cortex_a8_read_phys_memory(target, address, size, count, buffer);
} else {
- if (!armv7a->is_armv7r) {
retval = cortex_a8_check_address(target, address);
if (retval != ERROR_OK)
return retval;
retval = cortex_a8_check_address(target, address);
if (retval != ERROR_OK)
return retval;
+ /* enable MMU as we could have disabled it for phys access */
retval = cortex_a8_mmu_modify(target, 1);
if (retval != ERROR_OK)
return retval;
retval = cortex_a8_mmu_modify(target, 1);
if (retval != ERROR_OK)
return retval;
static int cortex_a8_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
static int cortex_a8_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
uint32_t virt, phys;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
uint8_t apsel = swjdp->apsel;
uint32_t virt, phys;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->arm.dap;
uint8_t apsel = swjdp->apsel;
/* cortex_a8 handles unaligned memory access */
LOG_DEBUG("Writing memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
size, count);
/* cortex_a8 handles unaligned memory access */
LOG_DEBUG("Writing memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
size, count);
- if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
+ /* determine if MMU was enabled on target stop */
+ if (!armv7a->is_armv7r) {
+ retval = cortex_a8_mmu(target, &mmu_enabled);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
LOG_DEBUG("Writing memory to address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size,
count);
LOG_DEBUG("Writing memory to address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size,
count);
- if (!armv7a->is_armv7r) {
- retval = cortex_a8_mmu(target, &enabled);
+ if (mmu_enabled) {
+ virt = address;
+ retval = cortex_a8_virt2phys(target, virt, &phys);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- if (enabled) {
- virt = address;
- retval = cortex_a8_virt2phys(target, virt, &phys);
- if (retval != ERROR_OK)
- return retval;
- LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
- virt,
- phys);
- address = phys;
- }
+ LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
+ virt,
+ phys);
+ address = phys;
retval = cortex_a8_write_phys_memory(target, address, size,
count, buffer);
} else {
retval = cortex_a8_write_phys_memory(target, address, size,
count, buffer);
} else {
- if (!armv7a->is_armv7r) {
retval = cortex_a8_check_address(target, address);
if (retval != ERROR_OK)
return retval;
retval = cortex_a8_check_address(target, address);
if (retval != ERROR_OK)
return retval;
+ /* enable MMU as we could have disabled it for phys access */
retval = cortex_a8_mmu_modify(target, 1);
if (retval != ERROR_OK)
return retval;
retval = cortex_a8_mmu_modify(target, 1);
if (retval != ERROR_OK)
return retval;
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