This removes the armv7m::core_cache and uses the generic arm::core_cache.
Change-Id: If854281b31486cea8be005008f6a71a691b4c208
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/968
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
armv7m->pre_restore_context(target);
for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
armv7m->pre_restore_context(target);
for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
- if (armv7m->core_cache->reg_list[i].dirty)
+ if (armv7m->arm.core_cache->reg_list[i].dirty)
armv7m->write_core_reg(target, i);
}
armv7m->write_core_reg(target, i);
}
static int armv7m_get_core_reg(struct reg *reg)
{
int retval;
static int armv7m_get_core_reg(struct reg *reg)
{
int retval;
- struct armv7m_core_reg *armv7m_reg = reg->arch_info;
+ struct arm_reg *armv7m_reg = reg->arch_info;
struct target *target = armv7m_reg->target;
struct armv7m_common *armv7m = target_to_armv7m(target);
struct target *target = armv7m_reg->target;
struct armv7m_common *armv7m = target_to_armv7m(target);
static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
{
static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
{
- struct armv7m_core_reg *armv7m_reg = reg->arch_info;
+ struct arm_reg *armv7m_reg = reg->arch_info;
struct target *target = armv7m_reg->target;
uint32_t value = buf_get_u32(buf, 0, 32);
struct target *target = armv7m_reg->target;
uint32_t value = buf_get_u32(buf, 0, 32);
{
uint32_t reg_value;
int retval;
{
uint32_t reg_value;
int retval;
- struct armv7m_core_reg *armv7m_core_reg;
+ struct arm_reg *armv7m_core_reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
if (num >= ARMV7M_NUM_REGS)
return ERROR_COMMAND_SYNTAX_ERROR;
struct armv7m_common *armv7m = target_to_armv7m(target);
if (num >= ARMV7M_NUM_REGS)
return ERROR_COMMAND_SYNTAX_ERROR;
- armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
+ armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
retval = armv7m->load_core_reg_u32(target,
armv7m_core_reg->num,
®_value);
retval = armv7m->load_core_reg_u32(target,
armv7m_core_reg->num,
®_value);
- buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
- armv7m->core_cache->reg_list[num].valid = 1;
- armv7m->core_cache->reg_list[num].dirty = 0;
+ buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
+ armv7m->arm.core_cache->reg_list[num].valid = 1;
+ armv7m->arm.core_cache->reg_list[num].dirty = 0;
{
int retval;
uint32_t reg_value;
{
int retval;
uint32_t reg_value;
- struct armv7m_core_reg *armv7m_core_reg;
+ struct arm_reg *armv7m_core_reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
if (num >= ARMV7M_NUM_REGS)
return ERROR_COMMAND_SYNTAX_ERROR;
struct armv7m_common *armv7m = target_to_armv7m(target);
if (num >= ARMV7M_NUM_REGS)
return ERROR_COMMAND_SYNTAX_ERROR;
- reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
- armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
+ reg_value = buf_get_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32);
+ armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
retval = armv7m->store_core_reg_u32(target,
armv7m_core_reg->num,
reg_value);
if (retval != ERROR_OK) {
LOG_ERROR("JTAG failure");
retval = armv7m->store_core_reg_u32(target,
armv7m_core_reg->num,
reg_value);
if (retval != ERROR_OK) {
LOG_ERROR("JTAG failure");
- armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
+ armv7m->arm.core_cache->reg_list[num].dirty = armv7m->arm.core_cache->reg_list[num].valid;
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
- armv7m->core_cache->reg_list[num].valid = 1;
- armv7m->core_cache->reg_list[num].dirty = 0;
+ armv7m->arm.core_cache->reg_list[num].valid = 1;
+ armv7m->arm.core_cache->reg_list[num].dirty = 0;
* - CPSR
*/
for (i = 0; i < 16; i++)
* - CPSR
*/
for (i = 0; i < 16; i++)
- (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
+ (*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i];
for (i = 16; i < 24; i++)
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
for (i = 16; i < 24; i++)
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
/* refresh core register cache
* Not needed if core register cache is always consistent with target process state */
for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) {
/* refresh core register cache
* Not needed if core register cache is always consistent with target process state */
for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) {
- if (!armv7m->core_cache->reg_list[i].valid)
+ if (!armv7m->arm.core_cache->reg_list[i].valid)
armv7m->read_core_reg(target, i);
armv7m_algorithm_info->context[i] = buf_get_u32(
armv7m->read_core_reg(target, i);
armv7m_algorithm_info->context[i] = buf_get_u32(
- armv7m->core_cache->reg_list[i].value,
+ armv7m->arm.core_cache->reg_list[i].value,
for (int i = 0; i < num_reg_params; i++) {
struct reg *reg =
for (int i = 0; i < num_reg_params; i++) {
struct reg *reg =
- register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
+ register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, 0);
/* uint32_t regvalue; */
if (!reg) {
/* uint32_t regvalue; */
if (!reg) {
if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY) {
LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY) {
LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
- buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
+ buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
0, 1, armv7m_algorithm_info->core_mode);
0, 1, armv7m_algorithm_info->core_mode);
- armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
- armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
+ armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
+ armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
}
armv7m_algorithm_info->core_mode = core_mode;
}
armv7m_algorithm_info->core_mode = core_mode;
/* Copy core register values to reg_params[] */
for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction != PARAM_OUT) {
/* Copy core register values to reg_params[] */
for (int i = 0; i < num_reg_params; i++) {
if (reg_params[i].direction != PARAM_OUT) {
- struct reg *reg = register_get_by_name(armv7m->core_cache,
+ struct reg *reg = register_get_by_name(armv7m->arm.core_cache,
reg_params[i].reg_name,
0);
reg_params[i].reg_name,
0);
for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
uint32_t regvalue;
for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
uint32_t regvalue;
- regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
+ regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
if (regvalue != armv7m_algorithm_info->context[i]) {
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
if (regvalue != armv7m_algorithm_info->context[i]) {
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
- armv7m->core_cache->reg_list[i].name,
+ armv7m->arm.core_cache->reg_list[i].name,
armv7m_algorithm_info->context[i]);
armv7m_algorithm_info->context[i]);
- buf_set_u32(armv7m->core_cache->reg_list[i].value,
+ buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
0, 32, armv7m_algorithm_info->context[i]);
0, 32, armv7m_algorithm_info->context[i]);
- armv7m->core_cache->reg_list[i].valid = 1;
- armv7m->core_cache->reg_list[i].dirty = 1;
+ armv7m->arm.core_cache->reg_list[i].valid = 1;
+ armv7m->arm.core_cache->reg_list[i].dirty = 1;
struct arm *arm = &armv7m->arm;
uint32_t ctrl, sp;
struct arm *arm = &armv7m->arm;
uint32_t ctrl, sp;
- ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
- sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
+ ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
+ sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
LOG_USER("target halted due to %s, current mode: %s %s\n"
"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
LOG_USER("target halted due to %s, current mode: %s %s\n"
"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
- struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
+ struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
int i;
#ifdef ARMV7_GDB_HACKS
int i;
#ifdef ARMV7_GDB_HACKS
cache->reg_list = reg_list;
cache->num_regs = num_regs;
(*cache_p) = cache;
cache->reg_list = reg_list;
cache->num_regs = num_regs;
(*cache_p) = cache;
- armv7m->core_cache = cache;
for (i = 0; i < num_regs; i++) {
arch_info[i].num = armv7m_regs[i].id;
arch_info[i].target = target;
for (i = 0; i < num_regs; i++) {
arch_info[i].num = armv7m_regs[i].id;
arch_info[i].target = target;
- arch_info[i].armv7m_common = armv7m;
+ arch_info[i].arm = arm;
+
reg_list[i].name = armv7m_regs[i].name;
reg_list[i].size = armv7m_regs[i].bits;
reg_list[i].value = calloc(1, 4);
reg_list[i].name = armv7m_regs[i].name;
reg_list[i].size = armv7m_regs[i].bits;
reg_list[i].value = calloc(1, 4);
struct arm arm;
int common_magic;
struct arm arm;
int common_magic;
- struct reg_cache *core_cache;
int exception_number;
struct adiv5_dap dap;
int exception_number;
struct adiv5_dap dap;
uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
};
uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
};
-struct armv7m_core_reg {
- uint32_t num;
- struct target *target;
- struct armv7m_common *armv7m_common;
-};
-
struct reg_cache *armv7m_build_reg_cache(struct target *target);
enum armv7m_mode armv7m_number_to_mode(int number);
int armv7m_mode_to_number(enum armv7m_mode mode);
struct reg_cache *armv7m_build_reg_cache(struct target *target);
enum armv7m_mode armv7m_number_to_mode(int number);
int armv7m_mode_to_number(enum armv7m_mode mode);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(armv7m->arm.core_cache);
/* make sure we have latest dhcsr flags */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
/* make sure we have latest dhcsr flags */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
return retval;
/* Examine target state and mode
return retval;
/* Examine target state and mode
- * First load register acessible through core debug port*/
- int num_regs = armv7m->core_cache->num_regs;
+ * First load register accessible through core debug port */
+ int num_regs = arm->core_cache->num_regs;
for (i = 0; i < num_regs; i++) {
for (i = 0; i < num_regs; i++) {
- if (!armv7m->core_cache->reg_list[i].valid)
+ if (!armv7m->arm.core_cache->reg_list[i].valid)
armv7m->read_core_reg(target, i);
}
armv7m->read_core_reg(target, i);
}
- r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
+ r = arm->core_cache->reg_list + ARMV7M_xPSR;
xPSR = buf_get_u32(r->value, 0, 32);
#ifdef ARMV7_GDB_HACKS
xPSR = buf_get_u32(r->value, 0, 32);
#ifdef ARMV7_GDB_HACKS
target->state = TARGET_RESET;
/* registers are now invalid */
target->state = TARGET_RESET;
/* registers are now invalid */
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(cortex_m3->armv7m.arm.core_cache);
while (timeout < 100) {
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
while (timeout < 100) {
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
- r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
+ r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
/* Disable interrupts */
/* We disable interrupts in the PRIMASK register instead of
/* Disable interrupts */
/* We disable interrupts in the PRIMASK register instead of
r->valid = true;
/* Make sure we are in Thumb mode */
r->valid = true;
/* Make sure we are in Thumb mode */
- r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
+ r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR;
buf_set_u32(r->value, 24, 1, 1);
r->dirty = true;
r->valid = true;
buf_set_u32(r->value, 24, 1, 1);
r->dirty = true;
r->valid = true;
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
- register_cache_invalidate(armv7m->core_cache);
+ register_cache_invalidate(armv7m->arm.core_cache);
if (!debug_execution) {
target->state = TARGET_RUNNING;
if (!debug_execution) {
target->state = TARGET_RUNNING;
return retval;
/* registers are now invalid */
return retval;
/* registers are now invalid */
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(armv7m->arm.core_cache);
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
/* allow scripts to override the reset event */
target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
/* allow scripts to override the reset event */
target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(cortex_m3->armv7m.arm.core_cache);
target->state = TARGET_RESET;
return ERROR_OK;
target->state = TARGET_RESET;
return ERROR_OK;
target->state = TARGET_RESET;
jtag_add_sleep(50000);
target->state = TARGET_RESET;
jtag_add_sleep(50000);
- register_cache_invalidate(cortex_m3->armv7m.core_cache);
+ register_cache_invalidate(cortex_m3->armv7m.arm.core_cache);
if (target->reset_halt) {
retval = target_halt(target);
if (target->reset_halt) {
retval = target_halt(target);
struct reg *r;
LOG_ERROR("JTAG failure");
struct reg *r;
LOG_ERROR("JTAG failure");
- r = armv7m->core_cache->reg_list + num;
+ r = armv7m->arm.core_cache->reg_list + num;
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
struct reg *r;
LOG_ERROR("JTAG failure");
struct reg *r;
LOG_ERROR("JTAG failure");
- r = armv7m->core_cache->reg_list + num;
+ r = armv7m->arm.core_cache->reg_list + num;
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
static int adapter_load_context(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
static int adapter_load_context(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- int num_regs = armv7m->core_cache->num_regs;
+ int num_regs = armv7m->arm.core_cache->num_regs;
for (int i = 0; i < num_regs; i++) {
for (int i = 0; i < num_regs; i++) {
- if (!armv7m->core_cache->reg_list[i].valid)
+ if (!armv7m->arm.core_cache->reg_list[i].valid)
armv7m->read_core_reg(target, i);
}
armv7m->read_core_reg(target, i);
}
/* make sure we clear the vector catch bit */
adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
/* make sure we clear the vector catch bit */
adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
- r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
+ r = arm->core_cache->reg_list + ARMV7M_xPSR;
xPSR = buf_get_u32(r->value, 0, 32);
/* Are we in an exception handler */
xPSR = buf_get_u32(r->value, 0, 32);
/* Are we in an exception handler */
return res;
/* registers are now invalid */
return res;
/* registers are now invalid */
- register_cache_invalidate(armv7m->core_cache);
+ register_cache_invalidate(armv7m->arm.core_cache);
if (target->reset_halt) {
target->state = TARGET_RESET;
if (target->reset_halt) {
target->state = TARGET_RESET;
armv7m_restore_context(target);
/* registers are now invalid */
armv7m_restore_context(target);
/* registers are now invalid */
- register_cache_invalidate(armv7m->core_cache);
+ register_cache_invalidate(armv7m->arm.core_cache);
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) {
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) {
return res;
/* registers are now invalid */
return res;
/* registers are now invalid */
- register_cache_invalidate(armv7m->core_cache);
+ register_cache_invalidate(armv7m->arm.core_cache);
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
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