ARM semihosting: work with both low and high vectors

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 39625f61bcaccc5f7726358112021d749c0af7af..d448d54e8050aa3eed6c0b0c1dbf335d078e8482 100644 (file)
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -414,18 +414,16 @@ static int do_semihosting(struct target *target)
 int arm_semihosting(struct target *target, int *retval)
 {
        struct arm *arm = target_to_arm(target);
-       uint32_t lr, spsr;
+       uint32_t pc, lr, spsr;
        struct reg *r;
 
        if (!arm->is_semihosting || arm->core_mode != ARM_MODE_SVC)
                return 0;
 
-       /* Check for PC == 8:  Supervisor Call vector
-        * REVISIT:  assumes low exception vectors, not hivecs...
-        * safer to test "was this entry from a vector catch".
-        */
+       /* Check for PC == 0x00000008 or 0xffff0008: Supervisor Call vector. */
        r = arm->core_cache->reg_list + 15;
-       if (buf_get_u32(r->value, 0, 32) != 0x08)
+       pc = buf_get_u32(r->value, 0, 32);
+       if (pc != 0x00000008 && pc != 0xffff0008)
                return 0;
 
        r = arm_reg_current(arm, 14);