Remove misleading typedef and redundant suffix from struct s3c24xx_nand_controller.
NAND_DEVICE_COMMAND_HANDLER(s3c2410_nand_device_command)
{
NAND_DEVICE_COMMAND_HANDLER(s3c2410_nand_device_command)
{
- s3c24xx_nand_controller_t *info;
+ struct s3c24xx_nand_controller *info;
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
static int s3c2410_init(struct nand_device_s *nand)
{
static int s3c2410_init(struct nand_device_s *nand)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
static int s3c2410_write_data(struct nand_device_s *nand, uint16_t data)
{
static int s3c2410_write_data(struct nand_device_s *nand, uint16_t data)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
static int s3c2410_read_data(struct nand_device_s *nand, void *data)
{
static int s3c2410_read_data(struct nand_device_s *nand, void *data)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
static int s3c2410_nand_ready(struct nand_device_s *nand, int timeout)
{
static int s3c2410_nand_ready(struct nand_device_s *nand, int timeout)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
uint8_t status;
target_t *target = s3c24xx_info->target;
uint8_t status;
NAND_DEVICE_COMMAND_HANDLER(s3c2412_nand_device_command)
{
NAND_DEVICE_COMMAND_HANDLER(s3c2412_nand_device_command)
{
- s3c24xx_nand_controller_t *info;
+ struct s3c24xx_nand_controller *info;
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
static int s3c2412_init(struct nand_device_s *nand)
{
static int s3c2412_init(struct nand_device_s *nand)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
{
NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
{
- s3c24xx_nand_controller_t *info;
+ struct s3c24xx_nand_controller *info;
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
static int s3c2440_init(struct nand_device_s *nand)
{
static int s3c2440_init(struct nand_device_s *nand)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
{
int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
uint8_t status;
target_t *target = s3c24xx_info->target;
uint8_t status;
int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
{
int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
uint32_t nfdata = s3c24xx_info->data;
uint32_t tmp;
target_t *target = s3c24xx_info->target;
uint32_t nfdata = s3c24xx_info->data;
uint32_t tmp;
int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
{
int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
uint32_t nfdata = s3c24xx_info->data;
uint32_t tmp;
target_t *target = s3c24xx_info->target;
uint32_t nfdata = s3c24xx_info->data;
uint32_t tmp;
NAND_DEVICE_COMMAND_HANDLER(s3c2443_nand_device_command)
{
NAND_DEVICE_COMMAND_HANDLER(s3c2443_nand_device_command)
{
- s3c24xx_nand_controller_t *info;
+ struct s3c24xx_nand_controller *info;
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
static int s3c2443_init(struct nand_device_s *nand)
{
static int s3c2443_init(struct nand_device_s *nand)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
S3C24XX_DEVICE_COMMAND()
{
S3C24XX_DEVICE_COMMAND()
{
- s3c24xx_nand_controller_t *s3c24xx_info;
+ struct s3c24xx_nand_controller *s3c24xx_info;
- s3c24xx_info = malloc(sizeof(s3c24xx_nand_controller_t));
+ s3c24xx_info = malloc(sizeof(struct s3c24xx_nand_controller));
if (s3c24xx_info == NULL) {
LOG_ERROR("no memory for nand controller\n");
return -ENOMEM;
if (s3c24xx_info == NULL) {
LOG_ERROR("no memory for nand controller\n");
return -ENOMEM;
int s3c24xx_reset(struct nand_device_s *nand)
{
int s3c24xx_reset(struct nand_device_s *nand)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
int s3c24xx_command(struct nand_device_s *nand, uint8_t command)
{
int s3c24xx_command(struct nand_device_s *nand, uint8_t command)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
int s3c24xx_address(struct nand_device_s *nand, uint8_t address)
{
int s3c24xx_address(struct nand_device_s *nand, uint8_t address)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
int s3c24xx_write_data(struct nand_device_s *nand, uint16_t data)
{
int s3c24xx_write_data(struct nand_device_s *nand, uint16_t data)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
int s3c24xx_read_data(struct nand_device_s *nand, void *data)
{
int s3c24xx_read_data(struct nand_device_s *nand, void *data)
{
- s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+ struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
#include "nand.h"
#include "s3c24xx_regs_nand.h"
#include "nand.h"
#include "s3c24xx_regs_nand.h"
-typedef struct s3c24xx_nand_controller_s
+struct s3c24xx_nand_controller
{
struct target_s *target;
{
struct target_s *target;
uint32_t addr;
uint32_t data;
uint32_t nfstat;
uint32_t addr;
uint32_t data;
uint32_t nfstat;
-} s3c24xx_nand_controller_t;
/* Default to using the un-translated NAND register based address */
#undef S3C2410_NFREG
/* Default to using the un-translated NAND register based address */
#undef S3C2410_NFREG
#define S3C24XX_DEVICE_COMMAND() \
COMMAND_HELPER(s3c24xx_nand_device_command, \
struct nand_device_s *nand, \
#define S3C24XX_DEVICE_COMMAND() \
COMMAND_HELPER(s3c24xx_nand_device_command, \
struct nand_device_s *nand, \
- s3c24xx_nand_controller_t **info)
+ struct s3c24xx_nand_controller **info)
S3C24XX_DEVICE_COMMAND();
S3C24XX_DEVICE_COMMAND();
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