From: Zachary T Welch Date: Fri, 13 Nov 2009 16:41:00 +0000 (-0800) Subject: arm_jtag_t -> struct arm_jtag X-Git-Tag: v0.4.0-rc1~686 X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=056fcdb540f0ab9a404f3b5de72fd707eb146603 arm_jtag_t -> struct arm_jtag Remove misleading typedef and redundant suffix from struct arm_jtag. --- diff --git a/src/flash/ocl.c b/src/flash/ocl.c index 83c8fcf79a..14b3e7c2b6 100644 --- a/src/flash/ocl.c +++ b/src/flash/ocl.c @@ -28,7 +28,7 @@ struct ocl_priv { - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; unsigned int buflen; unsigned int bufalign; }; diff --git a/src/flash/str9xpec.c b/src/flash/str9xpec.c index ad51cf191e..c553cdce52 100644 --- a/src/flash/str9xpec.c +++ b/src/flash/str9xpec.c @@ -240,7 +240,7 @@ FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command) struct str9xpec_flash_controller *str9xpec_info; armv4_5_common_t *armv4_5 = NULL; struct arm7_9_common *arm7_9 = NULL; - arm_jtag_t *jtag_info = NULL; + struct arm_jtag *jtag_info = NULL; if (argc < 6) { diff --git a/src/target/arm720t.c b/src/target/arm720t.c index a6641d0932..8ef7114e63 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -43,7 +43,7 @@ static int arm720t_scan_cp15(target_t *target, { int retval; struct arm720t_common *arm720t = target_to_arm720(target); - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; struct scan_field fields[2]; uint8_t out_buf[4]; uint8_t instruction_buf = instruction; @@ -414,7 +414,7 @@ COMMAND_HANDLER(arm720t_handle_cp15_command) int retval; target_t *target = get_current_target(cmd_ctx); struct arm720t_common *arm720t = target_to_arm720(target); - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; retval = arm720t_verify_pointer(cmd_ctx, arm720t); if (retval != ERROR_OK) diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 3894f850cb..65f2687543 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -703,7 +703,7 @@ int arm7_9_execute_sys_speed(struct target_s *target) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ @@ -756,7 +756,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) static uint8_t check_value[4], check_mask[4]; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ @@ -797,7 +797,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t *data; int retval = ERROR_OK; uint32_t i; @@ -833,7 +833,7 @@ int arm7_9_handle_target_request(void *priv) if (!target_was_examined(target)) return ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; if (!target->dbg_msg_enabled) @@ -1748,7 +1748,7 @@ int arm7_9_restore_context(target_t *target) int arm7_9_restart_core(struct target_s *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* set RESTART instruction */ jtag_set_end_state(TAP_IDLE); diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h index 2059bd0651..ca73997e14 100644 --- a/src/target/arm7_9_common.h +++ b/src/target/arm7_9_common.h @@ -42,7 +42,7 @@ struct arm7_9_common struct arm armv4_5_common; uint32_t common_magic; - arm_jtag_t jtag_info; /**< JTAG information for target */ + struct arm_jtag jtag_info; /**< JTAG information for target */ reg_cache_t *eice_cache; /**< Embedded ICE register cache */ uint32_t arm_bkpt; /**< ARM breakpoint instruction */ diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 2614d9e421..dc2cfbd35e 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -96,7 +96,7 @@ static int arm7tdmi_examine_debug_reason(target_t *target) static const int arm7tdmi_num_bits[] = {1, 32}; -static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, uint32_t out, int breakpoint) +static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint) { uint32_t values[2]={breakpoint, flip_u32(out, 32)}; @@ -116,7 +116,7 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, uint32_t out * * FIXME remove the unused "deprecated" parameter */ -static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, +static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t out, uint32_t *deprecated, int breakpoint) { jtag_set_end_state(TAP_DRPAUSE); @@ -127,7 +127,7 @@ static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, } /* clock the target, reading the databus */ -static int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in) +static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) { int retval = ERROR_OK; struct scan_field fields[2]; @@ -213,7 +213,7 @@ static int arm7endianness(jtag_callback_data_t arg, * the *in pointer points to a buffer where elements of 'size' bytes * are stored in big (be == 1) or little (be == 0) endianness */ -static int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, +static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, void *in, int size, int be) { int retval = ERROR_OK; @@ -267,7 +267,7 @@ static void arm7tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* save r0 before using it and put system in ARM state * to allow common handling of ARM and THUMB debugging */ @@ -324,7 +324,7 @@ static void arm7tdmi_read_core_regs(target_t *target, { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -349,7 +349,7 @@ static void arm7tdmi_read_core_regs_target_buffer(target_t *target, { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; uint16_t *buf_u16 = buffer; @@ -389,7 +389,7 @@ static void arm7tdmi_read_core_regs_target_buffer(target_t *target, static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* MRS r0, cpsr */ arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0); @@ -407,7 +407,7 @@ static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -437,7 +437,7 @@ static void arm7tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -456,7 +456,7 @@ static void arm7tdmi_write_core_regs(target_t *target, { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -480,7 +480,7 @@ static void arm7tdmi_write_core_regs(target_t *target, static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load-multiple into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -491,7 +491,7 @@ static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask) static void arm7tdmi_load_hword_reg(target_t *target, int num) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load half-word into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -502,7 +502,7 @@ static void arm7tdmi_load_hword_reg(target_t *target, int num) static void arm7tdmi_load_byte_reg(target_t *target, int num) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load byte into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -513,7 +513,7 @@ static void arm7tdmi_load_byte_reg(target_t *target, int num) static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store-multiple into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -524,7 +524,7 @@ static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask) static void arm7tdmi_store_hword_reg(target_t *target, int num) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store half-word into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -535,7 +535,7 @@ static void arm7tdmi_store_hword_reg(target_t *target, int num) static void arm7tdmi_store_byte_reg(target_t *target, int num) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store byte into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -546,7 +546,7 @@ static void arm7tdmi_store_byte_reg(target_t *target, int num) static void arm7tdmi_write_pc(target_t *target, uint32_t pc) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -571,7 +571,7 @@ static void arm7tdmi_write_pc(target_t *target, uint32_t pc) static void arm7tdmi_branch_resume(target_t *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0); @@ -581,7 +581,7 @@ static void arm7tdmi_branch_resume_thumb(target_t *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; LOG_DEBUG("-"); @@ -665,7 +665,7 @@ int arm7tdmi_examine(struct target_s *target) if (arm7_9->armv4_5_common.etm) { - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->armv4_5_common.etm); arm7_9->armv4_5_common.etm->reg_cache = (*cache_p)->next; diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 22f7b6309d..2fe50a132f 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -55,7 +55,7 @@ static int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value) { struct arm920t_common *arm920t = target_to_arm920(target); - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; struct scan_field fields[4]; uint8_t access_type_buf = 1; uint8_t reg_addr_buf = reg_addr & 0x3f; @@ -107,7 +107,7 @@ static int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value) { struct arm920t_common *arm920t = target_to_arm920(target); - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; struct scan_field fields[4]; uint8_t access_type_buf = 1; uint8_t reg_addr_buf = reg_addr & 0x3f; @@ -156,7 +156,7 @@ static int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, { int retval; struct arm920t_common *arm920t = target_to_arm920(target); - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; struct scan_field fields[4]; uint8_t access_type_buf = 0; /* interpreted access */ uint8_t reg_addr_buf = 0x0; diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 9133bd9e90..9ae19a878e 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -52,7 +52,7 @@ static int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); struct scan_field fields[4]; uint8_t address_buf[2]; @@ -144,7 +144,7 @@ static int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); struct scan_field fields[4]; uint8_t value_buf[4]; diff --git a/src/target/arm966e.c b/src/target/arm966e.c index 524c3625f1..dee9f612ad 100644 --- a/src/target/arm966e.c +++ b/src/target/arm966e.c @@ -71,7 +71,7 @@ static int arm966e_read_cp15(target_t *target, int reg_addr, uint32_t *value) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; struct scan_field fields[3]; uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 0; @@ -123,7 +123,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, uint32_t value) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; struct scan_field fields[3]; uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 1; diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 985b7ff7cc..897563ccaa 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -124,7 +124,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) /* put an instruction in the ARM9TDMI pipeline or write the data bus, * and optionally read data */ -int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, +int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed) { int retval = ERROR_OK; @@ -198,7 +198,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, } /* just read data (instruction and data-out = don't care) */ -int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in) +int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) { int retval = ERROR_OK;; struct scan_field fields[3]; @@ -269,7 +269,7 @@ static int arm9endianness(jtag_callback_data_t arg, * the *in pointer points to a buffer where elements of 'size' bytes * are stored in big (be == 1) or little (be == 0) endianness */ -int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, +int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, void *in, int size, int be) { int retval = ERROR_OK; @@ -330,7 +330,7 @@ static void arm9tdmi_change_to_arm(target_t *target, { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* save r0 before using it and put system in ARM state * to allow common handling of ARM and THUMB debugging */ @@ -384,7 +384,7 @@ void arm9tdmi_read_core_regs(target_t *target, { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -409,7 +409,7 @@ static void arm9tdmi_read_core_regs_target_buffer(target_t *target, { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; uint16_t *buf_u16 = buffer; @@ -447,7 +447,7 @@ static void arm9tdmi_read_core_regs_target_buffer(target_t *target, static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* MRS r0, cpsr */ arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); @@ -469,7 +469,7 @@ static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -504,7 +504,7 @@ static void arm9tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -530,7 +530,7 @@ void arm9tdmi_write_core_regs(target_t *target, { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -554,7 +554,7 @@ void arm9tdmi_write_core_regs(target_t *target, void arm9tdmi_load_word_regs(target_t *target, uint32_t mask) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load-multiple into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0); @@ -564,7 +564,7 @@ void arm9tdmi_load_word_regs(target_t *target, uint32_t mask) void arm9tdmi_load_hword_reg(target_t *target, int num) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load half-word into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0); @@ -574,7 +574,7 @@ void arm9tdmi_load_hword_reg(target_t *target, int num) void arm9tdmi_load_byte_reg(target_t *target, int num) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load byte into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0); @@ -584,7 +584,7 @@ void arm9tdmi_load_byte_reg(target_t *target, int num) void arm9tdmi_store_word_regs(target_t *target, uint32_t mask) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store-multiple into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0); @@ -594,7 +594,7 @@ void arm9tdmi_store_word_regs(target_t *target, uint32_t mask) void arm9tdmi_store_hword_reg(target_t *target, int num) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store half-word into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0); @@ -604,7 +604,7 @@ void arm9tdmi_store_hword_reg(target_t *target, int num) void arm9tdmi_store_byte_reg(target_t *target, int num) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store byte into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0); @@ -614,7 +614,7 @@ void arm9tdmi_store_byte_reg(target_t *target, int num) static void arm9tdmi_write_pc(target_t *target, uint32_t pc) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -638,7 +638,7 @@ static void arm9tdmi_write_pc(target_t *target, uint32_t pc) void arm9tdmi_branch_resume(target_t *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); @@ -650,7 +650,7 @@ static void arm9tdmi_branch_resume_thumb(target_t *target) struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* LDMIA r0-15, [r0] at debug speed @@ -760,7 +760,7 @@ int arm9tdmi_examine(struct target_s *target) if (arm7_9->armv4_5_common.etm) { - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->armv4_5_common.etm); arm7_9->armv4_5_common.etm->reg_cache = (*cache_p)->next; diff --git a/src/target/arm9tdmi.h b/src/target/arm9tdmi.h index 61d1ccf53c..552231791c 100644 --- a/src/target/arm9tdmi.h +++ b/src/target/arm9tdmi.h @@ -58,10 +58,10 @@ int arm9tdmi_init_arch_info(target_t *target, struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap); int arm9tdmi_register_commands(struct command_context_s *cmd_ctx); -int arm9tdmi_clock_out(arm_jtag_t *jtag_info, +int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed); -int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in); -int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, +int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in); +int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, void *in, int size, int be); void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]); diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 3323485eaa..751020fbc8 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -73,7 +73,7 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address /* Scan out and in from target ordered uint8_t buffers */ int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack) { - arm_jtag_t *jtag_info = swjdp->jtag_info; + struct arm_jtag *jtag_info = swjdp->jtag_info; struct scan_field fields[2]; uint8_t out_addr_buf; @@ -103,7 +103,7 @@ int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr /* Scan out and in from host ordered uint32_t variables */ int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack) { - arm_jtag_t *jtag_info = swjdp->jtag_info; + struct arm_jtag *jtag_info = swjdp->jtag_info; struct scan_field fields[2]; uint8_t out_value_buf[4]; uint8_t out_addr_buf; diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 5f2c96977e..486d29f407 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -79,12 +79,12 @@ struct swjdp_reg { int addr; - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; }; struct swjdp_common { - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; /* Control config */ uint32_t dp_ctrl_stat; /* Support for several AP's in one DAP */ diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c index 4b5bd3929f..e7dbea4fa7 100644 --- a/src/target/arm_jtag.c +++ b/src/target/arm_jtag.c @@ -31,7 +31,7 @@ #define _ARM_JTAG_SCAN_N_CHECK_ #endif -int arm_jtag_set_instr(arm_jtag_t *jtag_info, uint32_t new_instr, void *no_verify_capture) +int arm_jtag_set_instr(struct arm_jtag *jtag_info, uint32_t new_instr, void *no_verify_capture) { struct jtag_tap *tap; tap = jtag_info->tap; @@ -66,7 +66,7 @@ int arm_jtag_set_instr(arm_jtag_t *jtag_info, uint32_t new_instr, void *no_veri return ERROR_OK; } -int arm_jtag_scann(arm_jtag_t *jtag_info, uint32_t new_scan_chain) +int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain) { int retval = ERROR_OK; if (jtag_info->cur_scan_chain != new_scan_chain) @@ -96,7 +96,7 @@ int arm_jtag_scann(arm_jtag_t *jtag_info, uint32_t new_scan_chain) int arm_jtag_reset_callback(enum jtag_event event, void *priv) { - arm_jtag_t *jtag_info = priv; + struct arm_jtag *jtag_info = priv; if (event == JTAG_TRST_ASSERTED) { @@ -106,7 +106,7 @@ int arm_jtag_reset_callback(enum jtag_event event, void *priv) return ERROR_OK; } -int arm_jtag_setup_connection(arm_jtag_t *jtag_info) +int arm_jtag_setup_connection(struct arm_jtag *jtag_info) { jtag_info->scann_instr = 0x2; jtag_info->cur_scan_chain = 0; diff --git a/src/target/arm_jtag.h b/src/target/arm_jtag.h index 5b882c687e..b1905a3dce 100644 --- a/src/target/arm_jtag.h +++ b/src/target/arm_jtag.h @@ -25,7 +25,7 @@ #include "jtag.h" -typedef struct arm_jtag_s +struct arm_jtag { struct jtag_tap *tap; @@ -34,12 +34,12 @@ typedef struct arm_jtag_s uint32_t cur_scan_chain; uint32_t intest_instr; -} arm_jtag_t; +}; -int arm_jtag_set_instr(arm_jtag_t *jtag_info, +int arm_jtag_set_instr(struct arm_jtag *jtag_info, uint32_t new_instr, void *verify_capture); -int arm_jtag_scann(arm_jtag_t *jtag_info, uint32_t new_scan_chain); -int arm_jtag_setup_connection(arm_jtag_t *jtag_info); +int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain); +int arm_jtag_setup_connection(struct arm_jtag *jtag_info); /* JTAG buffers to host, be and le buffers, flipping variants */ int arm_jtag_buf_to_u32_flip(uint8_t *in_buf, void *priv, struct scan_field_s *field); diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h index 39d4e77af2..02cf797f5b 100644 --- a/src/target/cortex_a8.h +++ b/src/target/cortex_a8.h @@ -103,7 +103,7 @@ typedef struct cortex_a8_wrp_s typedef struct cortex_a8_common_s { int common_magic; - arm_jtag_t jtag_info; + struct arm_jtag jtag_info; /* Context information */ uint32_t cpudbg_dscr; diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h index 9ad9dca74e..5b1d5eaea3 100644 --- a/src/target/cortex_m3.h +++ b/src/target/cortex_m3.h @@ -139,7 +139,7 @@ typedef struct cortex_m3_dwt_comparator_s typedef struct cortex_m3_common_s { int common_magic; - arm_jtag_t jtag_info; + struct arm_jtag jtag_info; /* Context information */ uint32_t dcb_dhcsr; diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 4a60960b9b..3f0048e4d4 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -170,7 +170,7 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); reg_t *reg_list = NULL; embeddedice_reg_t *arch_info = NULL; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int num_regs = ARRAY_SIZE(eice_regs); int i; int eice_version = 0; @@ -396,7 +396,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, * functional clock, so the 50+ JTAG clocks needed to receive the word * allow hundreds of instruction cycles (per word) in the target. */ -int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) +int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) { struct scan_field fields[3]; uint8_t field1_out[1]; @@ -517,7 +517,7 @@ void embeddedice_store_reg(reg_t *reg) * functional clock, so the 50+ JTAG clocks needed to receive the word * allow hundreds of instruction cycles (per word) in the target. */ -int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) +int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) { struct scan_field fields[3]; uint8_t field0_out[4]; @@ -562,7 +562,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) /** * Poll DCC control register until read or write handshake completes. */ -int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout) +int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout) { struct scan_field fields[3]; uint8_t field0_in[4]; diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h index 4e5639cff6..113a8fe92e 100644 --- a/src/target/embeddedice.h +++ b/src/target/embeddedice.h @@ -90,7 +90,7 @@ enum typedef struct embeddedice_reg_s { int addr; - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; } embeddedice_reg_t; reg_cache_t* embeddedice_build_reg_cache(target_t *target, @@ -108,10 +108,10 @@ void embeddedice_store_reg(reg_t *reg); void embeddedice_set_reg(reg_t *reg, uint32_t value); int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf); -int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size); -int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size); +int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size); +int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size); -int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout); +int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout); /* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of * embeddedice_write_reg diff --git a/src/target/etm.c b/src/target/etm.c index 01a9b714bd..864346326e 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -247,7 +247,7 @@ static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id) return NULL; } -static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info, +static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info, reg_cache_t *cache, etm_reg_t *ereg, const struct etm_reg_info *r, unsigned nreg) { @@ -280,7 +280,7 @@ static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info, } reg_cache_t *etm_build_reg_cache(target_t *target, - arm_jtag_t *jtag_info, etm_context_t *etm_ctx) + struct arm_jtag *jtag_info, etm_context_t *etm_ctx) { reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); reg_t *reg_list = NULL; diff --git a/src/target/etm.h b/src/target/etm.h index ead45855e9..d6e12103df 100644 --- a/src/target/etm.h +++ b/src/target/etm.h @@ -75,7 +75,7 @@ typedef struct etm_reg_s { uint32_t value; const struct etm_reg_info *reg_info; - arm_jtag_t *jtag_info; + struct arm_jtag *jtag_info; } etm_reg_t; typedef enum @@ -208,7 +208,7 @@ typedef enum } etmv1_branch_reason_t; reg_cache_t* etm_build_reg_cache(target_t *target, - arm_jtag_t *jtag_info, etm_context_t *etm_ctx); + struct arm_jtag *jtag_info, etm_context_t *etm_ctx); int etm_setup(target_t *target); diff --git a/src/target/fa526.c b/src/target/fa526.c index 4aa5e3ab82..3b884c69d7 100644 --- a/src/target/fa526.c +++ b/src/target/fa526.c @@ -44,7 +44,7 @@ static void fa526_read_core_regs(target_t *target, { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -71,7 +71,7 @@ static void fa526_read_core_regs_target_buffer(target_t *target, { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; uint16_t *buf_u16 = buffer; @@ -111,7 +111,7 @@ static void fa526_read_core_regs_target_buffer(target_t *target, static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* MRS r0, cpsr */ arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); @@ -136,7 +136,7 @@ static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -173,7 +173,7 @@ static void fa526_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -201,7 +201,7 @@ static void fa526_write_core_regs(target_t *target, { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -227,7 +227,7 @@ static void fa526_write_core_regs(target_t *target, static void fa526_write_pc(target_t *target, uint32_t pc) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 73c0e57ca8..0439f813d2 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -69,7 +69,7 @@ int feroceon_assert_reset(target_t *target) return arm7_9_assert_reset(target); } -int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr) +int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr) { struct scan_field fields[3]; uint8_t out_buf[4]; @@ -112,7 +112,7 @@ void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) { armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* * save r0 before using it and put system in ARM state @@ -159,7 +159,7 @@ void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg int i; armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -178,7 +178,7 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void int i; armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; uint16_t *buf_u16 = buffer; @@ -214,7 +214,7 @@ void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -237,7 +237,7 @@ void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -278,7 +278,7 @@ void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps { armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -296,7 +296,7 @@ void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg int i; armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -315,7 +315,7 @@ void feroceon_branch_resume(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -332,7 +332,7 @@ void feroceon_branch_resume_thumb(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); @@ -365,7 +365,7 @@ int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CR { armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int err; arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0); @@ -387,7 +387,7 @@ int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t C { armv4_5_common_t *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);