From: Antonio Borneo Date: Fri, 21 Sep 2018 13:52:02 +0000 (+0200) Subject: target/arm_adi_v5: fix sync CSW cache on apreg write X-Git-Tag: v0.11.0-rc1~972 X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=1ba715422fba733bb5426ea887368e2dcf371b91;ds=sidebyside target/arm_adi_v5: fix sync CSW cache on apreg write Commit 0057c71ab6b81d0679b232318fc5f84b4becc471 updates the OpenOCD cached values of CSW and TAR registers if these registers are modified by an apreg command. The condition to force the update of CSW cache is incorrect and it will erase the default CSW value. Moreover, calling mem_ap_setup_csw() does not honor the value requested in the apreg command because such value is incorrectly bitwise or-ed with csw_default. Fix it by updating csw_value, instead of erasing csw_default, and writing directly in CSW register the new value from the command line. Change-Id: I40273cb64d22ccfb9b6d3499bd39b586eb60de38 Fixes: 0057c71ab6b8 ("target/arm_adi_v5: sync CSW and TAR cache on apreg write") Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/4679 Tested-by: jenkins Reviewed-by: Christopher Head Reviewed-by: Tomas Vanek --- diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index d9f3bd74f8..e62ac07577 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1738,8 +1738,10 @@ COMMAND_HANDLER(dap_apreg_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); switch (reg) { case MEM_AP_REG_CSW: - ap->csw_default = 0; /* invalid, force write */ - retval = mem_ap_setup_csw(ap, value); + ap->csw_value = 0; /* invalid, in case write fails */ + retval = dap_queue_ap_write(ap, reg, value); + if (retval == ERROR_OK) + ap->csw_value = value; break; case MEM_AP_REG_TAR: ap->tar_valid = false; /* invalid, force write */