From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Tue, 15 Sep 2009 09:41:09 +0000 (+0000)
Subject: added embedded ice programming while srst is asserted todo item
X-Git-Tag: v0.3.0-rc0~241
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=379386743ac6bded1cefe8f8bfbaf2d6a5498493

added embedded ice programming while srst is asserted todo item

git-svn-id: svn://svn.berlios.de/openocd/trunk@2710 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---

diff --git a/TODO b/TODO
index 7301e981f8..283ed5f3a9 100644
--- a/TODO
+++ b/TODO
@@ -114,6 +114,10 @@ Once the above are completed:
   https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html
 - regression: "reset halt" between 729(works) and 788(fails): @par
 https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
+- ARM7/9:
+  - add reset option to allow programming embedded ice while srst is asserted.
+  Some CPUs will gate the JTAG clock when srst is asserted and in this case,
+  it is necessary to program embedded ice and then assert srst afterwards.
 - ARM923EJS:
   - reset run/halt/step is not robust; needs testing to map out problems.
 - ARM11 improvements (MB?)