From: Salvador Arroyo Date: Sun, 5 Aug 2012 09:18:27 +0000 (+0200) Subject: Severe bug in Pracc code X-Git-Tag: v0.6.0-rc2~19 X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=47728f92159e11668a4aa1ec3d2713ee38a87192 Severe bug in Pracc code The function wait_for_pracc_rw() fails if Pracc bit is 0. The variable ejtag_ctrl is loaded with the content of the control register in the first scan. In the second scan Pracc bit is scanned out as 0, letting the proccesor go. The result is unpredictable. All the strange data corruption when scanning at certain frequencies, or the strange delays needed when entering or leaving fasdata area are retated to this bug. Now the code works at any scan frequency, tested up to 15000Khz and indepently of processor speed, tested at 31.25Khz and 4/8Mhz. Change-Id: Iedfd81d06d6af4bc738a521f720e42323025b268 Signed-off-by: Salvador Arroyo Reviewed-on: http://openocd.zylin.com/769 Tested-by: jenkins Reviewed-by: Freddie Chopin --- diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index 92b8699e0e..bae436784a 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -125,9 +125,9 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) /* wait for the PrAcc to become "1" */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); - ejtag_ctrl = ejtag_info->ejtag_ctrl; while (1) { + ejtag_ctrl = ejtag_info->ejtag_ctrl; retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); if (retval != ERROR_OK) return retval;