From: Paul Fertser Date: Thu, 9 Apr 2015 12:20:22 +0000 (+0300) Subject: tcl/target/stm32f3: fix reset init for stlink X-Git-Tag: v0.9.0-rc1~18 X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=68921d231655be696d6aad5ca7abe26cb5f17104;ds=sidebyside tcl/target/stm32f3: fix reset init for stlink Use mmw to manipulate only selected bits of the word. msb and mwb verify the memory location and may error on PLLRDY set as a result of PLLON written. Change-Id: I9a4c1e58f002a1e5e99be1bd34aac27ba65d111d Reported-by: Uwe Bonnes Signed-off-by: Paul Fertser Reviewed-on: http://openocd.zylin.com/2702 Tested-by: jenkins --- diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg index f3c22af7ae..ca8e6e1d8c 100644 --- a/tcl/target/stm32f3x.cfg +++ b/tcl/target/stm32f3x.cfg @@ -104,11 +104,11 @@ proc stm32f3x_default_examine_end {} { proc stm32f3x_default_reset_init {} { # Configure PLL to boost clock to HSI x 8 (64 MHz) - mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] - mwh 0x40021002 0x0100 ;# RCC_CR[31:16] = PLLON - mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] - sleep 10 ;# Wait for PLL to lock - mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1] + mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] + mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON + mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] + sleep 10 ;# Wait for PLL to lock + mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] # Boost JTAG frequency adapter_khz 8000