From: Nishanth Menon <nm@ti.com>
Date: Thu, 14 Sep 2023 12:49:02 +0000 (-0500)
Subject: tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=9c7c5ca4eb04b110f66b4e3c2494a1d55a962b33

tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access

While we can read and write from memory from the view of various
processors, all K3 debug systems have a AXI Access port that allows
us to directly access memory from debug interface. This port is
especially useful in the following scenarios:

1. Debug cache related behavior on processors as this provides a
   direct bypass path.
2. Processor has crashed or inaccessible for some reason (low power
   state etc.)
3. Scenarios prior to the processor getting active.
4. Debug MMU or address translation issues (example: TI's Region
   Address Table {RAT} translation table used to physically map
   SoC address space into R5/M4F processor address space)

The AXI-AP port is the same for all processors in TI's K3 family.

To prevent a circular-loop scenario for axi-ap accessing debug memory
with dmem (direct memory access debug), enable this only when dmem is
disabled.

Change-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b
Reported-by: Dubravko Srsan <dubravko.srsan@dolotron.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7899
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 090f08209a..1cd85eec3e 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -417,4 +417,7 @@ if { 0 == [string compare [adapter name] dmem ] } {
 	} else {
 		puts "ERROR: ${SOC} data is missing to support dmem access!"
 	}
+} else {
+	# AXI AP access port for SoC address map
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num 2
 }