From: Antonio Borneo <borneo.antonio@gmail.com>
Date: Sat, 11 Jul 2020 22:00:47 +0000 (+0200)
Subject: flash: fix typos and duplicated words
X-Git-Tag: v0.11.0-rc1~177
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=9db3e9879db3d89984eea80dc6fd9b1c3c269e58

flash: fix typos and duplicated words

Fix typos and duplicated words in comments and strings.

Change-Id: I64282c7018462deefeeb8e5f4d0d81942425b3fc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5758
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
---

diff --git a/src/flash/nand/driver.h b/src/flash/nand/driver.h
index 2182a77271..690ee91ec8 100644
--- a/src/flash/nand/driver.h
+++ b/src/flash/nand/driver.h
@@ -94,7 +94,7 @@ typedef int (*nand_driver_walker_t)(struct nand_flash_controller *c, void *);
  * Walk the list of drivers, encapsulating the data structure type.
  * Application state/context can be passed through the @c x pointer.
  * @param f The callback function to invoke for each function.
- * @param x For use as private data storate, passed directly to @c f.
+ * @param x For use as private data storage, passed directly to @c f.
  * @returns ERROR_OK if successful, or the non-zero return value of @c f.
  * This allows a walker to terminate the loop early.
  */
diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c
index f65f957bf2..1279e45a4f 100644
--- a/src/flash/nand/fileio.c
+++ b/src/flash/nand/fileio.c
@@ -206,7 +206,7 @@ int nand_fileio_read(struct nand_device *nand, struct nand_fileio_state *s)
 	} else if (s->oob_format & NAND_OOB_SW_ECC_KW)   {
 		/*
 		 * In this case eccpos is not used as
-		 * the ECC data is always stored contigously
+		 * the ECC data is always stored contiguously
 		 * at the end of the OOB area.  It consists
 		 * of 10 bytes per 512-byte data block.
 		 */
diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c
index 389c18ac4d..97bd7a351e 100644
--- a/src/flash/nand/lpc3180.c
+++ b/src/flash/nand/lpc3180.c
@@ -232,7 +232,7 @@ static int lpc3180_init(struct nand_device *nand)
 		/* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
 		target_write_u32(target, 0x400040c8, 0x05);
 
-		/* after reset set other registers of SLC so reset calling is here at the begining*/
+		/* after reset set other registers of SLC so reset calling is here at the beginning */
 		lpc3180_reset(nand);
 
 		/* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,
diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c
index 058d9a50ee..d516522f3d 100644
--- a/src/flash/nand/lpc32xx.c
+++ b/src/flash/nand/lpc32xx.c
@@ -42,7 +42,7 @@ extern int nand_correct_data(struct nand_device *nand, u_char *dat,
  * read/write data to the SLC controller.
  * - DMA descriptors will be put at start of working area,
  * - Hardware generated ECC will be stored at ECC_OFFS
- * - OOB wil be read/written from/to SPARE_OFFS
+ * - OOB will be read/written from/to SPARE_OFFS
  * - Actual page data will be read from/to DATA_OFFS
  * There are unused holes between the used areas.
  */
@@ -317,7 +317,7 @@ static int lpc32xx_init(struct nand_device *nand)
 		}
 
 		/* after reset set other registers of SLC,
-		 * so reset calling is here at the begining
+		 * so reset calling is here at the beginning
 		 */
 		retval = lpc32xx_reset(nand);
 		if (ERROR_OK != retval)
@@ -769,7 +769,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 2. Copy generated ECC data from Register to Spare Area
 	 * 3. X'fer next 256 bytes of data from Memory to Flash.
 	 * 4. Copy generated ECC data from Register to Spare Area.
-	 * 5. X'fer 16 byets of Spare area from Memory to Flash.
+	 * 5. X'fer 16 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Small Block NAND
 	 * ----------------------------------------------------------
 	 * 1. X'fer 256 bytes of data from Flash to Memory.
@@ -779,13 +779,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 	 * Write Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Write Operations repeate for four times
+	 * 1. Steps(1-4) of Write Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Read Operations repeate for four times
+	 * 1. Steps(1-4) of Read Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
@@ -842,7 +842,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 2. Copy generated ECC data from Register to Spare Area
 	 * 3. X'fer next 256 bytes of data from Memory to Flash.
 	 * 4. Copy generated ECC data from Register to Spare Area.
-	 * 5. X'fer 16 byets of Spare area from Memory to Flash.
+	 * 5. X'fer 16 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Small Block NAND
 	 * ----------------------------------------------------------
 	 * 1. X'fer 256 bytes of data from Flash to Memory.
@@ -852,13 +852,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 	 * Write Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Write Operations repeate for four times
+	 * 1. Steps(1-4) of Write Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Read Operations repeate for four times
+	 * 1. Steps(1-4) of Read Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
@@ -1044,7 +1044,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 
 	target_mem_base = pworking_area->address;
 	/*
-	 * Skip writting page which has all 0xFF data as this will
+	 * Skip writing page which has all 0xFF data as this will
 	 * generate 0x0 value.
 	 */
 	if (data && !oob) {
@@ -1102,7 +1102,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 			return retval;
 		}
 
-		/* Write first decriptor to DMA controller */
+		/* Write first descriptor to DMA controller */
 		retval = target_write_memory(target, 0x31000100, 4,
 				sizeof(dmac_ll_t) / 4,
 				(uint8_t *)dmalist);
@@ -1159,7 +1159,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 		return retval;
 	}
 
-	/* Write OOB decriptor to DMA controller */
+	/* Write OOB descriptor to DMA controller */
 	retval = target_write_memory(target, 0x31000100, 4,
 			sizeof(dmac_ll_t) / 4,
 			(uint8_t *)(&dmalist[nll-1]));
@@ -1487,7 +1487,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand,
 		return retval;
 	}
 
-	/* Write first decriptor to DMA controller */
+	/* Write first descriptor to DMA controller */
 	retval = target_write_memory(target, 0x31000100, 4,
 			sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
 	if (ERROR_OK != retval) {
diff --git a/src/flash/nand/mx3.c b/src/flash/nand/mx3.c
index da141b7423..abeaf159cc 100644
--- a/src/flash/nand/mx3.c
+++ b/src/flash/nand/mx3.c
@@ -149,7 +149,7 @@ static int imx31_init(struct nand_device *nand)
 		uint32_t gpr_register_content;
 		target_read_u32(target, MX3_GPR, &gpr_register_content);
 		if (gpr_register_content & 0x00000060) {
-			LOG_ERROR("pins mode overrided by GPR");
+			LOG_ERROR("pins mode overridden by GPR");
 			return ERROR_FAIL;
 		}
 	}
@@ -414,10 +414,10 @@ static int imx31_write_page(struct nand_device *nand, uint32_t page,
 		if (oob) {
 			if (mx3_nf_info->flags.hw_ecc_enabled) {
 				/*
-				 * part of spare block will be overrided by hardware
+				 * part of spare block will be overridden by hardware
 				 * ECC generator
 				 */
-				LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
+				LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
 			}
 			target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
 		}
@@ -530,7 +530,7 @@ static int initialize_nf_controller(struct nand_device *nand)
 	struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 	struct target *target = nand->target;
 	/*
-	* resets NAND flash controller in zero time ? I dont know.
+	* resets NAND flash controller in zero time ? I don't know.
 	*/
 	target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
 	{
@@ -680,18 +680,18 @@ static int do_data_output(struct nand_device *nand)
 				target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
 				switch (ecc_status & 0x000c) {
 				case 1 << 2:
-					LOG_DEBUG("main area readed with 1 (correctable) error");
+					LOG_DEBUG("main area read with 1 (correctable) error");
 					break;
 				case 2 << 2:
-					LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+					LOG_DEBUG("main area read with more than 1 (incorrectable) error");
 					return ERROR_NAND_OPERATION_FAILED;
 				}
 				switch (ecc_status & 0x0003) {
 				case 1:
-					LOG_DEBUG("spare area readed with 1 (correctable) error");
+					LOG_DEBUG("spare area read with 1 (correctable) error");
 					break;
 				case 2:
-					LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+					LOG_DEBUG("main area read with more than 1 (incorrectable) error");
 					return ERROR_NAND_OPERATION_FAILED;
 				}
 			}
diff --git a/src/flash/nand/mxc.c b/src/flash/nand/mxc.c
index ee093c056d..bc2ae9324b 100644
--- a/src/flash/nand/mxc.c
+++ b/src/flash/nand/mxc.c
@@ -136,7 +136,7 @@ NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
 		(nand->target->endianness == TARGET_LITTLE_ENDIAN);
 
 	/*
-	 * should factory bad block indicator be swaped
+	 * should factory bad block indicator be swapped
 	 * as a workaround for how the nfc handles pages.
 	 */
 	if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
@@ -181,7 +181,7 @@ static const struct command_registration mxc_sub_command_handlers[] = {
 		.name = "biswap",
 		.mode = COMMAND_EXEC,
 		.handler = handle_mxc_biswap_command,
-		.help = "Turns on/off bad block information swaping from main area, "
+		.help = "Turns on/off bad block information swapping from main area, "
 			"without parameter query status.",
 		.usage = "bank_id ['enable'|'disable']",
 	},
@@ -400,7 +400,7 @@ static int mxc_command(struct nand_device *nand, uint8_t command)
 			mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 			break;
 		default:
-			/* Ohter command use the default 'One page data out' FDO */
+			/* Other command use the default 'One page data out' FDO */
 			mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 			break;
 	}
@@ -502,10 +502,10 @@ static int mxc_write_page(struct nand_device *nand, uint32_t page,
 	if (oob) {
 		if (mxc_nf_info->flags.hw_ecc_enabled) {
 			/*
-			 * part of spare block will be overrided by hardware
+			 * part of spare block will be overridden by hardware
 			 * ECC generator
 			 */
-			LOG_DEBUG("part of spare block will be overrided "
+			LOG_DEBUG("part of spare block will be overridden "
 				"by hardware ECC generator");
 		}
 		if (nfc_is_v1())
@@ -710,7 +710,7 @@ static int initialize_nf_controller(struct nand_device *nand)
 	uint16_t work_mode = 0;
 	uint16_t temp;
 	/*
-	 * resets NAND flash controller in zero time ? I dont know.
+	 * resets NAND flash controller in zero time ? I don't know.
 	 */
 	target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
 	if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index c8c4afe1fb..1e2a074aa8 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -21,7 +21,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
 ****************************************************************************/
 
-/* Some of the the lower level code was based on code supplied by
+/* Some of the lower level code was based on code supplied by
  * ATMEL under this copyright. */
 
 /* BEGIN ATMEL COPYRIGHT */
@@ -3095,7 +3095,7 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
 }
 
 /**
- * Remove all chips from the internal list without distingushing which one
+ * Remove all chips from the internal list without distinguishing which one
  * is owned by this bank. This simplification works only for one shot
  * deallocation like current flash_free_all_banks()
  */
@@ -3398,7 +3398,7 @@ static int sam3_write(struct flash_bank *bank,
 	struct sam3_bank_private *pPrivate;
 	uint8_t *pagebuffer;
 
-	/* incase we bail further below, set this to null */
+	/* in case we bail further below, set this to null */
 	pagebuffer = NULL;
 
 	/* ignore dumb requests */
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index f2827496dc..4be3a5962a 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -22,7 +22,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
 ****************************************************************************/
 
-/* Some of the the lower level code was based on code supplied by
+/* Some of the lower level code was based on code supplied by
  * ATMEL under this copyright. */
 
 /* BEGIN ATMEL COPYRIGHT */
@@ -2509,7 +2509,7 @@ FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
 }
 
 /**
- * Remove all chips from the internal list without distingushing which one
+ * Remove all chips from the internal list without distinguishing which one
  * is owned by this bank. This simplification works only for one shot
  * deallocation like current flash_free_all_banks()
  */
@@ -2873,7 +2873,7 @@ static int sam4_write(struct flash_bank *bank,
 	struct sam4_bank_private *pPrivate;
 	uint8_t *pagebuffer;
 
-	/* incase we bail further below, set this to null */
+	/* in case we bail further below, set this to null */
 	pagebuffer = NULL;
 
 	/* ignore dumb requests */
diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index 7dfdf0d29b..59f5951ae4 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -254,7 +254,7 @@ static void at91sam7_read_clock_info(struct flash_bank *bank)
 		at91sam7_info->mck_freq = tmp;
 }
 
-/* Setup the timimg registers for nvbits or normal flash */
+/* Setup the timing registers for nvbits or normal flash */
 static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
 {
 	uint32_t fmr, fmcn = 0, fws = 0;
@@ -377,7 +377,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
 			/* re-calculate master clock frequency */
 			at91sam7_read_clock_info(t_bank);
 
-			/* no timming */
+			/* no timing */
 			at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 
 			/* check protect state */
@@ -415,7 +415,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
 			/* calculate master clock frequency */
 			at91sam7_read_clock_info(t_bank);
 
-			/* no timming */
+			/* no timing */
 			at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 
 			/* check protect state */
@@ -623,7 +623,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
 		/* calculate master clock frequency */
 		at91sam7_read_clock_info(t_bank);
 
-		/* no timming */
+		/* no timing */
 		at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 
 		/* check protect state */
diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index 0bd5f59950..63710d3e0b 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -41,7 +41,7 @@
 #define SAMD_NVMCTRL_CTRLA		0x00	/* NVM control A register */
 #define SAMD_NVMCTRL_CTRLB		0x04	/* NVM control B register */
 #define SAMD_NVMCTRL_PARAM		0x08	/* NVM parameters register */
-#define SAMD_NVMCTRL_INTFLAG	0x18	/* NVM Interupt Flag Status & Clear */
+#define SAMD_NVMCTRL_INTFLAG	0x18	/* NVM Interrupt Flag Status & Clear */
 #define SAMD_NVMCTRL_STATUS		0x18	/* NVM status register */
 #define SAMD_NVMCTRL_ADDR		0x1C	/* NVM address register */
 #define SAMD_NVMCTRL_LOCK		0x20	/* NVM Lock section register */
@@ -52,8 +52,8 @@
 /* NVMCTRL commands.  See Table 20-4 in 42129F–SAM–10/2013 */
 #define SAMD_NVM_CMD_ER		0x02		/* Erase Row */
 #define SAMD_NVM_CMD_WP		0x04		/* Write Page */
-#define SAMD_NVM_CMD_EAR	0x05		/* Erase Auxilary Row */
-#define SAMD_NVM_CMD_WAP	0x06		/* Write Auxilary Page */
+#define SAMD_NVM_CMD_EAR	0x05		/* Erase Auxiliary Row */
+#define SAMD_NVM_CMD_WAP	0x06		/* Write Auxiliary Page */
 #define SAMD_NVM_CMD_LR		0x40		/* Lock Region */
 #define SAMD_NVM_CMD_UR		0x41		/* Unlock Region */
 #define SAMD_NVM_CMD_SPRM	0x42		/* Set Power Reduction Mode */
diff --git a/src/flash/nor/atsame5.c b/src/flash/nor/atsame5.c
index ab79e8cf79..82306830a3 100644
--- a/src/flash/nor/atsame5.c
+++ b/src/flash/nor/atsame5.c
@@ -31,10 +31,10 @@
 #include <target/cortex_m.h>
 
 /* A note to prefixing.
- * Definitions and functions ingerited from at91samd.c without
- * any change retained the original prefix samd_ so they eventualy
+ * Definitions and functions inherited from at91samd.c without
+ * any change retained the original prefix samd_ so they eventually
  * may go to samd_common.h and .c
- * As currently there are olny 3 short functions identical with
+ * As currently there are only 3 short functions identical with
  * the original source, no common file was created. */
 
 #define SAME5_PAGES_PER_BLOCK	16
diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c
index 1ad37c1ab3..7db31f140f 100644
--- a/src/flash/nor/atsamv.c
+++ b/src/flash/nor/atsamv.c
@@ -25,7 +25,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
-/* Some of the the lower level code was based on code supplied by
+/* Some of the lower level code was based on code supplied by
  * ATMEL under this copyright. */
 
 /* BEGIN ATMEL COPYRIGHT */
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 9d2a53a6bc..887821b79c 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1178,7 +1178,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	 * r6: error test pattern
 	 */
 
-	/* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_intel_32.s for src */
 	static const uint32_t word_32_code[] = {
 		0xe4904004,	/* loop: ldr r4, [r0], #4 */
 		0xe5813000,	/*       str r3, [r1] */
@@ -1196,7 +1196,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 		0xeafffffe	/* done: b -2 */
 	};
 
-	/* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_intel_16.s for src */
 	static const uint32_t word_16_code[] = {
 		0xe0d040b2,	/* loop: ldrh r4, [r0], #2 */
 		0xe1c130b0,	/*       strh r3, [r1] */
@@ -1214,7 +1214,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 		0xeafffffe	/* done:	b -2 */
 	};
 
-	/* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_intel_8.s for src */
 	static const uint32_t word_8_code[] = {
 		0xe4d04001,	/* loop: ldrb r4, [r0], #1 */
 		0xe5c13000,	/*       strb r3, [r1] */
@@ -1249,7 +1249,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 
 	cfi_intel_clear_status_register(bank);
 
-	/* If we are setting up the write_algorith, we need target_code_src
+	/* If we are setting up the write_algorithm, we need target_code_src
 	 * if not we only need target_code_size. */
 
 	/* However, we don't want to create multiple code paths, so we
@@ -1364,7 +1364,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 		if (retval != ERROR_OK) {
 			cfi_intel_clear_status_register(bank);
 			LOG_ERROR(
-				"Execution of flash algorythm failed. Can't fall back. Please report.");
+				"Execution of flash algorithm failed. Can't fall back. Please report.");
 			retval = ERROR_FLASH_OPERATION_FAILED;
 			/* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
 			/* FIXME To allow fall back or recovery, we must save the actual status
@@ -1653,7 +1653,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buff
 	 *  R10 = unlock2_addr
 	 *  R11 = unlock2_cmd */
 
-	/* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_span_32.s for src */
 	static const uint32_t armv4_5_word_32_code[] = {
 		/* 00008100 <sp_32_code>:		*/
 		0xe4905004,		/* ldr	r5, [r0], #4			*/
@@ -1685,7 +1685,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buff
 		0xeafffffe		/* b	8154 <sp_32_done>		*/
 	};
 
-	/* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_span_16.s for src */
 	static const uint32_t armv4_5_word_16_code[] = {
 		/* 00008158 <sp_16_code>:		*/
 		0xe0d050b2,		/* ldrh	r5, [r0], #2			*/
@@ -2406,7 +2406,7 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of
 			break;
 	}
 	if (retval == ERROR_OK) {
-		/* Increment pointers and decrease count on succesful block write */
+		/* Increment pointers and decrease count on successful block write */
 		buffer += blk_count;
 		write_p += blk_count;
 		count -= blk_count;
@@ -2795,7 +2795,7 @@ int cfi_probe(struct flash_bank *bank)
 												 *for
 												 *all
 												 *CFI
-												 *flashs
+												 *flashes
 												 **/
 				cfi_read_0002_pri_ext(bank);
 				break;
diff --git a/src/flash/nor/core.h b/src/flash/nor/core.h
index 9f897e3e21..163e57878e 100644
--- a/src/flash/nor/core.h
+++ b/src/flash/nor/core.h
@@ -248,7 +248,7 @@ int get_flash_bank_by_num(unsigned int num, struct flash_bank **bank);
  * @a instance is driver-specific.
  * @param name_index The index to the string in args containing the
  * bank identifier.
- * @param bank On output, contians a pointer to the bank or NULL.
+ * @param bank On output, contains a pointer to the bank or NULL.
  * @returns ERROR_OK on success, or an error indicating the problem.
  */
 COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h
index ea8657b08b..7f66047fef 100644
--- a/src/flash/nor/driver.h
+++ b/src/flash/nor/driver.h
@@ -120,7 +120,7 @@ struct flash_driver {
 	 *
 	 * @param bank The bank to protect or unprotect.
 	 * @param set If non-zero, enable protection; if 0, disable it.
-	 * @param first The first sector to (un)protect, typicaly 0.
+	 * @param first The first sector to (un)protect, typically 0.
 	 * @param last The last sector to (un)project, typically N-1.
 	 * @returns ERROR_OK if successful; otherwise, an error code.
 	 */
@@ -202,14 +202,14 @@ struct flash_driver {
 	int (*info)(struct flash_bank *bank, char *buf, int buf_size);
 
 	/**
-	 * A more gentle flavor of filash_driver_s::probe, performing
+	 * A more gentle flavor of flash_driver_s::probe, performing
 	 * setup with less noise.  Generally, driver routines should test
 	 * to see if the bank has already been probed; if it has, the
 	 * driver probably should not perform its probe a second time.
 	 *
 	 * This callback is often called from the inside of other
 	 * routines (e.g. GDB flash downloads) to autoprobe the flash as
-	 * it is programing the flash.
+	 * it is programming the flash.
 	 *
 	 * @param bank - the bank to probe
 	 * @returns ERROR_OK if successful; otherwise, an error code.
diff --git a/src/flash/nor/dsp5680xx_flash.c b/src/flash/nor/dsp5680xx_flash.c
index f06f143653..6f1eccfeb9 100644
--- a/src/flash/nor/dsp5680xx_flash.c
+++ b/src/flash/nor/dsp5680xx_flash.c
@@ -107,7 +107,7 @@ static int dsp5680xx_flash_protect_check(struct flash_bank *bank)
 }
 
 /**
- * Protection funcionality is not implemented.
+ * Protection functionality is not implemented.
  * The current implementation applies/removes security on the chip.
  * The chip is effectively secured/unsecured after the first reset
  * following the execution of this function.
diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c
index 4e40e6b6b6..cb4456209f 100644
--- a/src/flash/nor/em357.c
+++ b/src/flash/nor/em357.c
@@ -466,7 +466,7 @@ static int em357_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	struct armv7m_algorithm armv7m_info;
 	int retval = ERROR_OK;
 
-	/* see contib/loaders/flash/stm32x.s for src, the same is used here except for
+	/* see contrib/loaders/flash/stm32x.s for src, the same is used here except for
 	 * a modified *_FLASH_BASE */
 
 	static const uint8_t em357_flash_write_code[] = {
diff --git a/src/flash/nor/fm3.c b/src/flash/nor/fm3.c
index afeba8e0bd..fef1797069 100644
--- a/src/flash/nor/fm3.c
+++ b/src/flash/nor/fm3.c
@@ -276,7 +276,7 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash acccess) */
+	/* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */
 	retval = target_write_u32(target, 0x40000000, 0x0001);
 	if (retval != ERROR_OK)
 		return retval;
@@ -336,7 +336,7 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
 	destroy_reg_param(&reg_params[1]);
 	destroy_reg_param(&reg_params[2]);
 
-	/* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash acccess) */
+	/* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash access) */
 	retval = target_write_u32(target, 0x40000000, 0x0002);
 	if (retval != ERROR_OK)
 		return retval;
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index 07c5eac368..43b90f1f0c 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -79,7 +79,7 @@
  *
  */
 
-/* Addressess */
+/* Addresses */
 #define FCF_ADDRESS	0x00000400
 #define FCF_FPROT	0x8
 #define FCF_FSEC	0xc
@@ -506,7 +506,7 @@ COMMAND_HANDLER(kinetis_mdm_halt)
 		}
 	}
 
-	LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
+	LOG_DEBUG("MDM: halt succeeded after %d attempts.", tries);
 
 	target_poll(target);
 	/* enable polling in case kinetis_check_flash_security_status disabled it */
@@ -1429,7 +1429,7 @@ static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
 		bank_iter = k_bank->bank;
 
 		if (bank_iter == NULL) {
-			LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplette", bank_idx);
+			LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplete", bank_idx);
 			continue;
 		}
 
@@ -2850,7 +2850,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
 				if (result == ERROR_OK) {
 					bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
 				} else {
-					LOG_DEBUG("Ignoring errored PFlash sector blank-check");
+					LOG_DEBUG("Ignoring error on PFlash sector blank-check");
 					kinetis_ftfx_clear_error(bank->target);
 					bank->sectors[i].is_erased = -1;
 				}
diff --git a/src/flash/nor/kinetis_ke.c b/src/flash/nor/kinetis_ke.c
index 206d6f7236..6afb3b9e6a 100644
--- a/src/flash/nor/kinetis_ke.c
+++ b/src/flash/nor/kinetis_ke.c
@@ -1229,7 +1229,7 @@ static int kinetis_ke_blank_check(struct flash_bank *bank)
 			if (result == ERROR_OK)	{
 				bank->sectors[i].is_erased = !(fstat & (FTMRX_FSTAT_MGSTAT0_MASK | FTMRX_FSTAT_MGSTAT1_MASK));
 			} else {
-				LOG_DEBUG("Ignoring errored PFlash sector blank-check");
+				LOG_DEBUG("Ignoring error on PFlash sector blank-check");
 				bank->sectors[i].is_erased = -1;
 			}
 		}
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 6758b43ddd..a1aa1df3e7 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -1170,7 +1170,7 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
 				break;
 		}
 
-		/* Exit if error occured */
+		/* Exit if error occurred */
 		if (retval != ERROR_OK)
 			break;
 
@@ -1212,7 +1212,7 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
 				break;
 		}
 
-		/* Exit if error occured */
+		/* Exit if error occurred */
 		if (retval != ERROR_OK)
 			break;
 
diff --git a/src/flash/nor/lpc288x.c b/src/flash/nor/lpc288x.c
index 13450ef82b..1c10e50157 100644
--- a/src/flash/nor/lpc288x.c
+++ b/src/flash/nor/lpc288x.c
@@ -398,10 +398,10 @@ static int lpc288x_protect(struct flash_bank *bank, int set, unsigned int first,
 
 	for (unsigned int lockregion = first; lockregion <= last; lockregion++) {
 		if (set) {
-			/* write an odd value to base addy to protect... */
+			/* write an odd value to base address to protect... */
 			value = 0x01;
 		} else {
-			/* write an even value to base addy to unprotect... */
+			/* write an even value to base address to unprotect... */
 			value = 0x00;
 		}
 		target_write_u32(target, bank->sectors[lockregion].offset, value);
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index af8bba092b..386c8bffe2 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -49,8 +49,8 @@
 #define FTCTR           0x2020000C	/* Flash test control */
 #define FBWST           0x20200010	/* Flash bridge wait-state */
 #define FCRA            0x2020001C	/* Flash clock divider */
-#define FMSSTART        0x20200020	/* Flash Built-In Selft Test start address */
-#define FMSSTOP         0x20200024	/* Flash Built-In Selft Test stop address */
+#define FMSSTART        0x20200020	/* Flash Built-In Self Test start address */
+#define FMSSTOP         0x20200024	/* Flash Built-In Self Test stop address */
 #define FMS16           0x20200028	/* Flash 16-bit signature */
 #define FMSW0           0x2020002C	/* Flash 128-bit signature Word 0 */
 #define FMSW1           0x20200030	/* Flash 128-bit signature Word 1 */
@@ -160,7 +160,7 @@ struct lpc2900_flash_bank {
 
 	/**
 	 * Maximum contiguous block of internal SRAM (bytes).
-	 * Autodetected by the driver. Not the total amount of SRAM, only the
+	 * Autodetected by the driver. Not the total amount of SRAM, only
 	 * the largest \em contiguous block!
 	 */
 	uint32_t max_ram_block;
@@ -1535,7 +1535,7 @@ static int lpc2900_erase_check(struct flash_bank *bank)
 		return status;
 	}
 
-	/* Use the BIST (Built-In Selft Test) to generate a signature of each flash
+	/* Use the BIST (Built-In Self Test) to generate a signature of each flash
 	 * sector. Compare against the expected signature of an empty sector.
 	 */
 	for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index 65898cd647..c840bd795d 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -80,7 +80,7 @@ struct max32xxx_flash_bank {
 	unsigned int burst_size_bits;
 };
 
-/* see contib/loaders/flash/max32xxx/max32xxx.s for src */
+/* see contrib/loaders/flash/max32xxx/max32xxx.s for src */
 static const uint8_t write_code[] = {
 #include "../../contrib/loaders/flash/max32xxx/max32xxx.inc"
 };
diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c
index 085403885b..2377e14f74 100644
--- a/src/flash/nor/niietcm4.c
+++ b/src/flash/nor/niietcm4.c
@@ -65,8 +65,8 @@
 #define FCIS_OP_ERROR				(1<<1)				/* Flag operation error */
 
 /*---- FCIC: CLear status register */
-#define FCIC_CLR_OPCMLT				(1<<0)				/* Cleare completion flag in register FCIS */
-#define FCIC_CLR_OPERROR			(1<<1)				/* Cleare error flag in register FCIS */
+#define FCIC_CLR_OPCMLT				(1<<0)				/* Clear completion flag in register FCIS */
+#define FCIC_CLR_OPERROR			(1<<1)				/* Clear error flag in register FCIS */
 
 /*-- USERFLASH ---------------------------------------------------------------*/
 #define USERFLASH_PAGE_SIZE			256
@@ -95,8 +95,8 @@
 #define UFCIS_OP_ERROR				(1<<1)				/* Flag operation error */
 
 /*---- UFCIC: CLear status register */
-#define UFCIC_CLR_OPCMLT			(1<<0)				/* Cleared completion flag in register FCIS */
-#define UFCIC_CLR_OPERROR			(1<<1)				/* Cleared error flag in register FCIS */
+#define UFCIC_CLR_OPCMLT			(1<<0)				/* Clear completion flag in register FCIS */
+#define UFCIC_CLR_OPERROR			(1<<1)				/* Clear error flag in register FCIS */
 
 /*---- In info userflash address space */
 #define INFOWORD0_ADDR				0x00
@@ -1226,7 +1226,7 @@ static int niietcm4_protect(struct flash_bank *bank, int set,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	LOG_INFO("Plese wait ..."); /* it`s quite a long process */
+	LOG_INFO("Please wait ..."); /* it`s quite a long process */
 	/* chose between main bootflash and info bootflash */
 	if (niietcm4_info->bflash_info_remap) {
 		/* dump */
@@ -1416,7 +1416,7 @@ static int niietcm4_write(struct flash_bank *bank, const uint8_t *buffer,
 		/* if block write failed (no sufficient working area),
 		 * we use normal (slow) single halfword accesses */
 		LOG_WARNING("Can't use block writes, falling back to single memory accesses");
-		LOG_INFO("Plese wait ..."); /* it`s quite a long process */
+		LOG_INFO("Please wait ..."); /* it`s quite a long process */
 
 		/* chose between main bootflash and info bootflash */
 		if (niietcm4_info->bflash_info_remap)
@@ -1588,10 +1588,10 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
 		char info_bootflash_addr_str[64];
 		if (niietcm4_info->bflash_info_remap)
 			snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
-					TARGET_ADDR_FMT " base adress", bank->base);
+					TARGET_ADDR_FMT " base address", bank->base);
 		else
 			snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
-					"not mapped to global adress space");
+					"not mapped to global address space");
 
 		snprintf(niietcm4_info->chip_brief,
 				sizeof(niietcm4_info->chip_brief),
@@ -1600,7 +1600,7 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
 				"Bootflash :\n"
 				"    %d kB total\n"
 				"    %d pages %d kB each\n"
-				"    0x%08x base adress\n"
+				"    0x%08x base address\n"
 				"%s"
 				"Info bootflash :\n"
 				"    %d kB total\n"
@@ -1611,18 +1611,18 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
 				"    %d kB total\n"
 				"    %d pages %d B each\n"
 				"    %d bit cells\n"
-				"    not maped to global adress space\n"
+				"    not mapped to global address space\n"
 				"Info userflash :\n"
 				"    %d B total\n"
 				"    %d pages of %d B each\n"
 				"    %d bit cells\n"
-				"    not maped to global adress space\n"
+				"    not mapped to global address space\n"
 				"RAM :\n"
 				"    192 kB total\n"
-				"    0x20000000 base adress\n"
+				"    0x20000000 base address\n"
 				"External memory :\n"
 				"    8/16 bit address space\n"
-				"    0x%08x base adress\n"
+				"    0x%08x base address\n"
 				"\n"
 				"INFOWORD STATUS\n"
 				"Bootflash info region remap :\n"
diff --git a/src/flash/nor/non_cfi.c b/src/flash/nor/non_cfi.c
index f44adba137..a817966c61 100644
--- a/src/flash/nor/non_cfi.c
+++ b/src/flash/nor/non_cfi.c
@@ -483,7 +483,7 @@ void cfi_fixup_non_cfi(struct flash_bank *bank)
 			break;
 	}
 
-	/* only fixup jedec flashs found in table */
+	/* only fixup jedec flashes found in table */
 	if (!non_cfi->mfr)
 		return;
 
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index a79aa78b90..0ceb8d7544 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -89,7 +89,7 @@ enum nrf5_ficr_registers {
 
 enum nrf5_uicr_registers {
 	NRF5_UICR_BASE = 0x10001000, /* User Information
-				       * Configuration Regsters */
+				       * Configuration Registers */
 
 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
 
@@ -256,7 +256,7 @@ static const struct nrf5_device_spec nrf5_known_devices_table[] = {
 	NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0",    256),
 	NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0",    256),
 
-	/* The driver fully autodects nRF52 series devices by FICR INFO,
+	/* The driver fully autodetects nRF52 series devices by FICR INFO,
 	 * no need for nRF52xxx HWIDs in this table */
 #if 0
 	/* nRF52810 Devices */
@@ -533,7 +533,7 @@ static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
 	}
 
 	if (first != 0) {
-		LOG_ERROR("Code region 0 must start at the begining of the bank");
+		LOG_ERROR("Code region 0 must start at the beginning of the bank");
 		return ERROR_FAIL;
 	}
 
@@ -1363,7 +1363,7 @@ const struct flash_driver nrf5_flash = {
 };
 
 /* We need to retain the flash-driver name as well as the commands
- * for backwards compatability */
+ * for backwards compatibility */
 const struct flash_driver nrf51_flash = {
 	.name			= "nrf51",
 	.commands		= nrf5_command_handlers,
diff --git a/src/flash/nor/ocl.h b/src/flash/nor/ocl.h
index 3e83f76cfd..b1fe308f26 100644
--- a/src/flash/nor/ocl.h
+++ b/src/flash/nor/ocl.h
@@ -22,7 +22,7 @@
 /* command/response mask */
 #define OCL_CMD_MASK 0xFFFF0000L
 
-/* commads */
+/* commands */
 #define OCL_FLASH_BLOCK 0x0CFB0000L
 #define OCL_ERASE_BLOCK 0x0CEB0000L
 #define OCL_ERASE_ALL 0x0CEA0000L
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index b214642a09..9b91853440 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -372,7 +372,7 @@ static int pic32mx_protect(struct flash_bank *bank, int set, unsigned int first,
 	return ERROR_OK;
 }
 
-/* see contib/loaders/flash/pic32mx.s for src */
+/* see contrib/loaders/flash/pic32mx.s for src */
 
 static uint32_t pic32mx_flash_write_code[] = {
 					/* write: */
diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c
index be9a886a26..0c656349f8 100644
--- a/src/flash/nor/psoc4.c
+++ b/src/flash/nor/psoc4.c
@@ -35,7 +35,7 @@
 #include <target/algorithm.h>
 #include <target/armv7m.h>
 
-/* device documets:
+/* device documents:
 
  PSoC(R) 4: PSoC 4200 Family Datasheet
 	Document Number: 001-87197 Rev. *B  Revised August 29, 2013
@@ -392,7 +392,7 @@ static int psoc4_get_silicon_id(struct flash_bank *bank, uint32_t *silicon_id, u
 	/* build ID as Cypress sw does:
 	 * bit 31..16 silicon ID
 	 * bit 15..8  revision ID (so far 0x11 for all devices)
-	 * bit 7..0   family ID (lowes 8 bits)
+	 * bit 7..0   family ID (lowest 8 bits)
 	 */
 	if (silicon_id)
 			*silicon_id = ((part0 & 0x0000ffff) << 16)
diff --git a/src/flash/nor/psoc5lp.c b/src/flash/nor/psoc5lp.c
index 17cc6d8085..25a0ee0259 100644
--- a/src/flash/nor/psoc5lp.c
+++ b/src/flash/nor/psoc5lp.c
@@ -47,7 +47,7 @@
 #define PANTHER_DEVICE_ID       0x4008001C
 
 /* NVL is not actually mapped to the Cortex-M address space
- * As we need a base addess different from other banks in the device
+ * As we need a base address different from other banks in the device
  * we use the address of NVL programming data in Cypress images */
 #define NVL_META_BASE			0x90000000
 
diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c
index 3eb2fc26b5..c7141738d0 100644
--- a/src/flash/nor/psoc6.c
+++ b/src/flash/nor/psoc6.c
@@ -325,7 +325,7 @@ static int ipc_acquire(struct target *target, char ipc_id)
  * @brief Invokes SROM API functions which are responsible for Flash operations
  *
  * @param target current target
- * @param req_and_params requect id of the function to invoke
+ * @param req_and_params request id of the function to invoke
  * @param working_area address of memory buffer in target's memory space for SROM API parameters
  * @param data_out pointer to variable which will be populated with execution status
  * @return ERROR_OK in case of success, ERROR_XXX code otherwise
@@ -475,7 +475,7 @@ static int psoc6_protect(struct flash_bank *bank, int set, unsigned int first,
 /** ***********************************************************************************************
  * @brief Translates Protection status to string
  * @param protection protection value
- * @return pointer to const string describintg protection status
+ * @return pointer to const string describing protection status
  *************************************************************************************************/
 static const char *protection_to_str(uint8_t protection)
 {
@@ -574,7 +574,7 @@ static int psoc6_probe(struct flash_bank *bank)
 
 	int hr = ERROR_OK;
 
-	/* Retrieve data from SPCIF_GEOMATRY */
+	/* Retrieve data from SPCIF_GEOMETRY */
 	uint32_t geom;
 	target_read_u32(target, PSOC6_SPCIF_GEOMETRY, &geom);
 	uint32_t row_sz_lg2 = (geom & 0xF0) >> 4;
@@ -835,7 +835,7 @@ exit:
  * @brief Performs Program operation
  * @param bank current flash bank
  * @param buffer pointer to the buffer with data
- * @param offset starting offset in falsh bank
+ * @param offset starting offset in flash bank
  * @param count number of bytes in buffer
  * @return ERROR_OK in case of success, ERROR_XXX code otherwise
  *************************************************************************************************/
@@ -956,7 +956,7 @@ int handle_reset_halt(struct target *target)
 
 	const struct armv7m_common *cm = target_to_armv7m(target);
 
-	/* PSoC6 reboots immediatelly after issuing SYSRESETREQ / VECTRESET
+	/* PSoC6 reboots immediately after issuing SYSRESETREQ / VECTRESET
 	 * this disables SWD/JTAG pins momentarily and may break communication
 	 * Ignoring return value of mem_ap_write_atomic_u32 seems to be ok here */
 	if (is_cm0) {
diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c
index d2d254e08a..21449041c8 100644
--- a/src/flash/nor/sim3x.c
+++ b/src/flash/nor/sim3x.c
@@ -250,7 +250,7 @@ static int sim3x_erase_page(struct flash_bank *bank, uint32_t addr)
 			if (ret != ERROR_OK)
 				return ret;
 
-			/* Write the inital unlock value to KEY */
+			/* Write the initial unlock value to KEY */
 			ret = target_write_u32(target, FLASHCTRL0_KEY,
 			FLASHCTRL0_KEY_INITIAL_UNLOCK);
 			if (ret != ERROR_OK)
@@ -490,7 +490,7 @@ static int sim3x_flash_write(struct flash_bank *bank, const uint8_t *buffer, uin
 	sim3x_info = bank->driver_priv;
 
 	if (sim3x_info->flash_locked) {
-		LOG_ERROR("Falsh is locked");
+		LOG_ERROR("Flash is locked");
 		return ERROR_FAIL;
 	}
 
@@ -1032,7 +1032,7 @@ COMMAND_HANDLER(sim3x_lock)
 		ret = target_read_u32(target, CPUID, &val);
 		/* if correct value is read, then it will continue */
 		if (ret != ERROR_OK || (val & CPUID_CHECK_VALUE_MASK) != CPUID_CHECK_VALUE) {
-			/* if correct value is'n read, then it will check SIM3X_AP_INIT_STAT register */
+			/* if correct value isn't read, then it will check SIM3X_AP_INIT_STAT register */
 			ret = ap_read_register(dap, SIM3X_AP_INIT_STAT, &val);
 			if (ret != ERROR_OK)
 				return ret;
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 9763644c5c..34c9c28feb 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -487,7 +487,7 @@ static int get_stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
 	if (stellaris_info->did1 == 0)
 		return ERROR_FLASH_BANK_NOT_PROBED;
 
-	/* Read main and master clock freqency register */
+	/* Read main and master clock frequency register */
 	stellaris_read_clock_info(bank);
 
 	printed = snprintf(buf,
@@ -533,7 +533,7 @@ static int get_stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
 *	chip identification and status                                         *
 ***************************************************************************/
 
-/* Set the flash timimg register to match current clocking */
+/* Set the flash timing register to match current clocking */
 static void stellaris_set_flash_timing(struct flash_bank *bank)
 {
 	struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
@@ -886,7 +886,7 @@ static int stellaris_erase(struct flash_bank *bank, unsigned int first,
 			target_read_u32(target, FLASH_FMC, &flash_fmc);
 		} while (flash_fmc & FMC_ERASE);
 
-		/* Check acess violations */
+		/* Check access violations */
 		target_read_u32(target, FLASH_CRIS, &flash_cris);
 		if (flash_cris & (AMASK)) {
 			LOG_WARNING("Error erasing flash page %i,  flash_cris 0x%" PRIx32 "",
@@ -998,7 +998,7 @@ static int stellaris_protect(struct flash_bank *bank, int set,
 	return ERROR_OK;
 }
 
-/* see contib/loaders/flash/stellaris.s for src */
+/* see contrib/loaders/flash/stellaris.s for src */
 
 static const uint8_t stellaris_write_code[] = {
 								/* write: */
@@ -1170,7 +1170,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
 			if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 				LOG_DEBUG("writing flash word-at-a-time");
 			} else if (retval == ERROR_FLASH_OPERATION_FAILED) {
-				/* if an error occured, we examine the reason, and quit */
+				/* if an error occurred, we examine the reason, and quit */
 				target_read_u32(target, FLASH_CRIS, &flash_cris);
 
 				LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index f07f24aaed..6510e75dc1 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -55,7 +55,7 @@
  * can be very different.
  *
  * To reduce testing complexity and dangers of regressions,
- * a seperate file is used for stm32fx2x.
+ * a separate file is used for stm32fx2x.
  *
  * Sector sizes in kiBytes:
  * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
@@ -419,7 +419,7 @@ static int stm32x_read_options(struct flash_bank *bank)
 		if (retval != ERROR_OK)
 			return retval;
 
-		/* FLASH_OPTCR1 has quite diffent meanings ... */
+		/* FLASH_OPTCR1 has quite different meanings ... */
 		if (stm32x_info->has_boot_addr) {
 			/* for F7xx it contains boot0 and boot1 */
 			stm32x_info->option_bytes.boot_addr = optiondata;
@@ -1026,7 +1026,7 @@ static int stm32x_probe(struct flash_bank *bank)
 		bank->prot_blocks = NULL;
 	}
 
-	/* if explicitely called out as OTP bank, short circuit probe */
+	/* if explicitly called out as OTP bank, short circuit probe */
 	if (stm32x_is_otp(bank)) {
 		if (stm32x_otp_is_f7(bank)) {
 			otp_size_in_b = STM32F7_OTP_SIZE;
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index edd013048b..c56bd6d600 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -534,7 +534,7 @@ static int stm32l4_protect_check(struct flash_bank *bank)
 		stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
 		stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
 	} else {
-		/* prevent unintialized errors */
+		/* prevent uninitialized errors */
 		wrp2ar = 0;
 		wrp2br = 0;
 	}
diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c
index 9c817c994f..cf5b360409 100644
--- a/src/flash/nor/stm32lx.c
+++ b/src/flash/nor/stm32lx.c
@@ -629,7 +629,7 @@ static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer,
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* first we need to write any unaligned head bytes upto
+	/* first we need to write any unaligned head bytes up to
 	 * the next 128 byte page */
 
 	if (offset % hp_nb)
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index dd72f538a5..e028c1ffd1 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -452,7 +452,7 @@ static int str7x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	struct arm_algorithm arm_algo;
 	int retval = ERROR_OK;
 
-	/* see contib/loaders/flash/str7x.s for src */
+	/* see contrib/loaders/flash/str7x.s for src */
 
 	static const uint32_t str7x_flash_write_code[] = {
 					/* write:				*/
diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index d49875c5aa..87ffec8777 100644
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -354,7 +354,7 @@ static int str9x_write_block(struct flash_bank *bank,
 	struct arm_algorithm arm_algo;
 	int retval = ERROR_OK;
 
-	/* see contib/loaders/flash/str9x.s for src */
+	/* see contrib/loaders/flash/str9x.s for src */
 
 	static const uint32_t str9x_flash_write_code[] = {
 					/* write:				*/
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index 0d3f487d95..4b8d2208af 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -722,7 +722,7 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
 	bank->sectors[sector].is_protected = 0;
 
 	/*
-	 * clear status regiser, sent erase command, kickoff erase
+	 * clear status register, sent erase command, kickoff erase
 	 */
 	target_write_u16(target, flashAddr, 0x0040);
 	LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
@@ -865,7 +865,7 @@ static int tms470_protect(struct flash_bank *bank, int set, unsigned int first,
 	target_read_u32(target, 0xFFE8BC04, &fmmac2);
 	target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
 
-	/* get the original sector proection flags for this bank */
+	/* get the original sector protection flags for this bank */
 	target_read_u32(target, 0xFFE88008, &fmbsea);
 	target_read_u32(target, 0xFFE8800C, &fmbseb);
 
diff --git a/src/flash/nor/w600.c b/src/flash/nor/w600.c
index 714b27db21..4790821777 100644
--- a/src/flash/nor/w600.c
+++ b/src/flash/nor/w600.c
@@ -347,7 +347,7 @@ static int w600_probe(struct flash_bank *bank)
 		bank->sectors[i].offset = i * W600_FLASH_SECSIZE;
 		bank->sectors[i].size = W600_FLASH_SECSIZE;
 		bank->sectors[i].is_erased = -1;
-		/* offset 0 to W600_FLASH_PROTECT_SIZE shoule be protected */
+		/* offset 0 to W600_FLASH_PROTECT_SIZE should be protected */
 		bank->sectors[i].is_protected = (i < W600_FLASH_PROTECT_SIZE / W600_FLASH_SECSIZE);
 	}
 
diff --git a/src/flash/nor/xmc4xxx.c b/src/flash/nor/xmc4xxx.c
index aa26693ec6..a032e4d46f 100644
--- a/src/flash/nor/xmc4xxx.c
+++ b/src/flash/nor/xmc4xxx.c
@@ -1197,7 +1197,7 @@ static int xmc4xxx_protect_check(struct flash_bank *bank)
 
 	unsigned int sectors = bank->num_sectors;
 
-	/* On devices with 12 sectors, sectors 10 & 11 are ptected
+	/* On devices with 12 sectors, sectors 10 & 11 are protected
 	 * together instead of individually */
 	if (sectors == 12)
 		sectors--;
@@ -1237,7 +1237,7 @@ static int xmc4xxx_protect_check(struct flash_bank *bank)
 		}
 	}
 
-	/* XMC4xxx also supports read proptection, make a note
+	/* XMC4xxx also supports read protection, make a note
 	 * in the private driver structure */
 	if (protection[0] & PROCON_RPRO_MASK)
 		fb->read_protected = true;