From: Sean Anderson <sean.anderson@seco.com>
Date: Fri, 11 Feb 2022 22:43:30 +0000 (-0500)
Subject: cpld: altera-epm240: Increase adapter speed
X-Git-Tag: v0.12.0-rc1~322
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=b61eae1962f008627f4593cfda9b3431e4c3c016

cpld: altera-epm240: Increase adapter speed

According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---

diff --git a/tcl/cpld/altera-epm240.cfg b/tcl/cpld/altera-epm240.cfg
index 6e10188ca8..ece02bbefc 100644
--- a/tcl/cpld/altera-epm240.cfg
+++ b/tcl/cpld/altera-epm240.cfg
@@ -17,3 +17,7 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
 	-expected-id 0x020a40dd \
 	-expected-id 0x020a50dd \
 	-expected-id 0x020a60dd
+
+# 200ns seems like a good speed
+# c.f. Table 5-34: MAX II JTAG Timing Parameters
+adapter speed 5000