From: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Date: Fri, 16 Sep 2016 13:31:29 +0000 (+0200)
Subject: aarch64: use correct A64 instructions for cache handling
X-Git-Tag: v0.11.0-rc1~1496
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=e8602889f9a9fce35eecc8109865fd9ae6d4d05e

aarch64: use correct A64 instructions for cache handling

Replace A32 MCR with proper A64 MSR opcodes

Change-Id: I64a60b17a58a26b199d2d1b2d5d91098e0c8cbd0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
---

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index ae2ecbfb69..d76da83f46 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2235,7 +2235,7 @@ static int aarch64_write_phys_memory(struct target *target,
 		 * wrong addresses will be invalidated!
 		 *
 		 * For both ICache and DCache, walk all cache lines in the
-		 * address range. Cortex-A8 has fixed 64 byte line length.
+		 * address range. Cortex-A has fixed 64 byte line length.
 		 *
 		 * REVISIT per ARMv7, these may trigger watchpoints ...
 		 */
@@ -2246,12 +2246,12 @@ static int aarch64_write_phys_memory(struct target *target,
 			 * with MVA to PoU
 			 *      MCR p15, 0, r0, c7, c5, 1
 			 */
-			for (uint32_t cacheline = address;
-				cacheline < address + size * count;
+			for (uint32_t cacheline = 0;
+				cacheline < size * count;
 				cacheline += 64) {
 				retval = dpm->instr_write_data_r0(dpm,
-						ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
-						cacheline);
+						ARMV8_MSR_GP(SYSTEM_ICIVAU, 0),
+						address + cacheline);
 				if (retval != ERROR_OK)
 					return retval;
 			}
@@ -2263,12 +2263,12 @@ static int aarch64_write_phys_memory(struct target *target,
 			 * with MVA to PoC
 			 *      MCR p15, 0, r0, c7, c6, 1
 			 */
-			for (uint32_t cacheline = address;
-				cacheline < address + size * count;
+			for (uint32_t cacheline = 0;
+				cacheline < size * count;
 				cacheline += 64) {
 				retval = dpm->instr_write_data_r0(dpm,
-						ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
-						cacheline);
+						ARMV8_MSR_GP(SYSTEM_DCCVAU, 0),
+						address + cacheline);
 				if (retval != ERROR_OK)
 					return retval;
 			}
diff --git a/src/target/armv8.c b/src/target/armv8.c
index d6b7dc8c1b..176c7adfde 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -34,7 +34,6 @@
 #include <unistd.h>
 
 #include "armv8_opcodes.h"
-#include "arm_opcodes.h"
 #include "target.h"
 #include "target_type.h"
 
@@ -465,7 +464,7 @@ static int _armv8_flush_all_data(struct target *target)
 			/*  DCCISW */
 			/* LOG_INFO ("%d %d %x",c_way,c_index,value); */
 			retval = dpm->instr_write_data_r0(dpm,
-					ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
+					ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
 					value);
 			if (retval != ERROR_OK)
 				goto done;