From f5657aa76e795e4ed5b13a9f5df943181a123e49 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 10 Apr 2021 01:23:57 +0200 Subject: [PATCH] tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. In the TCL scripts distributed with OpenOCD there are 1700+ lines that should be modified before switching to jimtcl 0.81. Apply the script below on every script in tcl folder. It fixes more than 92% of the lines %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- #!/usr/bin/perl -Wpi my $re_sym = qr{[a-z_][a-z0-9_]*}i; my $re_var = qr{(?:\$|\$::)$re_sym}; my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i; my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)}; my $re_op = qr{<<|>>|[+\-*/&|]}; my $re_expr = qr{( (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item) \s*$re_op\s* (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\)) )}x; # [expr [dict get $regsC100 SYM] + HEXNUM] s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/; # [ expr (EXPR) ] # [ expr EXPR ] # note: $re_expr captures '$3' s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/; s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/; %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6159 Tested-by: jenkins Reviewed-by: Tomas Vanek --- tcl/bitsbytes.tcl | 18 +- tcl/board/at91cap7a-stk-sdram.cfg | 2 +- tcl/board/at91sam9261-ek.cfg | 30 +- tcl/board/at91sam9263-ek.cfg | 32 +- tcl/board/dm355evm.cfg | 44 +- tcl/board/dm365evm.cfg | 12 +- tcl/board/embedded-artists_lpc2478-32.cfg | 2 +- tcl/board/icnova_imx53_sodimm.cfg | 130 +-- tcl/board/imx31pdk.cfg | 2 +- tcl/board/imx53-m53evk.cfg | 130 +-- tcl/board/imx53loco.cfg | 130 +-- tcl/board/mcb1700.cfg | 2 +- tcl/chip/atmel/at91/aic.tcl | 40 +- tcl/chip/atmel/at91/at91_pmc.cfg | 198 ++--- tcl/chip/atmel/at91/at91_rstc.cfg | 38 +- tcl/chip/atmel/at91/at91_wdt.cfg | 30 +- tcl/chip/atmel/at91/at91sam9261_matrix.cfg | 82 +- tcl/chip/atmel/at91/at91sam9263_matrix.cfg | 208 ++--- tcl/chip/atmel/at91/at91sam9_init.cfg | 28 +- tcl/chip/atmel/at91/at91sam9_sdramc.cfg | 92 +-- tcl/chip/atmel/at91/at91sam9_smc.cfg | 40 +- tcl/chip/atmel/at91/rtt.tcl | 10 +- tcl/chip/atmel/at91/usarts.tcl | 26 +- tcl/chip/st/spear/quirk_no_srst.tcl | 4 +- tcl/chip/st/spear/spear3xx_ddr.tcl | 2 +- tcl/chip/st/stm32/stm32_rcc.tcl | 20 +- tcl/chip/st/stm32/stm32_regs.tcl | 130 +-- tcl/cpu/arc/em.tcl | 2 +- tcl/cpu/arc/hs.tcl | 2 +- tcl/cpu/arc/v2.tcl | 4 +- tcl/fpga/xilinx-dna.cfg | 2 +- tcl/fpga/xilinx-xadc.cfg | 6 +- tcl/mem_helper.tcl | 2 +- tcl/memory.tcl | 8 +- tcl/mmr_helpers.tcl | 8 +- tcl/target/am335x.cfg | 4 +- tcl/target/am437x.cfg | 904 ++++++++++----------- tcl/target/ampere_emag.cfg | 2 +- tcl/target/bluenrg-x.cfg | 4 +- tcl/target/c100config.tcl | 38 +- tcl/target/c100helper.tcl | 38 +- tcl/target/c100regs.tcl | 386 ++++----- tcl/target/davinci.cfg | 200 ++--- tcl/target/fm4_mb9bf.cfg | 2 +- tcl/target/fm4_s6e2cc.cfg | 2 +- tcl/target/icepick.cfg | 2 +- tcl/target/imx.cfg | 2 +- tcl/target/ixp42x.cfg | 4 +- tcl/target/omap4430.cfg | 2 +- tcl/target/omap4460.cfg | 2 +- tcl/target/or1k.cfg | 2 +- tcl/target/pic32mx.cfg | 2 +- tcl/target/psoc5lp.cfg | 8 +- tcl/target/snps_em_sk_fpga.cfg | 2 +- tcl/target/snps_hsdk.cfg | 18 +- tcl/target/stm32h7x.cfg | 8 +- tcl/target/ti_dm355.cfg | 2 +- tcl/target/ti_dm365.cfg | 2 +- tcl/target/u8500.cfg | 4 +- tcl/test/selftest.cfg | 6 +- tcl/tools/memtest.tcl | 30 +- 61 files changed, 1596 insertions(+), 1596 deletions(-) diff --git a/tcl/bitsbytes.tcl b/tcl/bitsbytes.tcl index 52ca83db2e..5f9cae1147 100644 --- a/tcl/bitsbytes.tcl +++ b/tcl/bitsbytes.tcl @@ -5,30 +5,30 @@ # Creat helper variables ... # BIT0.. BIT31 -for { set x 0 } { $x < 32 } { set x [expr $x + 1]} { +for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} { set vn [format "BIT%d" $x] global $vn - set $vn [expr (1 << $x)] + set $vn [expr {1 << $x}] } # Create K bytes values # __1K ... to __2048K -for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} { +for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} { set vn [format "__%dK" $x] global $vn - set $vn [expr (1024 * $x)] + set $vn [expr {1024 * $x}] } # Create M bytes values # __1M ... to __2048K -for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} { +for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} { set vn [format "__%dM" $x] global $vn - set $vn [expr (1024 * 1024 * $x)] + set $vn [expr {1024 * 1024 * $x}] } proc create_mask { MSB LSB } { - return [expr (((1 << ($MSB - $LSB + 1))-1) << $LSB)] + return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}] } # Cut Bits $MSB to $LSB out of this value. @@ -52,8 +52,8 @@ proc normalize_bitfield { VALUE MSB LSB } { proc show_normalize_bitfield { VALUE MSB LSB } { set m [create_mask $MSB $LSB] - set mr [expr $VALUE & $m] - set sr [expr $mr >> $LSB] + set mr [expr {$VALUE & $m}] + set sr [expr {$mr >> $LSB}] echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr] return $sr } diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg index 8395ba33bc..8a371e064b 100644 --- a/tcl/board/at91cap7a-stk-sdram.cfg +++ b/tcl/board/at91cap7a-stk-sdram.cfg @@ -38,7 +38,7 @@ proc peek32 {address} { # Wait for an expression to be true with a timeout proc wait_state {expression} { - for {set i 0} {$i < 1000} {set i [expr $i + 1]} { + for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} { if {[uplevel 1 $expression] == 0} { return } diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg index 3963e9373d..d6e8c2d154 100644 --- a/tcl/board/at91sam9261-ek.cfg +++ b/tcl/board/at91sam9261-ek.cfg @@ -30,29 +30,29 @@ proc at91sam9261ek_reset_init { } { ;# set master_pll_mul 13 set val [expr $::AT91_WDT_WDV] ;# Counter Value - set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable - set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value - set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt - set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt + set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt set config(wdt_mr_val) $val ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBICSA - set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)] + set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}] ;# SDRAMC_CR - Configuration register set val [expr $::AT91_SDRAMC_NC_9] - set val [expr ($val | $::AT91_SDRAMC_NR_13)] - set val [expr ($val | $::AT91_SDRAMC_NB_4)] - set val [expr ($val | $::AT91_SDRAMC_CAS_3)] - set val [expr ($val | $::AT91_SDRAMC_DBW_32)] - set val [expr ($val | (2 << 8))] ;# Write Recovery Delay - set val [expr ($val | (7 << 12))] ;# Row Cycle Delay - set val [expr ($val | (3 << 16))] ;# Row Precharge Delay - set val [expr ($val | (2 << 20))] ;# Row to Column Delay - set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay - set val [expr ($val | (8 << 28))] ;# Exit Self Refresh to Active Delay + set val [expr {$val | $::AT91_SDRAMC_NR_13}] + set val [expr {$val | $::AT91_SDRAMC_NB_4}] + set val [expr {$val | $::AT91_SDRAMC_CAS_3}] + set val [expr {$val | $::AT91_SDRAMC_DBW_32}] + set val [expr {$val | (2 << 8)}] ;# Write Recovery Delay + set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay + set val [expr {$val | (3 << 16)}] ;# Row Precharge Delay + set val [expr {$val | (2 << 20)}] ;# Row to Column Delay + set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay + set val [expr {$val | (8 << 28)}] ;# Exit Self Refresh to Active Delay set config(sdram_cr_val) $val diff --git a/tcl/board/at91sam9263-ek.cfg b/tcl/board/at91sam9263-ek.cfg index 645b1a7bd0..b88efa9716 100644 --- a/tcl/board/at91sam9263-ek.cfg +++ b/tcl/board/at91sam9263-ek.cfg @@ -25,10 +25,10 @@ proc at91sam9263ek_reset_init { } { set config(master_pll_mul) 171 set val [expr $::AT91_WDT_WDV] ;# Counter Value - set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable - set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value - set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt - set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt + set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt set config(wdt_mr_val) $val @@ -37,22 +37,22 @@ proc at91sam9263ek_reset_init { } { set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA set val [expr $::AT91_MATRIX_EBI0_DBPUC] - set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)] - set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)] + set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}] + set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}] set config(matrix_ebicsa_val) $val ;# SDRAMC_CR - Configuration register set val [expr $::AT91_SDRAMC_NC_9] - set val [expr ($val | $::AT91_SDRAMC_NR_13)] - set val [expr ($val | $::AT91_SDRAMC_NB_4)] - set val [expr ($val | $::AT91_SDRAMC_CAS_3)] - set val [expr ($val | $::AT91_SDRAMC_DBW_32)] - set val [expr ($val | (1 << 8))] ;# Write Recovery Delay - set val [expr ($val | (7 << 12))] ;# Row Cycle Delay - set val [expr ($val | (2 << 16))] ;# Row Precharge Delay - set val [expr ($val | (2 << 20))] ;# Row to Column Delay - set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay - set val [expr ($val | (1 << 28))] ;# Exit Self Refresh to Active Delay + set val [expr {$val | $::AT91_SDRAMC_NR_13}] + set val [expr {$val | $::AT91_SDRAMC_NB_4}] + set val [expr {$val | $::AT91_SDRAMC_CAS_3}] + set val [expr {$val | $::AT91_SDRAMC_DBW_32}] + set val [expr {$val | (1 << 8)}] ;# Write Recovery Delay + set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay + set val [expr {$val | (2 << 16)}] ;# Row Precharge Delay + set val [expr {$val | (2 << 20)}] ;# Row to Column Delay + set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay + set val [expr {$val | (1 << 28)}] ;# Exit Self Refresh to Active Delay set config(sdram_cr_val) $val diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg index 0c971e9a0b..1e35b68fab 100644 --- a/tcl/board/dm355evm.cfg +++ b/tcl/board/dm355evm.cfg @@ -80,7 +80,7 @@ proc dm355evm_init {} { # VTPIOCR impedance calibration set addr [dict get $dm355 sysbase] - set addr [expr $addr + 0x70] + set addr [expr {$addr + 0x70}] # clear CLR, LOCK, PWRDN; wait a clock; set CLR mmw $addr 0 0x20c0 @@ -108,24 +108,24 @@ proc dm355evm_init {} { set addr [dict get $dm355 ddr_emif] # DDRPHYCR1 - mww [expr $addr + 0xe4] 0x50006404 + mww [expr {$addr + 0xe4}] 0x50006404 # PBBPR -- burst priority - mww [expr $addr + 0x20] 0xfe + mww [expr {$addr + 0x20}] 0xfe # SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM* - mmw [expr $addr + 0x08] 0x00800000 0 - mmw [expr $addr + 0x08] 0x0013c632 0x03870fff + mmw [expr {$addr + 0x08}] 0x00800000 0 + mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff # SDTIMR0, SDTIMR1 - mww [expr $addr + 0x10] 0x2a923249 - mww [expr $addr + 0x14] 0x4c17c763 + mww [expr {$addr + 0x10}] 0x2a923249 + mww [expr {$addr + 0x14}] 0x4c17c763 # SDCR -- relock SDTIM* - mmw [expr $addr + 0x08] 0 0x00008000 + mmw [expr {$addr + 0x08}] 0 0x00008000 # SDRCR -- refresh rate (171 MHz * 7.8usec) - mww [expr $addr + 0x0c] 1336 + mww [expr {$addr + 0x0c}] 1336 ######################## # ASYNC EMIF @@ -138,13 +138,13 @@ proc dm355evm_init {} { #set nand_timings 0x0400008c # AWCCR - mww [expr $addr + 0x04] 0xff + mww [expr {$addr + 0x04}] 0xff # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte) - mww [expr $addr + 0x10] $nand_timings + mww [expr {$addr + 0x10}] $nand_timings # CS1 == dm9000 Ethernet - mww [expr $addr + 0x14] 0x00a00505 + mww [expr {$addr + 0x14}] 0x00a00505 # NANDFCR -- only CS0 has NAND - mww [expr $addr + 0x60] 0x01 + mww [expr {$addr + 0x60}] 0x01 # default: both chipselects to the NAND socket are used nand probe 0 @@ -156,27 +156,27 @@ proc dm355evm_init {} { set addr [dict get $dm355 uart0] # PWREMU_MGNT -- rx + tx in reset - mww [expr $addr + 0x30] 0 + mww [expr {$addr + 0x30}] 0 # DLL, DLH -- 115200 baud - mwb [expr $addr + 0x20] 0x0d - mwb [expr $addr + 0x24] 0x00 + mwb [expr {$addr + 0x20}] 0x0d + mwb [expr {$addr + 0x24}] 0x00 # FCR - clear and disable FIFOs - mwb [expr $addr + 0x08] 0x07 - mwb [expr $addr + 0x08] 0x00 + mwb [expr {$addr + 0x08}] 0x07 + mwb [expr {$addr + 0x08}] 0x00 # IER - disable IRQs - mwb [expr $addr + 0x04] 0x00 + mwb [expr {$addr + 0x04}] 0x00 # LCR - 8-N-1 - mwb [expr $addr + 0x0c] 0x03 + mwb [expr {$addr + 0x0c}] 0x03 # MCR - no flow control or loopback - mwb [expr $addr + 0x10] 0x00 + mwb [expr {$addr + 0x10}] 0x00 # PWREMU_MGNT -- rx + tx normal, free running during JTAG halt - mww [expr $addr + 0x30] 0xe001 + mww [expr {$addr + 0x30}] 0xe001 ######################## diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg index 3b29dd866c..8c7f8c0a60 100644 --- a/tcl/board/dm365evm.cfg +++ b/tcl/board/dm365evm.cfg @@ -56,10 +56,10 @@ if { $CS0 == "NAND" } { #set nand_timings 0x0400008c # CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes) - mww [expr $a_emif + 0x10] $nand_timings + mww [expr {$a_emif + 0x10}] $nand_timings # NANDFCR -- CS0 has NAND - mww [expr $a_emif + 0x60] 0x01 + mww [expr {$a_emif + 0x60}] 0x01 } proc flashprobe {} { nand probe 0 @@ -80,10 +80,10 @@ if { $CS0 == "NAND" } { davinci_pinmux $dm365 2 0x00000055 # CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes) - mww [expr $a_emif + 0x10] 0x00000001 + mww [expr {$a_emif + 0x10}] 0x00000001 # ONENANDCTRL -- CS0 has OneNAND, enable sync reads - mww [expr $a_emif + 0x5c] 0x0441 + mww [expr {$a_emif + 0x5c}] 0x0441 } proc flashprobe {} { } } @@ -133,11 +133,11 @@ proc dm365evm_init {} { set a_emif [dict get $dm365 a_emif] # AWCCR - mww [expr $a_emif + 0x04] 0xff + mww [expr {$a_emif + 0x04}] 0xff # CS0 == NAND or OneNAND cs0_setup $a_emif # CS1 == CPLD - mww [expr $a_emif + 0x14] 0x00a00505 + mww [expr {$a_emif + 0x14}] 0x00a00505 # FIXME setup UART0 diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg index 8ef9179de1..abf0a5f227 100644 --- a/tcl/board/embedded-artists_lpc2478-32.cfg +++ b/tcl/board/embedded-artists_lpc2478-32.cfg @@ -26,7 +26,7 @@ proc init_board {} { global _CHIPNAME # A working area will help speeding the flash programming - $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0 + $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0 # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB) flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg index af9818814b..0a161f6cd5 100644 --- a/tcl/board/icnova_imx53_sodimm.cfg +++ b/tcl/board/icnova_imx53_sodimm.cfg @@ -45,7 +45,7 @@ proc sodimm_init { } { ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] - arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit init_l2cc init_aips @@ -79,7 +79,7 @@ proc init_l2cc { } { ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 - arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)] + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] } @@ -93,10 +93,10 @@ proc init_aips { } { set VAL 0x77777777 # dap apsel 1 - mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL # dap apsel 0 } @@ -104,22 +104,22 @@ proc init_aips { } { proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR - set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 - set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] - set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] - set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] - set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 - set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 return echo "not returned" @@ -127,52 +127,52 @@ proc init_clock { } { setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] ; # make sure change is effective - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers - mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 - mww [expr $CCM_BASE_ADDR + 0x10] 0 + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 ; # Switch ARM back to PLL 1. - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] ; # Restore the default values in the Gate registers - mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 ; # for cko - for ARM div by 8 - mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] } @@ -187,68 +187,68 @@ proc setup_pll { PLL_ADDR CLK } { set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { - set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (12 - 1)] + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] set DP_MFN 5 } elseif {$CLK == 850} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 41 } elseif {$CLK == 800} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 700} { - set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 7 } elseif {$CLK == 600} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 1 } elseif {$CLK == 665} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (96 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] set DP_MFN 89 } elseif {$CLK == 532} { - set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 13 } elseif {$CLK == 455} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 71 } elseif {$CLK == 400} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 216} { - set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 - mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { - return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] } diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg index 2dce157dbc..6c196543cd 100644 --- a/tcl/board/imx31pdk.cfg +++ b/tcl/board/imx31pdk.cfg @@ -6,7 +6,7 @@ $_TARGETNAME configure -event reset-init { imx31pdk_init } proc self_test {} { echo "Running 100 iterations of test." dump_image /ram/test 0x80000000 0x40000 - for {set i 0} {$i < 100} {set i [expr $i+1]} { + for {set i 0} {$i < 100} {set i [expr {$i+1}]} { echo "Iteration $i" reset init mww 0x80000000 0x12345678 0x10000 diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg index b529c49406..6f4964e3dc 100644 --- a/tcl/board/imx53-m53evk.cfg +++ b/tcl/board/imx53-m53evk.cfg @@ -44,7 +44,7 @@ proc m53evk_init { } { ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] - arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit init_l2cc init_aips @@ -75,7 +75,7 @@ proc init_l2cc { } { ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 - arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)] + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] } @@ -89,10 +89,10 @@ proc init_aips { } { set VAL 0x77777777 # dap apsel 1 - mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL # dap apsel 0 } @@ -100,22 +100,22 @@ proc init_aips { } { proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR - set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 - set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] - set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] - set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] - set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 - set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 return echo "not returned" @@ -123,52 +123,52 @@ proc init_clock { } { setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] ; # make sure change is effective - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers - mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 - mww [expr $CCM_BASE_ADDR + 0x10] 0 + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 ; # Switch ARM back to PLL 1. - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] ; # Restore the default values in the Gate registers - mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 ; # for cko - for ARM div by 8 - mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] } @@ -183,68 +183,68 @@ proc setup_pll { PLL_ADDR CLK } { set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { - set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (12 - 1)] + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] set DP_MFN 5 } elseif {$CLK == 850} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 41 } elseif {$CLK == 800} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 700} { - set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 7 } elseif {$CLK == 600} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 1 } elseif {$CLK == 665} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (96 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] set DP_MFN 89 } elseif {$CLK == 532} { - set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 13 } elseif {$CLK == 455} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 71 } elseif {$CLK == 400} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 216} { - set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 - mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { - return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] } diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg index 91c260138e..e1bc44da3b 100644 --- a/tcl/board/imx53loco.cfg +++ b/tcl/board/imx53loco.cfg @@ -46,7 +46,7 @@ proc loco_init { } { ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] - arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit init_l2cc init_aips @@ -80,7 +80,7 @@ proc init_l2cc { } { ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 - arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)] + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] } @@ -94,10 +94,10 @@ proc init_aips { } { set VAL 0x77777777 # dap apsel 1 - mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL # dap apsel 0 } @@ -105,22 +105,22 @@ proc init_aips { } { proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR - set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 - set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] - set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] - set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] - set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 - set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 return echo "not returned" @@ -128,52 +128,52 @@ proc init_clock { } { setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] ; # make sure change is effective - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers - mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 - mww [expr $CCM_BASE_ADDR + 0x10] 0 + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 ; # Switch ARM back to PLL 1. - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] ; # Restore the default values in the Gate registers - mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 ; # for cko - for ARM div by 8 - mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] } @@ -188,68 +188,68 @@ proc setup_pll { PLL_ADDR CLK } { set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { - set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (12 - 1)] + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] set DP_MFN 5 } elseif {$CLK == 850} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 41 } elseif {$CLK == 800} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 700} { - set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 7 } elseif {$CLK == 600} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 1 } elseif {$CLK == 665} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (96 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] set DP_MFN 89 } elseif {$CLK == 532} { - set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 13 } elseif {$CLK == 455} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 71 } elseif {$CLK == 400} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 216} { - set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 - mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { - return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] } diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg index 01080a0b16..a5e19024a9 100644 --- a/tcl/board/mcb1700.cfg +++ b/tcl/board/mcb1700.cfg @@ -55,7 +55,7 @@ $_TARGETNAME configure -event reset-init { # # global MCB1700_CCLK - adapter speed [expr $MCB1700_CCLK / 8] + adapter speed [expr {$MCB1700_CCLK / 8}] # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select # "User Flash Mode" where interrupt vectors are _not_ remapped, diff --git a/tcl/chip/atmel/at91/aic.tcl b/tcl/chip/atmel/at91/aic.tcl index ba0f2a91ba..b0b1002707 100644 --- a/tcl/chip/atmel/at91/aic.tcl +++ b/tcl/chip/atmel/at91/aic.tcl @@ -1,38 +1,38 @@ -set AIC_SMR [expr $AT91C_BASE_AIC + 0x00000000 ] +set AIC_SMR [expr {$AT91C_BASE_AIC + 0x00000000} ] global AIC_SMR -set AIC_SVR [expr $AT91C_BASE_AIC + 0x00000080 ] +set AIC_SVR [expr {$AT91C_BASE_AIC + 0x00000080} ] global AIC_SVR -set AIC_IVR [expr $AT91C_BASE_AIC + 0x00000100 ] +set AIC_IVR [expr {$AT91C_BASE_AIC + 0x00000100} ] global AIC_IVR -set AIC_FVR [expr $AT91C_BASE_AIC + 0x00000104 ] +set AIC_FVR [expr {$AT91C_BASE_AIC + 0x00000104} ] global AIC_FVR -set AIC_ISR [expr $AT91C_BASE_AIC + 0x00000108 ] +set AIC_ISR [expr {$AT91C_BASE_AIC + 0x00000108} ] global AIC_ISR -set AIC_IPR [expr $AT91C_BASE_AIC + 0x0000010C ] +set AIC_IPR [expr {$AT91C_BASE_AIC + 0x0000010C} ] global AIC_IPR -set AIC_IMR [expr $AT91C_BASE_AIC + 0x00000110 ] +set AIC_IMR [expr {$AT91C_BASE_AIC + 0x00000110} ] global AIC_IMR -set AIC_CISR [expr $AT91C_BASE_AIC + 0x00000114 ] +set AIC_CISR [expr {$AT91C_BASE_AIC + 0x00000114} ] global AIC_CISR -set AIC_IECR [expr $AT91C_BASE_AIC + 0x00000120 ] +set AIC_IECR [expr {$AT91C_BASE_AIC + 0x00000120} ] global AIC_IECR -set AIC_IDCR [expr $AT91C_BASE_AIC + 0x00000124 ] +set AIC_IDCR [expr {$AT91C_BASE_AIC + 0x00000124} ] global AIC_IDCR -set AIC_ICCR [expr $AT91C_BASE_AIC + 0x00000128 ] +set AIC_ICCR [expr {$AT91C_BASE_AIC + 0x00000128} ] global AIC_ICCR -set AIC_ISCR [expr $AT91C_BASE_AIC + 0x0000012C ] +set AIC_ISCR [expr {$AT91C_BASE_AIC + 0x0000012C} ] global AIC_ISCR -set AIC_EOICR [expr $AT91C_BASE_AIC + 0x00000130 ] +set AIC_EOICR [expr {$AT91C_BASE_AIC + 0x00000130} ] global AIC_EOICR -set AIC_SPU [expr $AT91C_BASE_AIC + 0x00000134 ] +set AIC_SPU [expr {$AT91C_BASE_AIC + 0x00000134} ] global AIC_SPU -set AIC_DCR [expr $AT91C_BASE_AIC + 0x00000138 ] +set AIC_DCR [expr {$AT91C_BASE_AIC + 0x00000138} ] global AIC_DCR -set AIC_FFER [expr $AT91C_BASE_AIC + 0x00000140 ] +set AIC_FFER [expr {$AT91C_BASE_AIC + 0x00000140} ] global AIC_FFER -set AIC_FFDR [expr $AT91C_BASE_AIC + 0x00000144 ] +set AIC_FFDR [expr {$AT91C_BASE_AIC + 0x00000144} ] global AIC_FFDR -set AIC_FFSR [expr $AT91C_BASE_AIC + 0x00000148 ] +set AIC_FFSR [expr {$AT91C_BASE_AIC + 0x00000148} ] global AIC_FFSR @@ -54,7 +54,7 @@ proc show_AIC_IMR_helper { NAME ADDR VAL } { proc show_AIC { } { global AIC_SMR - if [catch { mem2array aaa 32 $AIC_SMR [expr 32 * 4] } msg ] { + if [catch { mem2array aaa 32 $AIC_SMR [expr {32 * 4}] } msg ] { error [format "%s (%s)" $msg AIC_SMR] } echo "AIC_SMR: Mode & Type" @@ -71,7 +71,7 @@ proc show_AIC { } { incr x } global AIC_SVR - if [catch { mem2array aaa 32 $AIC_SVR [expr 32 * 4] } msg ] { + if [catch { mem2array aaa 32 $AIC_SVR [expr {32 * 4}] } msg ] { error [format "%s (%s)" $msg AIC_SVR] } echo "AIC_SVR: Vectors" diff --git a/tcl/chip/atmel/at91/at91_pmc.cfg b/tcl/chip/atmel/at91/at91_pmc.cfg index 88b137024a..0233cb4c16 100644 --- a/tcl/chip/atmel/at91/at91_pmc.cfg +++ b/tcl/chip/atmel/at91/at91_pmc.cfg @@ -1,113 +1,113 @@ -set AT91_PMC_SCER [expr ($AT91_PMC + 0x00)] ;# System Clock Enable Register -set AT91_PMC_SCDR [expr ($AT91_PMC + 0x04)] ;# System Clock Disable Register +set AT91_PMC_SCER [expr {$AT91_PMC + 0x00}] ;# System Clock Enable Register +set AT91_PMC_SCDR [expr {$AT91_PMC + 0x04}] ;# System Clock Disable Register -set AT91_PMC_SCSR [expr ($AT91_PMC + 0x08)] ;# System Clock Status Register -set AT91_PMC_PCK [expr (1 << 0)] ;# Processor Clock -set AT91RM9200_PMC_UDP [expr (1 << 1)] ;# USB Devcice Port Clock [AT91RM9200 only] -set AT91RM9200_PMC_MCKUDP [expr (1 << 2)] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] -set AT91CAP9_PMC_DDR [expr (1 << 2)] ;# DDR Clock [CAP9 revC & some SAM9 only] -set AT91RM9200_PMC_UHP [expr (1 << 4)] ;# USB Host Port Clock [AT91RM9200 only] -set AT91SAM926x_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91SAM926x only] -set AT91CAP9_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91CAP9 only] -set AT91SAM926x_PMC_UDP [expr (1 << 7)] ;# USB Devcice Port Clock [AT91SAM926x only] -set AT91_PMC_PCK0 [expr (1 << 8)] ;# Programmable Clock 0 -set AT91_PMC_PCK1 [expr (1 << 9)] ;# Programmable Clock 1 -set AT91_PMC_PCK2 [expr (1 << 10)] ;# Programmable Clock 2 -set AT91_PMC_PCK3 [expr (1 << 11)] ;# Programmable Clock 3 -set AT91_PMC_HCK0 [expr (1 << 16)] ;# AHB Clock (USB host) [AT91SAM9261 only] -set AT91_PMC_HCK1 [expr (1 << 17)] ;# AHB Clock (LCD) [AT91SAM9261 only] +set AT91_PMC_SCSR [expr {$AT91_PMC + 0x08}] ;# System Clock Status Register +set AT91_PMC_PCK [expr {1 << 0}] ;# Processor Clock +set AT91RM9200_PMC_UDP [expr {1 << 1}] ;# USB Devcice Port Clock [AT91RM9200 only] +set AT91RM9200_PMC_MCKUDP [expr {1 << 2}] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] +set AT91CAP9_PMC_DDR [expr {1 << 2}] ;# DDR Clock [CAP9 revC & some SAM9 only] +set AT91RM9200_PMC_UHP [expr {1 << 4}] ;# USB Host Port Clock [AT91RM9200 only] +set AT91SAM926x_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91SAM926x only] +set AT91CAP9_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91CAP9 only] +set AT91SAM926x_PMC_UDP [expr {1 << 7}] ;# USB Devcice Port Clock [AT91SAM926x only] +set AT91_PMC_PCK0 [expr {1 << 8}] ;# Programmable Clock 0 +set AT91_PMC_PCK1 [expr {1 << 9}] ;# Programmable Clock 1 +set AT91_PMC_PCK2 [expr {1 << 10}] ;# Programmable Clock 2 +set AT91_PMC_PCK3 [expr {1 << 11}] ;# Programmable Clock 3 +set AT91_PMC_HCK0 [expr {1 << 16}] ;# AHB Clock (USB host) [AT91SAM9261 only] +set AT91_PMC_HCK1 [expr {1 << 17}] ;# AHB Clock (LCD) [AT91SAM9261 only] -set AT91_PMC_PCER [expr ($AT91_PMC + 0x10)] ;# Peripheral Clock Enable Register -set AT91_PMC_PCDR [expr ($AT91_PMC + 0x14)] ;# Peripheral Clock Disable Register -set AT91_PMC_PCSR [expr ($AT91_PMC + 0x18)] ;# Peripheral Clock Status Register +set AT91_PMC_PCER [expr {$AT91_PMC + 0x10}] ;# Peripheral Clock Enable Register +set AT91_PMC_PCDR [expr {$AT91_PMC + 0x14}] ;# Peripheral Clock Disable Register +set AT91_PMC_PCSR [expr {$AT91_PMC + 0x18}] ;# Peripheral Clock Status Register -set AT91_CKGR_UCKR [expr ($AT91_PMC + 0x1C)] ;# UTMI Clock Register [some SAM9, CAP9] -set AT91_PMC_UPLLEN [expr (1 << 16)] ;# UTMI PLL Enable -set AT91_PMC_UPLLCOUNT [expr (0xf << 20)] ;# UTMI PLL Start-up Time -set AT91_PMC_BIASEN [expr (1 << 24)] ;# UTMI BIAS Enable -set AT91_PMC_BIASCOUNT [expr (0xf << 28)] ;# UTMI BIAS Start-up Time +set AT91_CKGR_UCKR [expr {$AT91_PMC + 0x1C}] ;# UTMI Clock Register [some SAM9, CAP9] +set AT91_PMC_UPLLEN [expr {1 << 16}] ;# UTMI PLL Enable +set AT91_PMC_UPLLCOUNT [expr {0xf << 20}] ;# UTMI PLL Start-up Time +set AT91_PMC_BIASEN [expr {1 << 24}] ;# UTMI BIAS Enable +set AT91_PMC_BIASCOUNT [expr {0xf << 28}] ;# UTMI BIAS Start-up Time -set AT91_CKGR_MOR [expr ($AT91_PMC + 0x20)] ;# Main Oscillator Register [not on SAM9RL] -set AT91_PMC_MOSCEN [expr (1 << 0)] ;# Main Oscillator Enable -set AT91_PMC_OSCBYPASS [expr (1 << 1)] ;# Oscillator Bypass [SAM9x, CAP9] -set AT91_PMC_OSCOUNT [expr (0xff << 8)] ;# Main Oscillator Start-up Time +set AT91_CKGR_MOR [expr {$AT91_PMC + 0x20}] ;# Main Oscillator Register [not on SAM9RL] +set AT91_PMC_MOSCEN [expr {1 << 0}] ;# Main Oscillator Enable +set AT91_PMC_OSCBYPASS [expr {1 << 1}] ;# Oscillator Bypass [SAM9x, CAP9] +set AT91_PMC_OSCOUNT [expr {0xff << 8}] ;# Main Oscillator Start-up Time -set AT91_CKGR_MCFR [expr ($AT91_PMC + 0x24)] ;# Main Clock Frequency Register -set AT91_PMC_MAINF [expr (0xffff << 0)] ;# Main Clock Frequency -set AT91_PMC_MAINRDY [expr (1 << 16)] ;# Main Clock Ready +set AT91_CKGR_MCFR [expr {$AT91_PMC + 0x24}] ;# Main Clock Frequency Register +set AT91_PMC_MAINF [expr {0xffff << 0}] ;# Main Clock Frequency +set AT91_PMC_MAINRDY [expr {1 << 16}] ;# Main Clock Ready -set AT91_CKGR_PLLAR [expr ($AT91_PMC + 0x28)] ;# PLL A Register -set AT91_CKGR_PLLBR [expr ($AT91_PMC + 0x2c)] ;# PLL B Register -set AT91_PMC_DIV [expr (0xff << 0)] ;# Divider -set AT91_PMC_PLLCOUNT [expr (0x3f << 8)] ;# PLL Counter -set AT91_PMC_OUT [expr (3 << 14)] ;# PLL Clock Frequency Range -set AT91_PMC_MUL [expr (0x7ff << 16)] ;# PLL Multiplier -set AT91_PMC_USBDIV [expr (3 << 28)] ;# USB Divisor (PLLB only) -set AT91_PMC_USBDIV_1 [expr (0 << 28)] -set AT91_PMC_USBDIV_2 [expr (1 << 28)] -set AT91_PMC_USBDIV_4 [expr (2 << 28)] -set AT91_PMC_USB96M [expr (1 << 28)] ;# Divider by 2 Enable (PLLB only) -set AT91_PMC_PLLA_WR_ERRATA [expr (1 << 29)] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register +set AT91_CKGR_PLLAR [expr {$AT91_PMC + 0x28}] ;# PLL A Register +set AT91_CKGR_PLLBR [expr {$AT91_PMC + 0x2c}] ;# PLL B Register +set AT91_PMC_DIV [expr {0xff << 0}] ;# Divider +set AT91_PMC_PLLCOUNT [expr {0x3f << 8}] ;# PLL Counter +set AT91_PMC_OUT [expr {3 << 14}] ;# PLL Clock Frequency Range +set AT91_PMC_MUL [expr {0x7ff << 16}] ;# PLL Multiplier +set AT91_PMC_USBDIV [expr {3 << 28}] ;# USB Divisor (PLLB only) +set AT91_PMC_USBDIV_1 [expr {0 << 28}] +set AT91_PMC_USBDIV_2 [expr {1 << 28}] +set AT91_PMC_USBDIV_4 [expr {2 << 28}] +set AT91_PMC_USB96M [expr {1 << 28}] ;# Divider by 2 Enable (PLLB only) +set AT91_PMC_PLLA_WR_ERRATA [expr {1 << 29}] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register -set AT91_PMC_MCKR [expr ($AT91_PMC + 0x30)] ;# Master Clock Register -set AT91_PMC_CSS [expr (3 << 0)] ;# Master Clock Selection -set AT91_PMC_CSS_SLOW [expr (0 << 0)] -set AT91_PMC_CSS_MAIN [expr (1 << 0)] -set AT91_PMC_CSS_PLLA [expr (2 << 0)] -set AT91_PMC_CSS_PLLB [expr (3 << 0)] -set AT91_PMC_CSS_UPLL [expr (3 << 0)] ;# [some SAM9 only] -set AT91_PMC_PRES [expr (7 << 2)] ;# Master Clock Prescaler -set AT91_PMC_PRES_1 [expr (0 << 2)] -set AT91_PMC_PRES_2 [expr (1 << 2)] -set AT91_PMC_PRES_4 [expr (2 << 2)] -set AT91_PMC_PRES_8 [expr (3 << 2)] -set AT91_PMC_PRES_16 [expr (4 << 2)] -set AT91_PMC_PRES_32 [expr (5 << 2)] -set AT91_PMC_PRES_64 [expr (6 << 2)] -set AT91_PMC_MDIV [expr (3 << 8)] ;# Master Clock Division -set AT91RM9200_PMC_MDIV_1 [expr (0 << 8)] ;# [AT91RM9200 only] -set AT91RM9200_PMC_MDIV_2 [expr (1 << 8)] -set AT91RM9200_PMC_MDIV_3 [expr (2 << 8)] -set AT91RM9200_PMC_MDIV_4 [expr (3 << 8)] -set AT91SAM9_PMC_MDIV_1 [expr (0 << 8)] ;# [SAM9,CAP9 only] -set AT91SAM9_PMC_MDIV_2 [expr (1 << 8)] -set AT91SAM9_PMC_MDIV_4 [expr (2 << 8)] -set AT91SAM9_PMC_MDIV_6 [expr (3 << 8)] ;# [some SAM9 only] -set AT91SAM9_PMC_MDIV_3 [expr (3 << 8)] ;# [some SAM9 only] -set AT91_PMC_PDIV [expr (1 << 12)] ;# Processor Clock Division [some SAM9 only] -set AT91_PMC_PDIV_1 [expr (0 << 12)] -set AT91_PMC_PDIV_2 [expr (1 << 12)] -set AT91_PMC_PLLADIV2 [expr (1 << 12)] ;# PLLA divisor by 2 [some SAM9 only] -set AT91_PMC_PLLADIV2_OFF [expr (0 << 12)] -set AT91_PMC_PLLADIV2_ON [expr (1 << 12)] +set AT91_PMC_MCKR [expr {$AT91_PMC + 0x30}] ;# Master Clock Register +set AT91_PMC_CSS [expr {3 << 0}] ;# Master Clock Selection +set AT91_PMC_CSS_SLOW [expr {0 << 0}] +set AT91_PMC_CSS_MAIN [expr {1 << 0}] +set AT91_PMC_CSS_PLLA [expr {2 << 0}] +set AT91_PMC_CSS_PLLB [expr {3 << 0}] +set AT91_PMC_CSS_UPLL [expr {3 << 0}] ;# [some SAM9 only] +set AT91_PMC_PRES [expr {7 << 2}] ;# Master Clock Prescaler +set AT91_PMC_PRES_1 [expr {0 << 2}] +set AT91_PMC_PRES_2 [expr {1 << 2}] +set AT91_PMC_PRES_4 [expr {2 << 2}] +set AT91_PMC_PRES_8 [expr {3 << 2}] +set AT91_PMC_PRES_16 [expr {4 << 2}] +set AT91_PMC_PRES_32 [expr {5 << 2}] +set AT91_PMC_PRES_64 [expr {6 << 2}] +set AT91_PMC_MDIV [expr {3 << 8}] ;# Master Clock Division +set AT91RM9200_PMC_MDIV_1 [expr {0 << 8}] ;# [AT91RM9200 only] +set AT91RM9200_PMC_MDIV_2 [expr {1 << 8}] +set AT91RM9200_PMC_MDIV_3 [expr {2 << 8}] +set AT91RM9200_PMC_MDIV_4 [expr {3 << 8}] +set AT91SAM9_PMC_MDIV_1 [expr {0 << 8}] ;# [SAM9,CAP9 only] +set AT91SAM9_PMC_MDIV_2 [expr {1 << 8}] +set AT91SAM9_PMC_MDIV_4 [expr {2 << 8}] +set AT91SAM9_PMC_MDIV_6 [expr {3 << 8}] ;# [some SAM9 only] +set AT91SAM9_PMC_MDIV_3 [expr {3 << 8}] ;# [some SAM9 only] +set AT91_PMC_PDIV [expr {1 << 12}] ;# Processor Clock Division [some SAM9 only] +set AT91_PMC_PDIV_1 [expr {0 << 12}] +set AT91_PMC_PDIV_2 [expr {1 << 12}] +set AT91_PMC_PLLADIV2 [expr {1 << 12}] ;# PLLA divisor by 2 [some SAM9 only] +set AT91_PMC_PLLADIV2_OFF [expr {0 << 12}] +set AT91_PMC_PLLADIV2_ON [expr {1 << 12}] -set AT91_PMC_USB [expr ($AT91_PMC + 0x38)] ;# USB Clock Register [some SAM9 only] -set AT91_PMC_USBS [expr (0x1 << 0)] ;# USB OHCI Input clock selection -set AT91_PMC_USBS_PLLA [expr (0 << 0)] -set AT91_PMC_USBS_UPLL [expr (1 << 0)] -set AT91_PMC_OHCIUSBDIV [expr (0xF << 8)] ;# Divider for USB OHCI Clock +set AT91_PMC_USB [expr {$AT91_PMC + 0x38}] ;# USB Clock Register [some SAM9 only] +set AT91_PMC_USBS [expr {0x1 << 0}] ;# USB OHCI Input clock selection +set AT91_PMC_USBS_PLLA [expr {0 << 0}] +set AT91_PMC_USBS_UPLL [expr {1 << 0}] +set AT91_PMC_OHCIUSBDIV [expr {0xF << 8}] ;# Divider for USB OHCI Clock ;# set AT91_PMC_PCKR(n) [expr ($AT91_PMC + 0x40 + ((n) * 4))] ;# Programmable Clock 0-N Registers -set AT91_PMC_CSSMCK [expr (0x1 << 8)] ;# CSS or Master Clock Selection -set AT91_PMC_CSSMCK_CSS [expr (0 << 8)] -set AT91_PMC_CSSMCK_MCK [expr (1 << 8)] +set AT91_PMC_CSSMCK [expr {0x1 << 8}] ;# CSS or Master Clock Selection +set AT91_PMC_CSSMCK_CSS [expr {0 << 8}] +set AT91_PMC_CSSMCK_MCK [expr {1 << 8}] -set AT91_PMC_IER [expr ($AT91_PMC + 0x60)] ;# Interrupt Enable Register -set AT91_PMC_IDR [expr ($AT91_PMC + 0x64)] ;# Interrupt Disable Register -set AT91_PMC_SR [expr ($AT91_PMC + 0x68)] ;# Status Register -set AT91_PMC_MOSCS [expr (1 << 0)] ;# MOSCS Flag -set AT91_PMC_LOCKA [expr (1 << 1)] ;# PLLA Lock -set AT91_PMC_LOCKB [expr (1 << 2)] ;# PLLB Lock -set AT91_PMC_MCKRDY [expr (1 << 3)] ;# Master Clock -set AT91_PMC_LOCKU [expr (1 << 6)] ;# UPLL Lock [some SAM9, AT91CAP9 only] -set AT91_PMC_OSCSEL [expr (1 << 7)] ;# Slow Clock Oscillator [AT91CAP9 revC only] -set AT91_PMC_PCK0RDY [expr (1 << 8)] ;# Programmable Clock 0 -set AT91_PMC_PCK1RDY [expr (1 << 9)] ;# Programmable Clock 1 -set AT91_PMC_PCK2RDY [expr (1 << 10)] ;# Programmable Clock 2 -set AT91_PMC_PCK3RDY [expr (1 << 11)] ;# Programmable Clock 3 -set AT91_PMC_IMR [expr ($AT91_PMC + 0x6c)] ;# Interrupt Mask Register +set AT91_PMC_IER [expr {$AT91_PMC + 0x60}] ;# Interrupt Enable Register +set AT91_PMC_IDR [expr {$AT91_PMC + 0x64}] ;# Interrupt Disable Register +set AT91_PMC_SR [expr {$AT91_PMC + 0x68}] ;# Status Register +set AT91_PMC_MOSCS [expr {1 << 0}] ;# MOSCS Flag +set AT91_PMC_LOCKA [expr {1 << 1}] ;# PLLA Lock +set AT91_PMC_LOCKB [expr {1 << 2}] ;# PLLB Lock +set AT91_PMC_MCKRDY [expr {1 << 3}] ;# Master Clock +set AT91_PMC_LOCKU [expr {1 << 6}] ;# UPLL Lock [some SAM9, AT91CAP9 only] +set AT91_PMC_OSCSEL [expr {1 << 7}] ;# Slow Clock Oscillator [AT91CAP9 revC only] +set AT91_PMC_PCK0RDY [expr {1 << 8}] ;# Programmable Clock 0 +set AT91_PMC_PCK1RDY [expr {1 << 9}] ;# Programmable Clock 1 +set AT91_PMC_PCK2RDY [expr {1 << 10}] ;# Programmable Clock 2 +set AT91_PMC_PCK3RDY [expr {1 << 11}] ;# Programmable Clock 3 +set AT91_PMC_IMR [expr {$AT91_PMC + 0x6c}] ;# Interrupt Mask Register -set AT91_PMC_PROT [expr ($AT91_PMC + 0xe4)] ;# Protect Register [AT91CAP9 revC only] +set AT91_PMC_PROT [expr {$AT91_PMC + 0xe4}] ;# Protect Register [AT91CAP9 revC only] set AT91_PMC_PROTKEY 0x504d4301 ;# Activation Code -set AT91_PMC_VER [expr ($AT91_PMC + 0xfc)] ;# PMC Module Version [AT91CAP9 only] +set AT91_PMC_VER [expr {$AT91_PMC + 0xfc}] ;# PMC Module Version [AT91CAP9 only] diff --git a/tcl/chip/atmel/at91/at91_rstc.cfg b/tcl/chip/atmel/at91/at91_rstc.cfg index ed60822278..6673fe6452 100644 --- a/tcl/chip/atmel/at91/at91_rstc.cfg +++ b/tcl/chip/atmel/at91/at91_rstc.cfg @@ -1,21 +1,21 @@ -set AT91_RSTC_CR [expr ($AT91_RSTC + 0x00)] ;# Reset Controller Control Register -set AT91_RSTC_PROCRST [expr (1 << 0)] ;# Processor Reset -set AT91_RSTC_PERRST [expr (1 << 2)] ;# Peripheral Reset -set AT91_RSTC_EXTRST [expr (1 << 3)] ;# External Reset -set AT91_RSTC_KEY [expr (0xa5 << 24)] ;# KEY Password +set AT91_RSTC_CR [expr {$AT91_RSTC + 0x00}] ;# Reset Controller Control Register +set AT91_RSTC_PROCRST [expr {1 << 0}] ;# Processor Reset +set AT91_RSTC_PERRST [expr {1 << 2}] ;# Peripheral Reset +set AT91_RSTC_EXTRST [expr {1 << 3}] ;# External Reset +set AT91_RSTC_KEY [expr {0xa5 << 24}] ;# KEY Password -set AT91_RSTC_SR [expr ($AT91_RSTC + 0x04)] ;# Reset Controller Status Register -set AT91_RSTC_URSTS [expr (1 << 0)] ;# User Reset Status -set AT91_RSTC_RSTTYP [expr (7 << 8)] ;# Reset Type -set AT91_RSTC_RSTTYP_GENERAL [expr (0 << 8)] -set AT91_RSTC_RSTTYP_WAKEUP [expr (1 << 8)] -set AT91_RSTC_RSTTYP_WATCHDOG [expr (2 << 8)] -set AT91_RSTC_RSTTYP_SOFTWARE [expr (3 << 8)] -set AT91_RSTC_RSTTYP_USER [expr (4 << 8)] -set AT91_RSTC_NRSTL [expr (1 << 16)] ;# NRST Pin Level -set AT91_RSTC_SRCMP [expr (1 << 17)] ;# Software Reset Command in Progress +set AT91_RSTC_SR [expr {$AT91_RSTC + 0x04}] ;# Reset Controller Status Register +set AT91_RSTC_URSTS [expr {1 << 0}] ;# User Reset Status +set AT91_RSTC_RSTTYP [expr {7 << 8}] ;# Reset Type +set AT91_RSTC_RSTTYP_GENERAL [expr {0 << 8}] +set AT91_RSTC_RSTTYP_WAKEUP [expr {1 << 8}] +set AT91_RSTC_RSTTYP_WATCHDOG [expr {2 << 8}] +set AT91_RSTC_RSTTYP_SOFTWARE [expr {3 << 8}] +set AT91_RSTC_RSTTYP_USER [expr {4 << 8}] +set AT91_RSTC_NRSTL [expr {1 << 16}] ;# NRST Pin Level +set AT91_RSTC_SRCMP [expr {1 << 17}] ;# Software Reset Command in Progress -set AT91_RSTC_MR [expr ($AT91_RSTC + 0x08)] ;# Reset Controller Mode Register -set AT91_RSTC_URSTEN [expr (1 << 0)] ;# User Reset Enable -set AT91_RSTC_URSTIEN [expr (1 << 4)] ;# User Reset Interrupt Enable -set AT91_RSTC_ERSTL [expr (0xf << 8)] ;# External Reset Length +set AT91_RSTC_MR [expr {$AT91_RSTC + 0x08}] ;# Reset Controller Mode Register +set AT91_RSTC_URSTEN [expr {1 << 0}] ;# User Reset Enable +set AT91_RSTC_URSTIEN [expr {1 << 4}] ;# User Reset Interrupt Enable +set AT91_RSTC_ERSTL [expr {0xf << 8}] ;# External Reset Length diff --git a/tcl/chip/atmel/at91/at91_wdt.cfg b/tcl/chip/atmel/at91/at91_wdt.cfg index a263cc7f6b..9b4e817e29 100644 --- a/tcl/chip/atmel/at91/at91_wdt.cfg +++ b/tcl/chip/atmel/at91/at91_wdt.cfg @@ -1,17 +1,17 @@ -set AT91_WDT_CR [expr ($AT91_WDT + 0x00)] ;# Watchdog Control Register -set AT91_WDT_WDRSTT [expr (1 << 0)] ;# Restart -set AT91_WDT_KEY [expr (0xa5 << 24)] ;# KEY Password +set AT91_WDT_CR [expr {$AT91_WDT + 0x00}] ;# Watchdog Control Register +set AT91_WDT_WDRSTT [expr {1 << 0}] ;# Restart +set AT91_WDT_KEY [expr {0xa5 << 24}] ;# KEY Password -set AT91_WDT_MR [expr ($AT91_WDT + 0x04)] ;# Watchdog Mode Register -set AT91_WDT_WDV [expr (0xfff << 0)] ;# Counter Value -set AT91_WDT_WDFIEN [expr (1 << 12)] ;# Fault Interrupt Enable -set AT91_WDT_WDRSTEN [expr (1 << 13)] ;# Reset Processor -set AT91_WDT_WDRPROC [expr (1 << 14)] ;# Timer Restart -set AT91_WDT_WDDIS [expr (1 << 15)] ;# Watchdog Disable -set AT91_WDT_WDD [expr (0xfff << 16)] ;# Delta Value -set AT91_WDT_WDDBGHLT [expr (1 << 28)] ;# Debug Halt -set AT91_WDT_WDIDLEHLT [expr (1 << 29)] ;# Idle Halt +set AT91_WDT_MR [expr {$AT91_WDT + 0x04}] ;# Watchdog Mode Register +set AT91_WDT_WDV [expr {0xfff << 0}] ;# Counter Value +set AT91_WDT_WDFIEN [expr {1 << 12}] ;# Fault Interrupt Enable +set AT91_WDT_WDRSTEN [expr {1 << 13}] ;# Reset Processor +set AT91_WDT_WDRPROC [expr {1 << 14}] ;# Timer Restart +set AT91_WDT_WDDIS [expr {1 << 15}] ;# Watchdog Disable +set AT91_WDT_WDD [expr {0xfff << 16}] ;# Delta Value +set AT91_WDT_WDDBGHLT [expr {1 << 28}] ;# Debug Halt +set AT91_WDT_WDIDLEHLT [expr {1 << 29}] ;# Idle Halt -set AT91_WDT_SR [expr ($AT91_WDT + 0x08)] ;# Watchdog Status Register -set AT91_WDT_WDUNF [expr (1 << 0)] ;# Watchdog Underflow -set AT91_WDT_WDERR [expr (1 << 1)] ;# Watchdog Error +set AT91_WDT_SR [expr {$AT91_WDT + 0x08}] ;# Watchdog Status Register +set AT91_WDT_WDUNF [expr {1 << 0}] ;# Watchdog Underflow +set AT91_WDT_WDERR [expr {1 << 1}] ;# Watchdog Error diff --git a/tcl/chip/atmel/at91/at91sam9261_matrix.cfg b/tcl/chip/atmel/at91/at91sam9261_matrix.cfg index dc8de23762..238e658414 100644 --- a/tcl/chip/atmel/at91/at91sam9261_matrix.cfg +++ b/tcl/chip/atmel/at91/at91sam9261_matrix.cfg @@ -1,46 +1,46 @@ -set AT91_MATRIX_MCFG [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register # -set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) -set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) +set AT91_MATRIX_MCFG [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register # +set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) +set AT91_MATRIX_RCB1 [expr {1 << 1}] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) -set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x04)] ;# Slave Configuration Register 0 -set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x08)] ;# Slave Configuration Register 1 -set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x0C)] ;# Slave Configuration Register 2 -set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x10)] ;# Slave Configuration Register 3 -set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x14)] ;# Slave Configuration Register 4 -set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst -set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type -set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)] -set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)] -set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)] -set AT91_MATRIX_FIXED_DEFMSTR [expr (7 << 18)] ;# Fixed Index of Default Master +set AT91_MATRIX_SCFG0 [expr {$AT91_MATRIX + 0x04}] ;# Slave Configuration Register 0 +set AT91_MATRIX_SCFG1 [expr {$AT91_MATRIX + 0x08}] ;# Slave Configuration Register 1 +set AT91_MATRIX_SCFG2 [expr {$AT91_MATRIX + 0x0C}] ;# Slave Configuration Register 2 +set AT91_MATRIX_SCFG3 [expr {$AT91_MATRIX + 0x10}] ;# Slave Configuration Register 3 +set AT91_MATRIX_SCFG4 [expr {$AT91_MATRIX + 0x14}] ;# Slave Configuration Register 4 +set AT91_MATRIX_SLOT_CYCLE [expr {0xff << 0}] ;# Maximum Number of Allowed Cycles for a Burst +set AT91_MATRIX_DEFMSTR_TYPE [expr {3 << 16}] ;# Default Master Type +set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr {0 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr {1 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr {2 << 16}] +set AT91_MATRIX_FIXED_DEFMSTR [expr {7 << 18}] ;# Fixed Index of Default Master -set AT91_MATRIX_TCR [expr ($AT91_MATRIX + 0x24)] ;# TCM Configuration Register -set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block -set AT91_MATRIX_ITCM_0 [expr (0 << 0)] -set AT91_MATRIX_ITCM_16 [expr (5 << 0)] -set AT91_MATRIX_ITCM_32 [expr (6 << 0)] -set AT91_MATRIX_ITCM_64 [expr (7 << 0)] -set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block -set AT91_MATRIX_DTCM_0 [expr (0 << 4)] -set AT91_MATRIX_DTCM_16 [expr (5 << 4)] -set AT91_MATRIX_DTCM_32 [expr (6 << 4)] -set AT91_MATRIX_DTCM_64 [expr (7 << 4)] +set AT91_MATRIX_TCR [expr {$AT91_MATRIX + 0x24}] ;# TCM Configuration Register +set AT91_MATRIX_ITCM_SIZE [expr {0xf << 0}] ;# Size of ITCM enabled memory block +set AT91_MATRIX_ITCM_0 [expr {0 << 0}] +set AT91_MATRIX_ITCM_16 [expr {5 << 0}] +set AT91_MATRIX_ITCM_32 [expr {6 << 0}] +set AT91_MATRIX_ITCM_64 [expr {7 << 0}] +set AT91_MATRIX_DTCM_SIZE [expr {0xf << 4}] ;# Size of DTCM enabled memory block +set AT91_MATRIX_DTCM_0 [expr {0 << 4}] +set AT91_MATRIX_DTCM_16 [expr {5 << 4}] +set AT91_MATRIX_DTCM_32 [expr {6 << 4}] +set AT91_MATRIX_DTCM_64 [expr {7 << 4}] -set AT91_MATRIX_EBICSA [expr ($AT91_MATRIX + 0x30)] ;# EBI Chip Select Assignment Register -set AT91_MATRIX_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment -set AT91_MATRIX_CS1A_SMC [expr (0 << 1)] -set AT91_MATRIX_CS1A_SDRAMC [expr (1 << 1)] -set AT91_MATRIX_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignment -set AT91_MATRIX_CS3A_SMC [expr (0 << 3)] -set AT91_MATRIX_CS3A_SMC_SMARTMEDIA [expr (1 << 3)] -set AT91_MATRIX_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment -set AT91_MATRIX_CS4A_SMC [expr (0 << 4)] -set AT91_MATRIX_CS4A_SMC_CF1 [expr (1 << 4)] -set AT91_MATRIX_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment -set AT91_MATRIX_CS5A_SMC [expr (0 << 5)] -set AT91_MATRIX_CS5A_SMC_CF2 [expr (1 << 5)] -set AT91_MATRIX_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration +set AT91_MATRIX_EBICSA [expr {$AT91_MATRIX + 0x30}] ;# EBI Chip Select Assignment Register +set AT91_MATRIX_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment +set AT91_MATRIX_CS1A_SMC [expr {0 << 1}] +set AT91_MATRIX_CS1A_SDRAMC [expr {1 << 1}] +set AT91_MATRIX_CS3A [expr {1 << 3}] ;# Chip Select 3 Assignment +set AT91_MATRIX_CS3A_SMC [expr {0 << 3}] +set AT91_MATRIX_CS3A_SMC_SMARTMEDIA [expr {1 << 3}] +set AT91_MATRIX_CS4A [expr {1 << 4}] ;# Chip Select 4 Assignment +set AT91_MATRIX_CS4A_SMC [expr {0 << 4}] +set AT91_MATRIX_CS4A_SMC_CF1 [expr {1 << 4}] +set AT91_MATRIX_CS5A [expr {1 << 5}] ;# Chip Select 5 Assignment +set AT91_MATRIX_CS5A_SMC [expr {0 << 5}] +set AT91_MATRIX_CS5A_SMC_CF2 [expr {1 << 5}] +set AT91_MATRIX_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration -set AT91_MATRIX_USBPUCR [expr ($AT91_MATRIX + 0x34)] ;# USB Pad Pull-Up Control Register -set AT91_MATRIX_USBPUCR_PUON [expr (1 << 30)] ;# USB Device PAD Pull-up Enable +set AT91_MATRIX_USBPUCR [expr {$AT91_MATRIX + 0x34}] ;# USB Pad Pull-Up Control Register +set AT91_MATRIX_USBPUCR_PUON [expr {1 << 30}] ;# USB Device PAD Pull-up Enable diff --git a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg index f287cd9bf2..b4a07d32df 100644 --- a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg +++ b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg @@ -1,110 +1,110 @@ -set AT91_MATRIX_MCFG0 [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register 0 -set AT91_MATRIX_MCFG1 [expr ($AT91_MATRIX + 0x04)] ;# Master Configuration Register 1 -set AT91_MATRIX_MCFG2 [expr ($AT91_MATRIX + 0x08)] ;# Master Configuration Register 2 -set AT91_MATRIX_MCFG3 [expr ($AT91_MATRIX + 0x0C)] ;# Master Configuration Register 3 -set AT91_MATRIX_MCFG4 [expr ($AT91_MATRIX + 0x10)] ;# Master Configuration Register 4 -set AT91_MATRIX_MCFG5 [expr ($AT91_MATRIX + 0x14)] ;# Master Configuration Register 5 -set AT91_MATRIX_MCFG6 [expr ($AT91_MATRIX + 0x18)] ;# Master Configuration Register 6 -set AT91_MATRIX_MCFG7 [expr ($AT91_MATRIX + 0x1C)] ;# Master Configuration Register 7 -set AT91_MATRIX_MCFG8 [expr ($AT91_MATRIX + 0x20)] ;# Master Configuration Register 8 -set AT91_MATRIX_ULBT [expr (7 << 0)] ;# Undefined Length Burst Type -set AT91_MATRIX_ULBT_INFINITE [expr (0 << 0)] -set AT91_MATRIX_ULBT_SINGLE [expr (1 << 0)] -set AT91_MATRIX_ULBT_FOUR [expr (2 << 0)] -set AT91_MATRIX_ULBT_EIGHT [expr (3 << 0)] -set AT91_MATRIX_ULBT_SIXTEEN [expr (4 << 0)] +set AT91_MATRIX_MCFG0 [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register 0 +set AT91_MATRIX_MCFG1 [expr {$AT91_MATRIX + 0x04}] ;# Master Configuration Register 1 +set AT91_MATRIX_MCFG2 [expr {$AT91_MATRIX + 0x08}] ;# Master Configuration Register 2 +set AT91_MATRIX_MCFG3 [expr {$AT91_MATRIX + 0x0C}] ;# Master Configuration Register 3 +set AT91_MATRIX_MCFG4 [expr {$AT91_MATRIX + 0x10}] ;# Master Configuration Register 4 +set AT91_MATRIX_MCFG5 [expr {$AT91_MATRIX + 0x14}] ;# Master Configuration Register 5 +set AT91_MATRIX_MCFG6 [expr {$AT91_MATRIX + 0x18}] ;# Master Configuration Register 6 +set AT91_MATRIX_MCFG7 [expr {$AT91_MATRIX + 0x1C}] ;# Master Configuration Register 7 +set AT91_MATRIX_MCFG8 [expr {$AT91_MATRIX + 0x20}] ;# Master Configuration Register 8 +set AT91_MATRIX_ULBT [expr {7 << 0}] ;# Undefined Length Burst Type +set AT91_MATRIX_ULBT_INFINITE [expr {0 << 0}] +set AT91_MATRIX_ULBT_SINGLE [expr {1 << 0}] +set AT91_MATRIX_ULBT_FOUR [expr {2 << 0}] +set AT91_MATRIX_ULBT_EIGHT [expr {3 << 0}] +set AT91_MATRIX_ULBT_SIXTEEN [expr {4 << 0}] -set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x40)] ;# Slave Configuration Register 0 -set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x44)] ;# Slave Configuration Register 1 -set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x48)] ;# Slave Configuration Register 2 -set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x4C)] ;# Slave Configuration Register 3 -set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x50)] ;# Slave Configuration Register 4 -set AT91_MATRIX_SCFG5 [expr ($AT91_MATRIX + 0x54)] ;# Slave Configuration Register 5 -set AT91_MATRIX_SCFG6 [expr ($AT91_MATRIX + 0x58)] ;# Slave Configuration Register 6 -set AT91_MATRIX_SCFG7 [expr ($AT91_MATRIX + 0x5C)] ;# Slave Configuration Register 7 -set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst -set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type -set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)] -set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)] -set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)] -set AT91_MATRIX_FIXED_DEFMSTR [expr (0xf << 18)] ;# Fixed Index of Default Master -set AT91_MATRIX_ARBT [expr (3 << 24)] ;# Arbitration Type -set AT91_MATRIX_ARBT_ROUND_ROBIN [expr (0 << 24)] -set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr (1 << 24)] +set AT91_MATRIX_SCFG0 [expr {$AT91_MATRIX + 0x40}] ;# Slave Configuration Register 0 +set AT91_MATRIX_SCFG1 [expr {$AT91_MATRIX + 0x44}] ;# Slave Configuration Register 1 +set AT91_MATRIX_SCFG2 [expr {$AT91_MATRIX + 0x48}] ;# Slave Configuration Register 2 +set AT91_MATRIX_SCFG3 [expr {$AT91_MATRIX + 0x4C}] ;# Slave Configuration Register 3 +set AT91_MATRIX_SCFG4 [expr {$AT91_MATRIX + 0x50}] ;# Slave Configuration Register 4 +set AT91_MATRIX_SCFG5 [expr {$AT91_MATRIX + 0x54}] ;# Slave Configuration Register 5 +set AT91_MATRIX_SCFG6 [expr {$AT91_MATRIX + 0x58}] ;# Slave Configuration Register 6 +set AT91_MATRIX_SCFG7 [expr {$AT91_MATRIX + 0x5C}] ;# Slave Configuration Register 7 +set AT91_MATRIX_SLOT_CYCLE [expr {0xff << 0}] ;# Maximum Number of Allowed Cycles for a Burst +set AT91_MATRIX_DEFMSTR_TYPE [expr {3 << 16}] ;# Default Master Type +set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr {0 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr {1 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr {2 << 16}] +set AT91_MATRIX_FIXED_DEFMSTR [expr {0xf << 18}] ;# Fixed Index of Default Master +set AT91_MATRIX_ARBT [expr {3 << 24}] ;# Arbitration Type +set AT91_MATRIX_ARBT_ROUND_ROBIN [expr {0 << 24}] +set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr {1 << 24}] -set AT91_MATRIX_PRAS0 [expr ($AT91_MATRIX + 0x80)] ;# Priority Register A for Slave 0 -set AT91_MATRIX_PRBS0 [expr ($AT91_MATRIX + 0x84)] ;# Priority Register B for Slave 0 -set AT91_MATRIX_PRAS1 [expr ($AT91_MATRIX + 0x88)] ;# Priority Register A for Slave 1 -set AT91_MATRIX_PRBS1 [expr ($AT91_MATRIX + 0x8C)] ;# Priority Register B for Slave 1 -set AT91_MATRIX_PRAS2 [expr ($AT91_MATRIX + 0x90)] ;# Priority Register A for Slave 2 -set AT91_MATRIX_PRBS2 [expr ($AT91_MATRIX + 0x94)] ;# Priority Register B for Slave 2 -set AT91_MATRIX_PRAS3 [expr ($AT91_MATRIX + 0x98)] ;# Priority Register A for Slave 3 -set AT91_MATRIX_PRBS3 [expr ($AT91_MATRIX + 0x9C)] ;# Priority Register B for Slave 3 -set AT91_MATRIX_PRAS4 [expr ($AT91_MATRIX + 0xA0)] ;# Priority Register A for Slave 4 -set AT91_MATRIX_PRBS4 [expr ($AT91_MATRIX + 0xA4)] ;# Priority Register B for Slave 4 -set AT91_MATRIX_PRAS5 [expr ($AT91_MATRIX + 0xA8)] ;# Priority Register A for Slave 5 -set AT91_MATRIX_PRBS5 [expr ($AT91_MATRIX + 0xAC)] ;# Priority Register B for Slave 5 -set AT91_MATRIX_PRAS6 [expr ($AT91_MATRIX + 0xB0)] ;# Priority Register A for Slave 6 -set AT91_MATRIX_PRBS6 [expr ($AT91_MATRIX + 0xB4)] ;# Priority Register B for Slave 6 -set AT91_MATRIX_PRAS7 [expr ($AT91_MATRIX + 0xB8)] ;# Priority Register A for Slave 7 -set AT91_MATRIX_PRBS7 [expr ($AT91_MATRIX + 0xBC)] ;# Priority Register B for Slave 7 -set AT91_MATRIX_M0PR [expr (3 << 0)] ;# Master 0 Priority -set AT91_MATRIX_M1PR [expr (3 << 4)] ;# Master 1 Priority -set AT91_MATRIX_M2PR [expr (3 << 8)] ;# Master 2 Priority -set AT91_MATRIX_M3PR [expr (3 << 12)] ;# Master 3 Priority -set AT91_MATRIX_M4PR [expr (3 << 16)] ;# Master 4 Priority -set AT91_MATRIX_M5PR [expr (3 << 20)] ;# Master 5 Priority -set AT91_MATRIX_M6PR [expr (3 << 24)] ;# Master 6 Priority -set AT91_MATRIX_M7PR [expr (3 << 28)] ;# Master 7 Priority -set AT91_MATRIX_M8PR [expr (3 << 0)] ;# Master 8 Priority (in Register B) +set AT91_MATRIX_PRAS0 [expr {$AT91_MATRIX + 0x80}] ;# Priority Register A for Slave 0 +set AT91_MATRIX_PRBS0 [expr {$AT91_MATRIX + 0x84}] ;# Priority Register B for Slave 0 +set AT91_MATRIX_PRAS1 [expr {$AT91_MATRIX + 0x88}] ;# Priority Register A for Slave 1 +set AT91_MATRIX_PRBS1 [expr {$AT91_MATRIX + 0x8C}] ;# Priority Register B for Slave 1 +set AT91_MATRIX_PRAS2 [expr {$AT91_MATRIX + 0x90}] ;# Priority Register A for Slave 2 +set AT91_MATRIX_PRBS2 [expr {$AT91_MATRIX + 0x94}] ;# Priority Register B for Slave 2 +set AT91_MATRIX_PRAS3 [expr {$AT91_MATRIX + 0x98}] ;# Priority Register A for Slave 3 +set AT91_MATRIX_PRBS3 [expr {$AT91_MATRIX + 0x9C}] ;# Priority Register B for Slave 3 +set AT91_MATRIX_PRAS4 [expr {$AT91_MATRIX + 0xA0}] ;# Priority Register A for Slave 4 +set AT91_MATRIX_PRBS4 [expr {$AT91_MATRIX + 0xA4}] ;# Priority Register B for Slave 4 +set AT91_MATRIX_PRAS5 [expr {$AT91_MATRIX + 0xA8}] ;# Priority Register A for Slave 5 +set AT91_MATRIX_PRBS5 [expr {$AT91_MATRIX + 0xAC}] ;# Priority Register B for Slave 5 +set AT91_MATRIX_PRAS6 [expr {$AT91_MATRIX + 0xB0}] ;# Priority Register A for Slave 6 +set AT91_MATRIX_PRBS6 [expr {$AT91_MATRIX + 0xB4}] ;# Priority Register B for Slave 6 +set AT91_MATRIX_PRAS7 [expr {$AT91_MATRIX + 0xB8}] ;# Priority Register A for Slave 7 +set AT91_MATRIX_PRBS7 [expr {$AT91_MATRIX + 0xBC}] ;# Priority Register B for Slave 7 +set AT91_MATRIX_M0PR [expr {3 << 0}] ;# Master 0 Priority +set AT91_MATRIX_M1PR [expr {3 << 4}] ;# Master 1 Priority +set AT91_MATRIX_M2PR [expr {3 << 8}] ;# Master 2 Priority +set AT91_MATRIX_M3PR [expr {3 << 12}] ;# Master 3 Priority +set AT91_MATRIX_M4PR [expr {3 << 16}] ;# Master 4 Priority +set AT91_MATRIX_M5PR [expr {3 << 20}] ;# Master 5 Priority +set AT91_MATRIX_M6PR [expr {3 << 24}] ;# Master 6 Priority +set AT91_MATRIX_M7PR [expr {3 << 28}] ;# Master 7 Priority +set AT91_MATRIX_M8PR [expr {3 << 0}] ;# Master 8 Priority (in Register B) -set AT91_MATRIX_MRCR [expr ($AT91_MATRIX + 0x100)] ;# Master Remap Control Register -set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) -set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) -set AT91_MATRIX_RCB2 [expr (1 << 2)] -set AT91_MATRIX_RCB3 [expr (1 << 3)] -set AT91_MATRIX_RCB4 [expr (1 << 4)] -set AT91_MATRIX_RCB5 [expr (1 << 5)] -set AT91_MATRIX_RCB6 [expr (1 << 6)] -set AT91_MATRIX_RCB7 [expr (1 << 7)] -set AT91_MATRIX_RCB8 [expr (1 << 8)] +set AT91_MATRIX_MRCR [expr {$AT91_MATRIX + 0x100}] ;# Master Remap Control Register +set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) +set AT91_MATRIX_RCB1 [expr {1 << 1}] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) +set AT91_MATRIX_RCB2 [expr {1 << 2}] +set AT91_MATRIX_RCB3 [expr {1 << 3}] +set AT91_MATRIX_RCB4 [expr {1 << 4}] +set AT91_MATRIX_RCB5 [expr {1 << 5}] +set AT91_MATRIX_RCB6 [expr {1 << 6}] +set AT91_MATRIX_RCB7 [expr {1 << 7}] +set AT91_MATRIX_RCB8 [expr {1 << 8}] -set AT91_MATRIX_TCMR [expr ($AT91_MATRIX + 0x114)] ;# TCM Configuration Register -set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block -set AT91_MATRIX_ITCM_0 [expr (0 << 0)] -set AT91_MATRIX_ITCM_16 [expr (5 << 0)] -set AT91_MATRIX_ITCM_32 [expr (6 << 0)] -set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block -set AT91_MATRIX_DTCM_0 [expr (0 << 4)] -set AT91_MATRIX_DTCM_16 [expr (5 << 4)] -set AT91_MATRIX_DTCM_32 [expr (6 << 4)] +set AT91_MATRIX_TCMR [expr {$AT91_MATRIX + 0x114}] ;# TCM Configuration Register +set AT91_MATRIX_ITCM_SIZE [expr {0xf << 0}] ;# Size of ITCM enabled memory block +set AT91_MATRIX_ITCM_0 [expr {0 << 0}] +set AT91_MATRIX_ITCM_16 [expr {5 << 0}] +set AT91_MATRIX_ITCM_32 [expr {6 << 0}] +set AT91_MATRIX_DTCM_SIZE [expr {0xf << 4}] ;# Size of DTCM enabled memory block +set AT91_MATRIX_DTCM_0 [expr {0 << 4}] +set AT91_MATRIX_DTCM_16 [expr {5 << 4}] +set AT91_MATRIX_DTCM_32 [expr {6 << 4}] -set AT91_MATRIX_EBI0CSA [expr ($AT91_MATRIX + 0x120)] ;# EBI0 Chip Select Assignment Register -set AT91_MATRIX_EBI0_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment -set AT91_MATRIX_EBI0_CS1A_SMC [expr (0 << 1)] -set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr (1 << 1)] -set AT91_MATRIX_EBI0_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignmen -set AT91_MATRIX_EBI0_CS3A_SMC [expr (0 << 3)] -set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr (1 << 3)] -set AT91_MATRIX_EBI0_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment -set AT91_MATRIX_EBI0_CS4A_SMC [expr (0 << 4)] -set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr (1 << 4)] -set AT91_MATRIX_EBI0_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment -set AT91_MATRIX_EBI0_CS5A_SMC [expr (0 << 5)] -set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr (1 << 5)] -set AT91_MATRIX_EBI0_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration -set AT91_MATRIX_EBI0_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection -set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr (0 << 16)] -set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr (1 << 16)] +set AT91_MATRIX_EBI0CSA [expr {$AT91_MATRIX + 0x120}] ;# EBI0 Chip Select Assignment Register +set AT91_MATRIX_EBI0_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment +set AT91_MATRIX_EBI0_CS1A_SMC [expr {0 << 1}] +set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr {1 << 1}] +set AT91_MATRIX_EBI0_CS3A [expr {1 << 3}] ;# Chip Select 3 Assignmen +set AT91_MATRIX_EBI0_CS3A_SMC [expr {0 << 3}] +set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr {1 << 3}] +set AT91_MATRIX_EBI0_CS4A [expr {1 << 4}] ;# Chip Select 4 Assignment +set AT91_MATRIX_EBI0_CS4A_SMC [expr {0 << 4}] +set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr {1 << 4}] +set AT91_MATRIX_EBI0_CS5A [expr {1 << 5}] ;# Chip Select 5 Assignment +set AT91_MATRIX_EBI0_CS5A_SMC [expr {0 << 5}] +set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr {1 << 5}] +set AT91_MATRIX_EBI0_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration +set AT91_MATRIX_EBI0_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection +set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr {0 << 16}] +set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr {1 << 16}] -set AT91_MATRIX_EBI1CSA [expr ($AT91_MATRIX + 0x124)] ;# EBI1 Chip Select Assignment Register -set AT91_MATRIX_EBI1_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment -set AT91_MATRIX_EBI1_CS1A_SMC [expr (0 << 1)] -set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr (1 << 1)] -set AT91_MATRIX_EBI1_CS2A [expr (1 << 3)] ;# Chip Select 3 Assignment -set AT91_MATRIX_EBI1_CS2A_SMC [expr (0 << 3)] -set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr (1 << 3)] -set AT91_MATRIX_EBI1_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration -set AT91_MATRIX_EBI1_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection -set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr (0 << 16)] -set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr (1 << 16)] +set AT91_MATRIX_EBI1CSA [expr {$AT91_MATRIX + 0x124}] ;# EBI1 Chip Select Assignment Register +set AT91_MATRIX_EBI1_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment +set AT91_MATRIX_EBI1_CS1A_SMC [expr {0 << 1}] +set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr {1 << 1}] +set AT91_MATRIX_EBI1_CS2A [expr {1 << 3}] ;# Chip Select 3 Assignment +set AT91_MATRIX_EBI1_CS2A_SMC [expr {0 << 3}] +set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr {1 << 3}] +set AT91_MATRIX_EBI1_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration +set AT91_MATRIX_EBI1_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection +set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr {0 << 16}] +set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr {1 << 16}] diff --git a/tcl/chip/atmel/at91/at91sam9_init.cfg b/tcl/chip/atmel/at91/at91sam9_init.cfg index 2d78d241db..688cb1f4c4 100644 --- a/tcl/chip/atmel/at91/at91sam9_init.cfg +++ b/tcl/chip/atmel/at91/at91sam9_init.cfg @@ -12,8 +12,8 @@ proc at91sam9_reset_start { } { halt wait_halt 10000 set rstc_mr_val [expr $::AT91_RSTC_KEY] - set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))] - set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)] + set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}] + set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset. } @@ -21,14 +21,14 @@ proc at91sam9_reset_init { config } { mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog - set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))] + set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}] mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc. while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 } set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog - set pllar_val [expr ($pllar_val | $::AT91_PMC_OUT)] - set pllar_val [expr ($pllar_val | $::AT91_PMC_PLLCOUNT)] + set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}] + set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}] set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)] set pllar_val [expr ($pllar_val | $config(master_pll_div))] @@ -37,9 +37,9 @@ proc at91sam9_reset_init { config } { ;# PCK/2 = MCK Master Clock from PLLA set mckr_val [expr $::AT91_PMC_CSS_PLLA] - set mckr_val [expr ($mckr_val | $::AT91_PMC_PRES_1)] - set mckr_val [expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)] - set mckr_val [expr ($mckr_val | $::AT91_PMC_PDIV_1)] + set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}] + set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}] + set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}] mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz) while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 } @@ -51,19 +51,19 @@ proc at91sam9_reset_init { config } { arm7_9 fast_memory_access enable set rstc_mr_val [expr ($::AT91_RSTC_KEY)] - set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)] + set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable if { [info exists config(sdram_piod)] } { - set pdr_addr [expr ($::AT91_PIOD + $::PIO_PDR)] - set pudr_addr [expr ($::AT91_PIOD + $::PIO_PUDR)] - set asr_addr [expr ($::AT91_PIOD + $::PIO_ASR)] + set pdr_addr [expr {$::AT91_PIOD + $::PIO_PDR}] + set pudr_addr [expr {$::AT91_PIOD + $::PIO_PUDR}] + set asr_addr [expr {$::AT91_PIOD + $::PIO_ASR}] mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16] mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16] mww $asr_addr 0xffff0000 } else { - set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)] - set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)] + set pdr_addr [expr {$::AT91_PIOC + $::PIO_PDR}] + set pudr_addr [expr {$::AT91_PIOC + $::PIO_PUDR}] mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16] mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16] } diff --git a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg index dbca497b28..7b09369de9 100644 --- a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg +++ b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg @@ -1,7 +1,7 @@ # SDRAM Controller (SDRAMC) registers -set AT91_SDRAMC_MR [expr ($AT91_SDRAMC + 0x00)] ;# SDRAM Controller Mode Register -set AT91_SDRAMC_MODE [expr (0xf << 0)] ;# Command Mode +set AT91_SDRAMC_MR [expr {$AT91_SDRAMC + 0x00}] ;# SDRAM Controller Mode Register +set AT91_SDRAMC_MODE [expr {0xf << 0}] ;# Command Mode set AT91_SDRAMC_MODE_NORMAL 0 set AT91_SDRAMC_MODE_NOP 1 set AT91_SDRAMC_MODE_PRECHARGE 2 @@ -10,57 +10,57 @@ set AT91_SDRAMC_MODE_REFRESH 4 set AT91_SDRAMC_MODE_EXT_LMR 5 set AT91_SDRAMC_MODE_DEEP 6 -set AT91_SDRAMC_TR [expr ($AT91_SDRAMC + 0x04)] ;# SDRAM Controller Refresh Timer Register -set AT91_SDRAMC_COUNT [expr (0xfff << 0)] ;# Refresh Timer Counter +set AT91_SDRAMC_TR [expr {$AT91_SDRAMC + 0x04}] ;# SDRAM Controller Refresh Timer Register +set AT91_SDRAMC_COUNT [expr {0xfff << 0}] ;# Refresh Timer Counter -set AT91_SDRAMC_CR [expr ($AT91_SDRAMC + 0x08)] ;# SDRAM Controller Configuration Register -set AT91_SDRAMC_NC [expr (3 << 0)] ;# Number of Column Bits -set AT91_SDRAMC_NC_8 [expr (0 << 0)] -set AT91_SDRAMC_NC_9 [expr (1 << 0)] -set AT91_SDRAMC_NC_10 [expr (2 << 0)] -set AT91_SDRAMC_NC_11 [expr (3 << 0)] -set AT91_SDRAMC_NR [expr (3 << 2)] ;# Number of Row Bits -set AT91_SDRAMC_NR_11 [expr (0 << 2)] -set AT91_SDRAMC_NR_12 [expr (1 << 2)] -set AT91_SDRAMC_NR_13 [expr (2 << 2)] -set AT91_SDRAMC_NB [expr (1 << 4)] ;# Number of Banks -set AT91_SDRAMC_NB_2 [expr (0 << 4)] -set AT91_SDRAMC_NB_4 [expr (1 << 4)] -set AT91_SDRAMC_CAS [expr (3 << 5)] ;# CAS Latency -set AT91_SDRAMC_CAS_1 [expr (1 << 5)] -set AT91_SDRAMC_CAS_2 [expr (2 << 5)] -set AT91_SDRAMC_CAS_3 [expr (3 << 5)] -set AT91_SDRAMC_DBW [expr (1 << 7)] ;# Data Bus Width -set AT91_SDRAMC_DBW_32 [expr (0 << 7)] -set AT91_SDRAMC_DBW_16 [expr (1 << 7)] -set AT91_SDRAMC_TWR [expr (0xf << 8)] ;# Write Recovery Delay -set AT91_SDRAMC_TRC [expr (0xf << 12)] ;# Row Cycle Delay -set AT91_SDRAMC_TRP [expr (0xf << 16)] ;# Row Precharge Delay -set AT91_SDRAMC_TRCD [expr (0xf << 20)] ;# Row to Column Delay -set AT91_SDRAMC_TRAS [expr (0xf << 24)] ;# Active to Precharge Delay -set AT91_SDRAMC_TXSR [expr (0xf << 28)] ;# Exit Self Refresh to Active Delay +set AT91_SDRAMC_CR [expr {$AT91_SDRAMC + 0x08}] ;# SDRAM Controller Configuration Register +set AT91_SDRAMC_NC [expr {3 << 0}] ;# Number of Column Bits +set AT91_SDRAMC_NC_8 [expr {0 << 0}] +set AT91_SDRAMC_NC_9 [expr {1 << 0}] +set AT91_SDRAMC_NC_10 [expr {2 << 0}] +set AT91_SDRAMC_NC_11 [expr {3 << 0}] +set AT91_SDRAMC_NR [expr {3 << 2}] ;# Number of Row Bits +set AT91_SDRAMC_NR_11 [expr {0 << 2}] +set AT91_SDRAMC_NR_12 [expr {1 << 2}] +set AT91_SDRAMC_NR_13 [expr {2 << 2}] +set AT91_SDRAMC_NB [expr {1 << 4}] ;# Number of Banks +set AT91_SDRAMC_NB_2 [expr {0 << 4}] +set AT91_SDRAMC_NB_4 [expr {1 << 4}] +set AT91_SDRAMC_CAS [expr {3 << 5}] ;# CAS Latency +set AT91_SDRAMC_CAS_1 [expr {1 << 5}] +set AT91_SDRAMC_CAS_2 [expr {2 << 5}] +set AT91_SDRAMC_CAS_3 [expr {3 << 5}] +set AT91_SDRAMC_DBW [expr {1 << 7}] ;# Data Bus Width +set AT91_SDRAMC_DBW_32 [expr {0 << 7}] +set AT91_SDRAMC_DBW_16 [expr {1 << 7}] +set AT91_SDRAMC_TWR [expr {0xf << 8}] ;# Write Recovery Delay +set AT91_SDRAMC_TRC [expr {0xf << 12}] ;# Row Cycle Delay +set AT91_SDRAMC_TRP [expr {0xf << 16}] ;# Row Precharge Delay +set AT91_SDRAMC_TRCD [expr {0xf << 20}] ;# Row to Column Delay +set AT91_SDRAMC_TRAS [expr {0xf << 24}] ;# Active to Precharge Delay +set AT91_SDRAMC_TXSR [expr {0xf << 28}] ;# Exit Self Refresh to Active Delay -set AT91_SDRAMC_LPR [expr ($AT91_SDRAMC + 0x10)] ;# SDRAM Controller Low Power Register -set AT91_SDRAMC_LPCB [expr (3 << 0)] ;# Low-power Configurations +set AT91_SDRAMC_LPR [expr {$AT91_SDRAMC + 0x10}] ;# SDRAM Controller Low Power Register +set AT91_SDRAMC_LPCB [expr {3 << 0}] ;# Low-power Configurations set AT91_SDRAMC_LPCB_DISABLE 0 set AT91_SDRAMC_LPCB_SELF_REFRESH 1 set AT91_SDRAMC_LPCB_POWER_DOWN 2 set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 -set AT91_SDRAMC_PASR [expr (7 << 4)] ;# Partial Array Self Refresh -set AT91_SDRAMC_TCSR [expr (3 << 8)] ;# Temperature Compensated Self Refresh -set AT91_SDRAMC_DS [expr (3 << 10)] ;# Drive Strength -set AT91_SDRAMC_TIMEOUT [expr (3 << 12)] ;# Time to define when Low Power Mode is enabled -set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr (0 << 12)] -set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr (1 << 12)] -set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr (2 << 12)] +set AT91_SDRAMC_PASR [expr {7 << 4}] ;# Partial Array Self Refresh +set AT91_SDRAMC_TCSR [expr {3 << 8}] ;# Temperature Compensated Self Refresh +set AT91_SDRAMC_DS [expr {3 << 10}] ;# Drive Strength +set AT91_SDRAMC_TIMEOUT [expr {3 << 12}] ;# Time to define when Low Power Mode is enabled +set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr {0 << 12}] +set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr {1 << 12}] +set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr {2 << 12}] -set AT91_SDRAMC_IER [expr ($AT91_SDRAMC + 0x14)] ;# SDRAM Controller Interrupt Enable Register -set AT91_SDRAMC_IDR [expr ($AT91_SDRAMC + 0x18)] ;# SDRAM Controller Interrupt Disable Register -set AT91_SDRAMC_IMR [expr ($AT91_SDRAMC + 0x1C)] ;# SDRAM Controller Interrupt Mask Register -set AT91_SDRAMC_ISR [expr ($AT91_SDRAMC + 0x20)] ;# SDRAM Controller Interrupt Status Register -set AT91_SDRAMC_RES [expr (1 << 0)] ;# Refresh Error Status +set AT91_SDRAMC_IER [expr {$AT91_SDRAMC + 0x14}] ;# SDRAM Controller Interrupt Enable Register +set AT91_SDRAMC_IDR [expr {$AT91_SDRAMC + 0x18}] ;# SDRAM Controller Interrupt Disable Register +set AT91_SDRAMC_IMR [expr {$AT91_SDRAMC + 0x1C}] ;# SDRAM Controller Interrupt Mask Register +set AT91_SDRAMC_ISR [expr {$AT91_SDRAMC + 0x20}] ;# SDRAM Controller Interrupt Status Register +set AT91_SDRAMC_RES [expr {1 << 0}] ;# Refresh Error Status -set AT91_SDRAMC_MDR [expr ($AT91_SDRAMC + 0x24)] ;# SDRAM Memory Device Register -set AT91_SDRAMC_MD [expr (3 << 0)] ;# Memory Device Type +set AT91_SDRAMC_MDR [expr {$AT91_SDRAMC + 0x24}] ;# SDRAM Memory Device Register +set AT91_SDRAMC_MD [expr {3 << 0}] ;# Memory Device Type set AT91_SDRAMC_MD_SDRAM 0 set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 diff --git a/tcl/chip/atmel/at91/at91sam9_smc.cfg b/tcl/chip/atmel/at91/at91sam9_smc.cfg index 7dc7638582..3a76d147b7 100644 --- a/tcl/chip/atmel/at91/at91sam9_smc.cfg +++ b/tcl/chip/atmel/at91/at91sam9_smc.cfg @@ -1,20 +1,20 @@ -set AT91_SMC_READMODE [expr (1 << 0)] ;# Read Mode -set AT91_SMC_WRITEMODE [expr (1 << 1)] ;# Write Mode -set AT91_SMC_EXNWMODE [expr (3 << 4)] ;# NWAIT Mode -set AT91_SMC_EXNWMODE_DISABLE [expr (0 << 4)] -set AT91_SMC_EXNWMODE_FROZEN [expr (2 << 4)] -set AT91_SMC_EXNWMODE_READY [expr (3 << 4)] -set AT91_SMC_BAT [expr (1 << 8)] ;# Byte Access Type -set AT91_SMC_BAT_SELECT [expr (0 << 8)] -set AT91_SMC_BAT_WRITE [expr (1 << 8)] -set AT91_SMC_DBW [expr (3 << 12)] ;# Data Bus Width */ -set AT91_SMC_DBW_8 [expr (0 << 12)] -set AT91_SMC_DBW_16 [expr (1 << 12)] -set AT91_SMC_DBW_32 [expr (2 << 12)] -set AT91_SMC_TDFMODE [expr (1 << 20)] ;# TDF Optimization - Enabled -set AT91_SMC_PMEN [expr (1 << 24)] ;# Page Mode Enabled -set AT91_SMC_PS [expr (3 << 28)] ;# Page Size -set AT91_SMC_PS_4 [expr (0 << 28)] -set AT91_SMC_PS_8 [expr (1 << 28)] -set AT91_SMC_PS_16 [expr (2 << 28)] -set AT91_SMC_PS_32 [expr (3 << 28)] +set AT91_SMC_READMODE [expr {1 << 0}] ;# Read Mode +set AT91_SMC_WRITEMODE [expr {1 << 1}] ;# Write Mode +set AT91_SMC_EXNWMODE [expr {3 << 4}] ;# NWAIT Mode +set AT91_SMC_EXNWMODE_DISABLE [expr {0 << 4}] +set AT91_SMC_EXNWMODE_FROZEN [expr {2 << 4}] +set AT91_SMC_EXNWMODE_READY [expr {3 << 4}] +set AT91_SMC_BAT [expr {1 << 8}] ;# Byte Access Type +set AT91_SMC_BAT_SELECT [expr {0 << 8}] +set AT91_SMC_BAT_WRITE [expr {1 << 8}] +set AT91_SMC_DBW [expr {3 << 12}] ;# Data Bus Width */ +set AT91_SMC_DBW_8 [expr {0 << 12}] +set AT91_SMC_DBW_16 [expr {1 << 12}] +set AT91_SMC_DBW_32 [expr {2 << 12}] +set AT91_SMC_TDFMODE [expr {1 << 20}] ;# TDF Optimization - Enabled +set AT91_SMC_PMEN [expr {1 << 24}] ;# Page Mode Enabled +set AT91_SMC_PS [expr {3 << 28}] ;# Page Size +set AT91_SMC_PS_4 [expr {0 << 28}] +set AT91_SMC_PS_8 [expr {1 << 28}] +set AT91_SMC_PS_16 [expr {2 << 28}] +set AT91_SMC_PS_32 [expr {3 << 28}] diff --git a/tcl/chip/atmel/at91/rtt.tcl b/tcl/chip/atmel/at91/rtt.tcl index 2dd74fab92..3e3d414f41 100644 --- a/tcl/chip/atmel/at91/rtt.tcl +++ b/tcl/chip/atmel/at91/rtt.tcl @@ -1,15 +1,15 @@ -set RTTC_RTMR [expr $AT91C_BASE_RTTC + 0x00] -set RTTC_RTAR [expr $AT91C_BASE_RTTC + 0x04] -set RTTC_RTVR [expr $AT91C_BASE_RTTC + 0x08] -set RTTC_RTSR [expr $AT91C_BASE_RTTC + 0x0c] +set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}] +set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}] +set RTTC_RTVR [expr {$AT91C_BASE_RTTC + 0x08}] +set RTTC_RTSR [expr {$AT91C_BASE_RTTC + 0x0c}] global RTTC_RTMR global RTTC_RTAR global RTTC_RTVR global RTTC_RTSR proc show_RTTC_RTMR_helper { NAME ADDR VAL } { - set rtpres [expr $VAL & 0x0ffff] + set rtpres [expr {$VAL & 0x0ffff}] global BIT16 BIT17 if { $rtpres == 0 } { set rtpres 65536; diff --git a/tcl/chip/atmel/at91/usarts.tcl b/tcl/chip/atmel/at91/usarts.tcl index ecc4f60342..95aced882d 100644 --- a/tcl/chip/atmel/at91/usarts.tcl +++ b/tcl/chip/atmel/at91/usarts.tcl @@ -1,20 +1,20 @@ # the DBGU and USARTs are 'almost' indentical' -set DBGU_CR [expr $AT91C_BASE_DBGU + 0x00000000] -set DBGU_MR [expr $AT91C_BASE_DBGU + 0x00000004] -set DBGU_IER [expr $AT91C_BASE_DBGU + 0x00000008] -set DBGU_IDR [expr $AT91C_BASE_DBGU + 0x0000000C] -set DBGU_IMR [expr $AT91C_BASE_DBGU + 0x00000010] -set DBGU_CSR [expr $AT91C_BASE_DBGU + 0x00000014] -set DBGU_RHR [expr $AT91C_BASE_DBGU + 0x00000018] -set DBGU_THR [expr $AT91C_BASE_DBGU + 0x0000001C] -set DBGU_BRGR [expr $AT91C_BASE_DBGU + 0x00000020] +set DBGU_CR [expr {$AT91C_BASE_DBGU + 0x00000000}] +set DBGU_MR [expr {$AT91C_BASE_DBGU + 0x00000004}] +set DBGU_IER [expr {$AT91C_BASE_DBGU + 0x00000008}] +set DBGU_IDR [expr {$AT91C_BASE_DBGU + 0x0000000C}] +set DBGU_IMR [expr {$AT91C_BASE_DBGU + 0x00000010}] +set DBGU_CSR [expr {$AT91C_BASE_DBGU + 0x00000014}] +set DBGU_RHR [expr {$AT91C_BASE_DBGU + 0x00000018}] +set DBGU_THR [expr {$AT91C_BASE_DBGU + 0x0000001C}] +set DBGU_BRGR [expr {$AT91C_BASE_DBGU + 0x00000020}] # no RTOR # no TTGR # no FIDI # no NER -set DBGU_CIDR [expr $AT91C_BASE_DBGU + 0x00000040] -set DBGU_EXID [expr $AT91C_BASE_DBGU + 0x00000044] -set DBGU_FNTR [expr $AT91C_BASE_DBGU + 0x00000048] +set DBGU_CIDR [expr {$AT91C_BASE_DBGU + 0x00000040}] +set DBGU_EXID [expr {$AT91C_BASE_DBGU + 0x00000044}] +set DBGU_FNTR [expr {$AT91C_BASE_DBGU + 0x00000048}] set USx_CR 0x00000000 @@ -54,7 +54,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } { 2 { set s "Force=0" } 3 { set s "Force=1" } * { - set $x [expr $x & 6] + set $x [expr {$x & 6}] switch -exact $x { 4 { set s "None" } 6 { set s "Multidrop Mode" } diff --git a/tcl/chip/st/spear/quirk_no_srst.tcl b/tcl/chip/st/spear/quirk_no_srst.tcl index fd02d07c1d..515fb5824a 100644 --- a/tcl/chip/st/spear/quirk_no_srst.tcl +++ b/tcl/chip/st/spear/quirk_no_srst.tcl @@ -38,8 +38,8 @@ proc sp_reset_deassert_post {} { poll on echo "====> Press reset button on the board <====" - for {set i 0} { [sp_is_halted] == 0 } { set i [expr $i + 1]} { - echo -n "$bar([expr $i & 3])\r" + for {set i 0} { [sp_is_halted] == 0 } { set i [expr {$i + 1}]} { + echo -n "$bar([expr {$i & 3}])\r" sleep 200 } diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl index a9787d11d4..22fe06eaf7 100644 --- a/tcl/chip/st/spear/spear3xx_ddr.tcl +++ b/tcl/chip/st/spear/spear3xx_ddr.tcl @@ -28,7 +28,7 @@ proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} { if { $ddr_chips == 2 } { echo [format \ "Double chip DDR memory. Total memory size 0x%08x byte" \ - [expr 2 * $ddr_size]] + [expr {2 * $ddr_size}]] } else { echo [format \ "Single chip DDR memory. Memory size 0x%08x byte" \ diff --git a/tcl/chip/st/stm32/stm32_rcc.tcl b/tcl/chip/st/stm32/stm32_rcc.tcl index 07718b6493..fa652a2e65 100644 --- a/tcl/chip/st/stm32/stm32_rcc.tcl +++ b/tcl/chip/st/stm32/stm32_rcc.tcl @@ -1,14 +1,14 @@ -set RCC_CR [expr $RCC_BASE + 0x00] -set RCC_CFGR [expr $RCC_BASE + 0x04] -set RCC_CIR [expr $RCC_BASE + 0x08] -set RCC_APB2RSTR [expr $RCC_BASE + 0x0c] -set RCC_APB1RSTR [expr $RCC_BASE + 0x10] -set RCC_AHBENR [expr $RCC_BASE + 0x14] -set RCC_APB2ENR [expr $RCC_BASE + 0x18] -set RCC_APB1ENR [expr $RCC_BASE + 0x1c] -set RCC_BDCR [expr $RCC_BASE + 0x20] -set RCC_CSR [expr $RCC_BASE + 0x24] +set RCC_CR [expr {$RCC_BASE + 0x00}] +set RCC_CFGR [expr {$RCC_BASE + 0x04}] +set RCC_CIR [expr {$RCC_BASE + 0x08}] +set RCC_APB2RSTR [expr {$RCC_BASE + 0x0c}] +set RCC_APB1RSTR [expr {$RCC_BASE + 0x10}] +set RCC_AHBENR [expr {$RCC_BASE + 0x14}] +set RCC_APB2ENR [expr {$RCC_BASE + 0x18}] +set RCC_APB1ENR [expr {$RCC_BASE + 0x1c}] +set RCC_BDCR [expr {$RCC_BASE + 0x20}] +set RCC_CSR [expr {$RCC_BASE + 0x24}] proc show_RCC_CR { } { diff --git a/tcl/chip/st/stm32/stm32_regs.tcl b/tcl/chip/st/stm32/stm32_regs.tcl index 0c1f6257ce..6ae2f63f6b 100644 --- a/tcl/chip/st/stm32/stm32_regs.tcl +++ b/tcl/chip/st/stm32/stm32_regs.tcl @@ -11,78 +11,78 @@ set FSMC_R_BASE 0xA0000000 # /*Peripheral memory map */ set APB1PERIPH_BASE [set PERIPH_BASE] -set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000] -set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000] +set APB2PERIPH_BASE [expr {$PERIPH_BASE + 0x10000}] +set AHBPERIPH_BASE [expr {$PERIPH_BASE + 0x20000}] -set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000] -set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400] -set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800] -set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00] -set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000] -set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400] -set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800] -set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00] -set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000] -set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800] -set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00] -set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400] -set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800] -set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00] -set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000] -set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400] -set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800] -set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400] -set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00] -set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000] -set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400] +set TIM2_BASE [expr {$APB1PERIPH_BASE + 0x0000}] +set TIM3_BASE [expr {$APB1PERIPH_BASE + 0x0400}] +set TIM4_BASE [expr {$APB1PERIPH_BASE + 0x0800}] +set TIM5_BASE [expr {$APB1PERIPH_BASE + 0x0C00}] +set TIM6_BASE [expr {$APB1PERIPH_BASE + 0x1000}] +set TIM7_BASE [expr {$APB1PERIPH_BASE + 0x1400}] +set RTC_BASE [expr {$APB1PERIPH_BASE + 0x2800}] +set WWDG_BASE [expr {$APB1PERIPH_BASE + 0x2C00}] +set IWDG_BASE [expr {$APB1PERIPH_BASE + 0x3000}] +set SPI2_BASE [expr {$APB1PERIPH_BASE + 0x3800}] +set SPI3_BASE [expr {$APB1PERIPH_BASE + 0x3C00}] +set USART2_BASE [expr {$APB1PERIPH_BASE + 0x4400}] +set USART3_BASE [expr {$APB1PERIPH_BASE + 0x4800}] +set UART4_BASE [expr {$APB1PERIPH_BASE + 0x4C00}] +set UART5_BASE [expr {$APB1PERIPH_BASE + 0x5000}] +set I2C1_BASE [expr {$APB1PERIPH_BASE + 0x5400}] +set I2C2_BASE [expr {$APB1PERIPH_BASE + 0x5800}] +set CAN_BASE [expr {$APB1PERIPH_BASE + 0x6400}] +set BKP_BASE [expr {$APB1PERIPH_BASE + 0x6C00}] +set PWR_BASE [expr {$APB1PERIPH_BASE + 0x7000}] +set DAC_BASE [expr {$APB1PERIPH_BASE + 0x7400}] -set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000] -set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400] -set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800] -set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00] -set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000] -set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400] -set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800] -set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00] -set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000] -set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400] -set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800] -set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00] -set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000] -set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400] -set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800] -set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00] +set AFIO_BASE [expr {$APB2PERIPH_BASE + 0x0000}] +set EXTI_BASE [expr {$APB2PERIPH_BASE + 0x0400}] +set GPIOA_BASE [expr {$APB2PERIPH_BASE + 0x0800}] +set GPIOB_BASE [expr {$APB2PERIPH_BASE + 0x0C00}] +set GPIOC_BASE [expr {$APB2PERIPH_BASE + 0x1000}] +set GPIOD_BASE [expr {$APB2PERIPH_BASE + 0x1400}] +set GPIOE_BASE [expr {$APB2PERIPH_BASE + 0x1800}] +set GPIOF_BASE [expr {$APB2PERIPH_BASE + 0x1C00}] +set GPIOG_BASE [expr {$APB2PERIPH_BASE + 0x2000}] +set ADC1_BASE [expr {$APB2PERIPH_BASE + 0x2400}] +set ADC2_BASE [expr {$APB2PERIPH_BASE + 0x2800}] +set TIM1_BASE [expr {$APB2PERIPH_BASE + 0x2C00}] +set SPI1_BASE [expr {$APB2PERIPH_BASE + 0x3000}] +set TIM8_BASE [expr {$APB2PERIPH_BASE + 0x3400}] +set USART1_BASE [expr {$APB2PERIPH_BASE + 0x3800}] +set ADC3_BASE [expr {$APB2PERIPH_BASE + 0x3C00}] -set SDIO_BASE [expr $PERIPH_BASE + 0x18000] +set SDIO_BASE [expr {$PERIPH_BASE + 0x18000}] -set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000] -set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008] -set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C] -set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030] -set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044] -set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058] -set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C] -set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080] -set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400] -set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408] -set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C] -set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430] -set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444] -set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458] -set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000] -set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000] +set DMA1_BASE [expr {$AHBPERIPH_BASE + 0x0000}] +set DMA1_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0008}] +set DMA1_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x001C}] +set DMA1_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0030}] +set DMA1_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0044}] +set DMA1_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0058}] +set DMA1_Channel6_BASE [expr {$AHBPERIPH_BASE + 0x006C}] +set DMA1_Channel7_BASE [expr {$AHBPERIPH_BASE + 0x0080}] +set DMA2_BASE [expr {$AHBPERIPH_BASE + 0x0400}] +set DMA2_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0408}] +set DMA2_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x041C}] +set DMA2_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0430}] +set DMA2_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0444}] +set DMA2_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0458}] +set RCC_BASE [expr {$AHBPERIPH_BASE + 0x1000}] +set CRC_BASE [expr {$AHBPERIPH_BASE + 0x3000}] # /*Flash registers base address */ -set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000] +set FLASH_R_BASE [expr {$AHBPERIPH_BASE + 0x2000}] # /*Flash Option Bytes base address */ set OB_BASE 0x1FFFF800 # /*FSMC Bankx registers base address */ -set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000] -set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104] -set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060] -set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080] -set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0] +set FSMC_Bank1_R_BASE [expr {$FSMC_R_BASE + 0x0000}] +set FSMC_Bank1E_R_BASE [expr {$FSMC_R_BASE + 0x0104}] +set FSMC_Bank2_R_BASE [expr {$FSMC_R_BASE + 0x0060}] +set FSMC_Bank3_R_BASE [expr {$FSMC_R_BASE + 0x0080}] +set FSMC_Bank4_R_BASE [expr {$FSMC_R_BASE + 0x00A0}] # /*Debug MCU registers base address */ set DBGMCU_BASE 0xE0042000 @@ -90,6 +90,6 @@ set DBGMCU_BASE 0xE0042000 # /*System Control Space memory map */ set SCS_BASE 0xE000E000 -set SysTick_BASE [expr $SCS_BASE + 0x0010] -set NVIC_BASE [expr $SCS_BASE + 0x0100] -set SCB_BASE [expr $SCS_BASE + 0x0D00] +set SysTick_BASE [expr {$SCS_BASE + 0x0010}] +set NVIC_BASE [expr {$SCS_BASE + 0x0100}] +set SCB_BASE [expr {$SCS_BASE + 0x0D00}] diff --git a/tcl/cpu/arc/em.tcl b/tcl/cpu/arc/em.tcl index f0455bb742..595a351308 100644 --- a/tcl/cpu/arc/em.tcl +++ b/tcl/cpu/arc/em.tcl @@ -27,6 +27,6 @@ proc arc_em_reset { {target ""} } { # This is specific to ARC EM. set debug [arc jtag get-aux-reg 5] if { !($debug & (1 << 20)) } { - arc jtag set-aux-reg 5 [expr $debug | (1 << 20)] + arc jtag set-aux-reg 5 [expr {$debug | (1 << 20)}] } } diff --git a/tcl/cpu/arc/hs.tcl b/tcl/cpu/arc/hs.tcl index f39f2a7d00..181f993bf0 100644 --- a/tcl/cpu/arc/hs.tcl +++ b/tcl/cpu/arc/hs.tcl @@ -48,7 +48,7 @@ proc arc_hs_reset { {target ""} } { $target arc jtag set-aux-reg 0x904 1 set l2_ctrl [$target arc jtag get-aux-reg 0x903] set l2_ctrl [$target arc jtag get-aux-reg 0x903] - while { [expr $l2_ctrl & 0x100] != 0 } { + while { [expr {$l2_ctrl & 0x100}] != 0 } { set l2_ctrl [$target arc jtag get-aux-reg 0x903] } } diff --git a/tcl/cpu/arc/v2.tcl b/tcl/cpu/arc/v2.tcl index a3172c220a..364e8af37e 100644 --- a/tcl/cpu/arc/v2.tcl +++ b/tcl/cpu/arc/v2.tcl @@ -41,7 +41,7 @@ proc arc_v2_examine_target { {target ""} } { # 0b01 - 4 actionpoints # 0b10 - 8 actionpoints # 0b11 - reserved. - set ap_num [expr 0x2 << ($ap_build_type & 3)] + set ap_num [expr {0x2 << ($ap_build_type & 3)}] # Expression on top may produce 16 action points - which is a # reserved value for now. if { $ap_num < 16 } { @@ -341,6 +341,6 @@ proc arc_v2_reset { {target ""} } { # to write directly via JTAG layer... set num_ap [arc num-actionpoints] for {set i 0} {$i < $num_ap} {incr i} { - arc jtag set-aux-reg [expr 0x222 + $i * 3] 0 + arc jtag set-aux-reg [expr {0x222 + $i * 3}] 0 } } diff --git a/tcl/fpga/xilinx-dna.cfg b/tcl/fpga/xilinx-dna.cfg index a1d5ba3761..a8056735b1 100644 --- a/tcl/fpga/xilinx-dna.cfg +++ b/tcl/fpga/xilinx-dna.cfg @@ -30,7 +30,7 @@ proc xilinx_get_dna {tap chip} { # Print out the "Device DNA" in the same format that impact uses. proc xilinx_print_dna {dna} { - set dna [expr $dna >> 64 - 57] + set dna [expr {$dna >> 64 - 57}] echo [format "DNA = %057b (0x%016x)" $dna $dna] } diff --git a/tcl/fpga/xilinx-xadc.cfg b/tcl/fpga/xilinx-xadc.cfg index d4be4f5414..043e553939 100644 --- a/tcl/fpga/xilinx-xadc.cfg +++ b/tcl/fpga/xilinx-xadc.cfg @@ -118,17 +118,17 @@ proc xadc_read {tap addr} { # convert 16 bit register code from ADC measurement on # external voltages (VAUX) to Volt proc xadc_volt {code} { - return [expr $code * 1./(1 << 16)] + return [expr {$code * 1./(1 << 16)}] } # convert 16 bit temperature measurement to Celsius proc xadc_temp {code} { - return [expr $code * 503.975/(1 << 16) - 273.15] + return [expr {$code * 503.975/(1 << 16) - 273.15}] } # convert 16 bit suppply voltage measurement to Volt proc xadc_sup {code} { - return [expr $code * 3./(1 << 16)] + return [expr {$code * 3./(1 << 16)}] } # perform a single channel measurement using default settings diff --git a/tcl/mem_helper.tcl b/tcl/mem_helper.tcl index 5955793e25..9ea285a22c 100644 --- a/tcl/mem_helper.tcl +++ b/tcl/mem_helper.tcl @@ -34,7 +34,7 @@ add_help_text mrb "Returns value of byte in memory." # $reg <== ((value & ~$clearbits) | $setbits) proc mmw {reg setbits clearbits} { set old [mrw $reg] - set new [expr ($old & ~$clearbits) | $setbits] + set new [expr {($old & ~$clearbits) | $setbits}] mww $reg $new } diff --git a/tcl/memory.tcl b/tcl/memory.tcl index 3066c11139..c1e012d8d3 100644 --- a/tcl/memory.tcl +++ b/tcl/memory.tcl @@ -43,9 +43,9 @@ set RWX_NO_ACCESS 0 set RWX_X_ONLY $BIT0 set RWX_W_ONLY $BIT1 set RWX_R_ONLY $BIT2 -set RWX_RW [expr $RWX_R_ONLY + $RWX_W_ONLY] -set RWX_R_X [expr $RWX_R_ONLY + $RWX_X_ONLY] -set RWX_RWX [expr $RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY] +set RWX_RW [expr {$RWX_R_ONLY + $RWX_W_ONLY}] +set RWX_R_X [expr {$RWX_R_ONLY + $RWX_X_ONLY}] +set RWX_RWX [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}] set UNKNOWN(0,RWX) $RWX_NO_ACCESS # WIDTH - access width @@ -54,7 +54,7 @@ set ACCESS_WIDTH_NONE 0 set ACCESS_WIDTH_8 $BIT0 set ACCESS_WIDTH_16 $BIT1 set ACCESS_WIDTH_32 $BIT2 -set ACCESS_WIDTH_ANY [expr $ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32] +set ACCESS_WIDTH_ANY [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}] set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE proc iswithin { ADDRESS BASE LEN } { diff --git a/tcl/mmr_helpers.tcl b/tcl/mmr_helpers.tcl index e6b1c67042..6b2c1476ea 100644 --- a/tcl/mmr_helpers.tcl +++ b/tcl/mmr_helpers.tcl @@ -45,14 +45,14 @@ proc show_mmr32_bits { NAMES VAL } { for { set x 24 } { $x >= 0 } { incr x -8 } { echo -n " " for { set y 7 } { $y >= 0 } { incr y -1 } { - set s $MYNAMES([expr $x + $y]) - echo -n [format "%2d: %-*s | " [expr $x + $y] $w $s ] + set s $MYNAMES([expr {$x + $y}]) + echo -n [format "%2d: %-*s | " [expr {$x + $y}] $w $s ] } echo "" echo -n " " for { set y 7 } { $y >= 0 } { incr y -1 } { - echo -n [format " %d%*s | " [expr !!($VAL & (1 << ($x + $y)))] [expr $w -1] ""] + echo -n [format " %d%*s | " [expr !!($VAL & (1 << ($x + $y)))] [expr {$w -1}] ""] } echo "" } @@ -60,7 +60,7 @@ proc show_mmr32_bits { NAMES VAL } { proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } { - set width [expr (($MSB - $LSB + 1) + 7) / 4] + set width [expr {(($MSB - $LSB + 1) + 7) / 4}] set nval [show_normalize_bitfield $VAL $MSB $LSB ] set name0 [lindex $FIELDVALUES 0 ] if [ string compare $name0 _NUMBER_ ] { diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg index 02d8c7e82e..efc773d42d 100644 --- a/tcl/target/am335x.cfg +++ b/tcl/target/am335x.cfg @@ -85,8 +85,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000 # FIXME: unify with target/am437x.cfg source [find mem_helper.tcl] set WDT1_BASE_ADDR 0x44e35000 -set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034] -set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048] +set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}] +set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}] proc disable_watchdog { } { global WDT1_WSPR global WDT1_W_PEND_WSPR diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg index 8ce0941df0..e0813ca521 100644 --- a/tcl/target/am437x.cfg +++ b/tcl/target/am437x.cfg @@ -5,432 +5,432 @@ source [find mem_helper.tcl] ## AM437x Registers ## ############################################################################### set PRCM_BASE_ADDR 0x44df0000 -set REVISION_PRM [expr $PRCM_BASE_ADDR + 0x0000] -set PRM_IRQSTATUS_MPU [expr $PRCM_BASE_ADDR + 0x0004] -set PRM_IRQENABLE_MPU [expr $PRCM_BASE_ADDR + 0x0008] -set PRM_IRQSTATUS_M3 [expr $PRCM_BASE_ADDR + 0x000c] -set PRM_IRQENABLE_M3 [expr $PRCM_BASE_ADDR + 0x0010] -set PM_MPU_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0300] -set PM_MPU_PWRSTST [expr $PRCM_BASE_ADDR + 0x0304] -set RM_MPU_RSTST [expr $PRCM_BASE_ADDR + 0x0314] -set RM_MPU_CONTEXT [expr $PRCM_BASE_ADDR + 0x0324] -set PM_GFX_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0400] -set PM_GFX_PWRSTST [expr $PRCM_BASE_ADDR + 0x0404] -set RM_GFX_RSTCTRL [expr $PRCM_BASE_ADDR + 0x0410] -set RM_GFX_RSTST [expr $PRCM_BASE_ADDR + 0x0414] -set RM_GFX_CONTEXT [expr $PRCM_BASE_ADDR + 0x0424] -set RM_RTC_CONTEXT [expr $PRCM_BASE_ADDR + 0x0524] -set RM_WKUP_RSTCTRL [expr $PRCM_BASE_ADDR + 0x2010] -set RM_WKUP_RSTST [expr $PRCM_BASE_ADDR + 0x2014] -set CM_L3_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2800] -set CM_WKUP_DEBUGSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2820] -set CM_L3S_TSC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2900] -set CM_WKUP_ADC_TSC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2920] -set CM_L4_WKUP_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2a00] -set CM_WKUP_L4WKUP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a20] -set CM_WKUP_WKUP_M3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a28] -set CM_WKUP_SYNCTIMER_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a30] -set CM_WKUP_CLKDIV32K_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a38] -set CM_WKUP_USBPHY0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a40] -set CM_WKUP_USBPHY1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a48] -set CM_WKUP_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2b00] -set CM_WKUP_TIMER0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b20] -set CM_WKUP_TIMER1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b28] -set CM_WKUP_WDT0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b30] -set CM_WKUP_WDT1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b38] -set CM_WKUP_I2C0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b40] -set CM_WKUP_UART0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b48] -set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b50] -set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b58] -set CM_WKUP_CONTROL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b60] -set CM_WKUP_GPIO0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b68] -set CM_CLKMODE_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d20] -set CM_IDLEST_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d24] -set CM_CLKSEL_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d2c] -set CM_DIV_M4_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d38] -set CM_DIV_M5_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d3c] -set CM_DIV_M6_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d40] -set CM_SSC_DELTAMSTEP_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d48] -set CM_SSC_MODFREQDIV_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d4c] -set CM_CLKMODE_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d60] -set CM_IDLEST_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d64] -set CM_CLKSEL_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d6c] -set CM_DIV_M2_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d70] -set CM_SSC_DELTAMSTEP_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d88] -set CM_SSC_MODFREQDIV_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d8c] -set CM_CLKMODE_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da0] -set CM_IDLEST_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da4] -set CM_CLKSEL_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dac] -set CM_DIV_M2_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db0] -set CM_DIV_M4_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db8] -set CM_SSC_DELTAMSTEP_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dc8] -set CM_SSC_MODFREQDIV_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dcc] -set CM_CLKMODE_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de0] -set CM_IDLEST_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de4] -set CM_CLKSEL_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2dec] -set CM_DIV_M2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2df0] -set CM_CLKSEL2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e04] -set CM_SSC_DELTAMSTEP_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e08] -set CM_SSC_MODFREQDIV_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e0c] -set CM_CLKDCOLDO_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e14] -set CM_CLKMODE_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e20] -set CM_IDLEST_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e24] -set CM_CLKSEL_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e2c] -set CM_DIV_M2_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e30] -set CM_SSC_DELTAMSTEP_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e48] -set CM_SSC_MODFREQDIV_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e4c] -set CM_CLKMODE_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e60] -set CM_IDLEST_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e64] -set CM_CLKSEL_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e6c] -set CM_DIV_M2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e70] -set CM_CLKSEL2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e84] -set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e88] -set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e8c] -set CM_SHADOW_FREQ_CONFIG1 [expr $PRCM_BASE_ADDR + 0x2fa0] -set CM_SHADOW_FREQ_CONFIG2 [expr $PRCM_BASE_ADDR + 0x2fa4] -set CM_CLKOUT1_CTRL [expr $PRCM_BASE_ADDR + 0x4100] -set CM_DLL_CTRL [expr $PRCM_BASE_ADDR + 0x4104] -set CM_CLKOUT2_CTRL [expr $PRCM_BASE_ADDR + 0x4108] -set CLKSEL_TIMER1MS_CLK [expr $PRCM_BASE_ADDR + 0x4200] -set CLKSEL_TIMER2_CLK [expr $PRCM_BASE_ADDR + 0x4204] -set CLKSEL_TIMER3_CLK [expr $PRCM_BASE_ADDR + 0x4208] -set CLKSEL_TIMER4_CLK [expr $PRCM_BASE_ADDR + 0x420c] -set CLKSEL_TIMER5_CLK [expr $PRCM_BASE_ADDR + 0x4210] -set CLKSEL_TIMER6_CLK [expr $PRCM_BASE_ADDR + 0x4214] -set CLKSEL_TIMER7_CLK [expr $PRCM_BASE_ADDR + 0x4218] -set CLKSEL_TIMER8_CLK [expr $PRCM_BASE_ADDR + 0x421c] -set CLKSEL_TIMER9_CLK [expr $PRCM_BASE_ADDR + 0x4220] -set CLKSEL_TIMER10_CLK [expr $PRCM_BASE_ADDR + 0x4224] -set CLKSEL_TIMER11_CLK [expr $PRCM_BASE_ADDR + 0x4228] -set CLKSEL_WDT1_CLK [expr $PRCM_BASE_ADDR + 0x422c] -set CLKSEL_SYNCTIMER_CLK [expr $PRCM_BASE_ADDR + 0x4230] -set CLKSEL_MAC_CLK [expr $PRCM_BASE_ADDR + 0x4234] -set CLKSEL_CPTS_RFT_CLK [expr $PRCM_BASE_ADDR + 0x4238] -set CLKSEL_GFX_FCLK [expr $PRCM_BASE_ADDR + 0x423c] -set CLKSEL_GPIO0_DBCLK [expr $PRCM_BASE_ADDR + 0x4240] -set CLKSEL_LCDC_PIXEL_CLK [expr $PRCM_BASE_ADDR + 0x4244] -set CLKSEL_ICSS_OCP_CLK [expr $PRCM_BASE_ADDR + 0x4248] -set CLKSEL_DLL_AGING_CLK [expr $PRCM_BASE_ADDR + 0x4250] -set CLKSEL_USBPHY32KHZ_GCLK [expr $PRCM_BASE_ADDR + 0x4260] -set CM_MPU_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8300] -set CM_MPU_MPU_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8320] -set CM_GFX_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8400] -set CM_GFX_GFX_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8420] -set CM_RTC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8500] -set CM_RTC_RTC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8520] -set CM_PER_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8800] -set CM_PER_L3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8820] -set CM_PER_AES0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8828] -set CM_PER_DES_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8830] -set CM_PER_CRYPTODMA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8838] -set CM_PER_L3_INSTR_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8840] -set CM_PER_MSTR_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8848] -set CM_PER_OCMCRAM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8850] -set CM_PER_SHA0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8858] -set CM_PER_SLV_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8860] -set CM_PER_VPFE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8868] -set CM_PER_VPFE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8870] -set CM_PER_TPCC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8878] -set CM_PER_TPTC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8880] -set CM_PER_TPTC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8888] -set CM_PER_TPTC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8890] -set CM_PER_DLL_AGING_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8898] -set CM_PER_L4HS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a0] -set CM_PER_L4FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a8] -set CM_PER_L3S_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8a00] -set CM_PER_GPMC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a20] -set CM_PER_IEEE5000_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a28] -set CM_PER_MCASP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a38] -set CM_PER_MCASP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a40] -set CM_PER_MMC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a48] -set CM_PER_QSPI_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a58] -set CM_PER_USB_OTG_SS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a60] -set CM_PER_USB_OTG_SS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a68] -set CM_PER_ICSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8b00] -set CM_PER_ICSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8b20] -set CM_PER_L4LS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8c00] -set CM_PER_L4LS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c20] -set CM_PER_DCAN0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c28] -set CM_PER_DCAN1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c30] -set CM_PER_EPWMSS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c38] -set CM_PER_EPWMSS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c40] -set CM_PER_EPWMSS2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c48] -set CM_PER_EPWMSS3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c50] -set CM_PER_EPWMSS4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c58] -set CM_PER_EPWMSS5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c60] -set CM_PER_ELM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c68] -set CM_PER_GPIO1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c78] -set CM_PER_GPIO2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c80] -set CM_PER_GPIO3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c88] -set CM_PER_GPIO4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c90] -set CM_PER_GPIO5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c98] -set CM_PER_HDQ1W_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca0] -set CM_PER_I2C1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca8] -set CM_PER_I2C2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb0] -set CM_PER_MAILBOX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb8] -set CM_PER_MMC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc0] -set CM_PER_MMC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc8] -set CM_PER_PKA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cd0] -set CM_PER_RNG_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce0] -set CM_PER_SPARE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce8] -set CM_PER_SPARE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cf0] -set CM_PER_SPI0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d00] -set CM_PER_SPI1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d08] -set CM_PER_SPI2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d10] -set CM_PER_SPI3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d18] -set CM_PER_SPI4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d20] -set CM_PER_SPINLOCK_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d28] -set CM_PER_TIMER2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d30] -set CM_PER_TIMER3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d38] -set CM_PER_TIMER4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d40] -set CM_PER_TIMER5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d48] -set CM_PER_TIMER6_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d50] -set CM_PER_TIMER7_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d58] -set CM_PER_TIMER8_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d60] -set CM_PER_TIMER9_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d68] -set CM_PER_TIMER10_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d70] -set CM_PER_TIMER11_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d78] -set CM_PER_UART1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d80] -set CM_PER_UART2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d88] -set CM_PER_UART3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d90] -set CM_PER_UART4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d98] -set CM_PER_UART5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8da0] -set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8db8] -set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8dc0] -set CM_PER_EMIF_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8f00] -set CM_PER_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f20] -set CM_PER_DLL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f28] -set CM_PER_EMIF_FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f30] -set CM_PER_OTFA_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f38] -set CM_PER_DSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9200] -set CM_PER_DSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9220] -set CM_PER_CPSW_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9300] -set CM_PER_CPGMAC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9320] -set CM_PER_OCPWP_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9400] -set CM_PER_OCPWP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9420] +set REVISION_PRM [expr {$PRCM_BASE_ADDR + 0x0000}] +set PRM_IRQSTATUS_MPU [expr {$PRCM_BASE_ADDR + 0x0004}] +set PRM_IRQENABLE_MPU [expr {$PRCM_BASE_ADDR + 0x0008}] +set PRM_IRQSTATUS_M3 [expr {$PRCM_BASE_ADDR + 0x000c}] +set PRM_IRQENABLE_M3 [expr {$PRCM_BASE_ADDR + 0x0010}] +set PM_MPU_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0300}] +set PM_MPU_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0304}] +set RM_MPU_RSTST [expr {$PRCM_BASE_ADDR + 0x0314}] +set RM_MPU_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0324}] +set PM_GFX_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0400}] +set PM_GFX_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0404}] +set RM_GFX_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x0410}] +set RM_GFX_RSTST [expr {$PRCM_BASE_ADDR + 0x0414}] +set RM_GFX_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0424}] +set RM_RTC_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0524}] +set RM_WKUP_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x2010}] +set RM_WKUP_RSTST [expr {$PRCM_BASE_ADDR + 0x2014}] +set CM_L3_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2800}] +set CM_WKUP_DEBUGSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2820}] +set CM_L3S_TSC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2900}] +set CM_WKUP_ADC_TSC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2920}] +set CM_L4_WKUP_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2a00}] +set CM_WKUP_L4WKUP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a20}] +set CM_WKUP_WKUP_M3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a28}] +set CM_WKUP_SYNCTIMER_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a30}] +set CM_WKUP_CLKDIV32K_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a38}] +set CM_WKUP_USBPHY0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a40}] +set CM_WKUP_USBPHY1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a48}] +set CM_WKUP_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2b00}] +set CM_WKUP_TIMER0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b20}] +set CM_WKUP_TIMER1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b28}] +set CM_WKUP_WDT0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b30}] +set CM_WKUP_WDT1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b38}] +set CM_WKUP_I2C0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b40}] +set CM_WKUP_UART0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b48}] +set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b50}] +set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b58}] +set CM_WKUP_CONTROL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b60}] +set CM_WKUP_GPIO0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b68}] +set CM_CLKMODE_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d20}] +set CM_IDLEST_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d24}] +set CM_CLKSEL_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d2c}] +set CM_DIV_M4_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d38}] +set CM_DIV_M5_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d3c}] +set CM_DIV_M6_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d40}] +set CM_SSC_DELTAMSTEP_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d48}] +set CM_SSC_MODFREQDIV_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d4c}] +set CM_CLKMODE_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d60}] +set CM_IDLEST_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d64}] +set CM_CLKSEL_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d6c}] +set CM_DIV_M2_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d70}] +set CM_SSC_DELTAMSTEP_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d88}] +set CM_SSC_MODFREQDIV_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d8c}] +set CM_CLKMODE_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da0}] +set CM_IDLEST_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da4}] +set CM_CLKSEL_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dac}] +set CM_DIV_M2_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db0}] +set CM_DIV_M4_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db8}] +set CM_SSC_DELTAMSTEP_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dc8}] +set CM_SSC_MODFREQDIV_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dcc}] +set CM_CLKMODE_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de0}] +set CM_IDLEST_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de4}] +set CM_CLKSEL_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2dec}] +set CM_DIV_M2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2df0}] +set CM_CLKSEL2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e04}] +set CM_SSC_DELTAMSTEP_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e08}] +set CM_SSC_MODFREQDIV_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e0c}] +set CM_CLKDCOLDO_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e14}] +set CM_CLKMODE_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e20}] +set CM_IDLEST_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e24}] +set CM_CLKSEL_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e2c}] +set CM_DIV_M2_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e30}] +set CM_SSC_DELTAMSTEP_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e48}] +set CM_SSC_MODFREQDIV_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e4c}] +set CM_CLKMODE_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e60}] +set CM_IDLEST_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e64}] +set CM_CLKSEL_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e6c}] +set CM_DIV_M2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e70}] +set CM_CLKSEL2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e84}] +set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e88}] +set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e8c}] +set CM_SHADOW_FREQ_CONFIG1 [expr {$PRCM_BASE_ADDR + 0x2fa0}] +set CM_SHADOW_FREQ_CONFIG2 [expr {$PRCM_BASE_ADDR + 0x2fa4}] +set CM_CLKOUT1_CTRL [expr {$PRCM_BASE_ADDR + 0x4100}] +set CM_DLL_CTRL [expr {$PRCM_BASE_ADDR + 0x4104}] +set CM_CLKOUT2_CTRL [expr {$PRCM_BASE_ADDR + 0x4108}] +set CLKSEL_TIMER1MS_CLK [expr {$PRCM_BASE_ADDR + 0x4200}] +set CLKSEL_TIMER2_CLK [expr {$PRCM_BASE_ADDR + 0x4204}] +set CLKSEL_TIMER3_CLK [expr {$PRCM_BASE_ADDR + 0x4208}] +set CLKSEL_TIMER4_CLK [expr {$PRCM_BASE_ADDR + 0x420c}] +set CLKSEL_TIMER5_CLK [expr {$PRCM_BASE_ADDR + 0x4210}] +set CLKSEL_TIMER6_CLK [expr {$PRCM_BASE_ADDR + 0x4214}] +set CLKSEL_TIMER7_CLK [expr {$PRCM_BASE_ADDR + 0x4218}] +set CLKSEL_TIMER8_CLK [expr {$PRCM_BASE_ADDR + 0x421c}] +set CLKSEL_TIMER9_CLK [expr {$PRCM_BASE_ADDR + 0x4220}] +set CLKSEL_TIMER10_CLK [expr {$PRCM_BASE_ADDR + 0x4224}] +set CLKSEL_TIMER11_CLK [expr {$PRCM_BASE_ADDR + 0x4228}] +set CLKSEL_WDT1_CLK [expr {$PRCM_BASE_ADDR + 0x422c}] +set CLKSEL_SYNCTIMER_CLK [expr {$PRCM_BASE_ADDR + 0x4230}] +set CLKSEL_MAC_CLK [expr {$PRCM_BASE_ADDR + 0x4234}] +set CLKSEL_CPTS_RFT_CLK [expr {$PRCM_BASE_ADDR + 0x4238}] +set CLKSEL_GFX_FCLK [expr {$PRCM_BASE_ADDR + 0x423c}] +set CLKSEL_GPIO0_DBCLK [expr {$PRCM_BASE_ADDR + 0x4240}] +set CLKSEL_LCDC_PIXEL_CLK [expr {$PRCM_BASE_ADDR + 0x4244}] +set CLKSEL_ICSS_OCP_CLK [expr {$PRCM_BASE_ADDR + 0x4248}] +set CLKSEL_DLL_AGING_CLK [expr {$PRCM_BASE_ADDR + 0x4250}] +set CLKSEL_USBPHY32KHZ_GCLK [expr {$PRCM_BASE_ADDR + 0x4260}] +set CM_MPU_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8300}] +set CM_MPU_MPU_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8320}] +set CM_GFX_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8400}] +set CM_GFX_GFX_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8420}] +set CM_RTC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8500}] +set CM_RTC_RTC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8520}] +set CM_PER_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8800}] +set CM_PER_L3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8820}] +set CM_PER_AES0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8828}] +set CM_PER_DES_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8830}] +set CM_PER_CRYPTODMA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8838}] +set CM_PER_L3_INSTR_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8840}] +set CM_PER_MSTR_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8848}] +set CM_PER_OCMCRAM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8850}] +set CM_PER_SHA0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8858}] +set CM_PER_SLV_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8860}] +set CM_PER_VPFE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8868}] +set CM_PER_VPFE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8870}] +set CM_PER_TPCC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8878}] +set CM_PER_TPTC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8880}] +set CM_PER_TPTC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8888}] +set CM_PER_TPTC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8890}] +set CM_PER_DLL_AGING_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8898}] +set CM_PER_L4HS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a0}] +set CM_PER_L4FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a8}] +set CM_PER_L3S_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8a00}] +set CM_PER_GPMC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a20}] +set CM_PER_IEEE5000_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a28}] +set CM_PER_MCASP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a38}] +set CM_PER_MCASP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a40}] +set CM_PER_MMC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a48}] +set CM_PER_QSPI_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a58}] +set CM_PER_USB_OTG_SS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a60}] +set CM_PER_USB_OTG_SS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a68}] +set CM_PER_ICSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8b00}] +set CM_PER_ICSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8b20}] +set CM_PER_L4LS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8c00}] +set CM_PER_L4LS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c20}] +set CM_PER_DCAN0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c28}] +set CM_PER_DCAN1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c30}] +set CM_PER_EPWMSS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c38}] +set CM_PER_EPWMSS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c40}] +set CM_PER_EPWMSS2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c48}] +set CM_PER_EPWMSS3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c50}] +set CM_PER_EPWMSS4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c58}] +set CM_PER_EPWMSS5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c60}] +set CM_PER_ELM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c68}] +set CM_PER_GPIO1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c78}] +set CM_PER_GPIO2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c80}] +set CM_PER_GPIO3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c88}] +set CM_PER_GPIO4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c90}] +set CM_PER_GPIO5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c98}] +set CM_PER_HDQ1W_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca0}] +set CM_PER_I2C1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca8}] +set CM_PER_I2C2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb0}] +set CM_PER_MAILBOX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb8}] +set CM_PER_MMC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc0}] +set CM_PER_MMC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc8}] +set CM_PER_PKA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cd0}] +set CM_PER_RNG_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce0}] +set CM_PER_SPARE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce8}] +set CM_PER_SPARE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cf0}] +set CM_PER_SPI0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d00}] +set CM_PER_SPI1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d08}] +set CM_PER_SPI2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d10}] +set CM_PER_SPI3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d18}] +set CM_PER_SPI4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d20}] +set CM_PER_SPINLOCK_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d28}] +set CM_PER_TIMER2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d30}] +set CM_PER_TIMER3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d38}] +set CM_PER_TIMER4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d40}] +set CM_PER_TIMER5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d48}] +set CM_PER_TIMER6_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d50}] +set CM_PER_TIMER7_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d58}] +set CM_PER_TIMER8_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d60}] +set CM_PER_TIMER9_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d68}] +set CM_PER_TIMER10_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d70}] +set CM_PER_TIMER11_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d78}] +set CM_PER_UART1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d80}] +set CM_PER_UART2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d88}] +set CM_PER_UART3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d90}] +set CM_PER_UART4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d98}] +set CM_PER_UART5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8da0}] +set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8db8}] +set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8dc0}] +set CM_PER_EMIF_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8f00}] +set CM_PER_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f20}] +set CM_PER_DLL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f28}] +set CM_PER_EMIF_FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f30}] +set CM_PER_OTFA_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f38}] +set CM_PER_DSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9200}] +set CM_PER_DSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9220}] +set CM_PER_CPSW_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9300}] +set CM_PER_CPGMAC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9320}] +set CM_PER_OCPWP_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9400}] +set CM_PER_OCPWP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9420}] set CONTROL_BASE_ADDR 0x44e10000 -set CONTROL_STATUS [expr $CONTROL_BASE_ADDR + 0x0040] -set DEVICE_ID [expr $CONTROL_BASE_ADDR + 0x0600] -set DEV_FEATURE [expr $CONTROL_BASE_ADDR + 0x0604] -set DEV_ATTRIBUTE [expr $CONTROL_BASE_ADDR + 0x0610] -set MAC_ID0_LO [expr $CONTROL_BASE_ADDR + 0x0630] -set MAC_ID0_HI [expr $CONTROL_BASE_ADDR + 0x0634] -set MAC_ID1_LO [expr $CONTROL_BASE_ADDR + 0x0638] -set MAC_ID1_HI [expr $CONTROL_BASE_ADDR + 0x063c] -set USB_VID_PID [expr $CONTROL_BASE_ADDR + 0x07f4] -set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr $CONTROL_BASE_ADDR + 0x0964] -set CONTROL_CONF_SPI4_CS0 [expr $CONTROL_BASE_ADDR + 0x0a5c] -set CONTROL_CONF_SPI2_SCLK [expr $CONTROL_BASE_ADDR + 0x0a60] -set CONTROL_CONF_SPI2_D0 [expr $CONTROL_BASE_ADDR + 0x0a64] -set CONTROL_CONF_XDMA_EVENT_INTR0 [expr $CONTROL_BASE_ADDR + 0x0a70] -set CONTROL_CONF_XDMA_EVENT_INTR1 [expr $CONTROL_BASE_ADDR + 0x0a74] -set CONTROL_CONF_GPMC_A0 [expr $CONTROL_BASE_ADDR + 0x0840] -set DDR_IO_CTRL [expr $CONTROL_BASE_ADDR + 0x0e04] -set VTP_CTRL_REG [expr $CONTROL_BASE_ADDR + 0x0e0c] -set VREF_CTRL [expr $CONTROL_BASE_ADDR + 0x0e14] -set DDR_CKE_CTRL [expr $CONTROL_BASE_ADDR + 0x131c] -set DDR_ADDRCTRL_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1404] -set DDR_ADDRCTRL_WD0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1408] -set DDR_ADDRCTRL_WD1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x140c] -set DDR_DATA0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1440] -set DDR_DATA1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1444] -set DDR_DATA2_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1448] -set DDR_DATA3_IOCTRL [expr $CONTROL_BASE_ADDR + 0x144c] -set EMIF_SDRAM_CONFIG_EXT [expr $CONTROL_BASE_ADDR + 0x1460] -set EMIF_SDRAM_STATUS_EXT [expr $CONTROL_BASE_ADDR + 0x1464] +set CONTROL_STATUS [expr {$CONTROL_BASE_ADDR + 0x0040}] +set DEVICE_ID [expr {$CONTROL_BASE_ADDR + 0x0600}] +set DEV_FEATURE [expr {$CONTROL_BASE_ADDR + 0x0604}] +set DEV_ATTRIBUTE [expr {$CONTROL_BASE_ADDR + 0x0610}] +set MAC_ID0_LO [expr {$CONTROL_BASE_ADDR + 0x0630}] +set MAC_ID0_HI [expr {$CONTROL_BASE_ADDR + 0x0634}] +set MAC_ID1_LO [expr {$CONTROL_BASE_ADDR + 0x0638}] +set MAC_ID1_HI [expr {$CONTROL_BASE_ADDR + 0x063c}] +set USB_VID_PID [expr {$CONTROL_BASE_ADDR + 0x07f4}] +set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr {$CONTROL_BASE_ADDR + 0x0964}] +set CONTROL_CONF_SPI4_CS0 [expr {$CONTROL_BASE_ADDR + 0x0a5c}] +set CONTROL_CONF_SPI2_SCLK [expr {$CONTROL_BASE_ADDR + 0x0a60}] +set CONTROL_CONF_SPI2_D0 [expr {$CONTROL_BASE_ADDR + 0x0a64}] +set CONTROL_CONF_XDMA_EVENT_INTR0 [expr {$CONTROL_BASE_ADDR + 0x0a70}] +set CONTROL_CONF_XDMA_EVENT_INTR1 [expr {$CONTROL_BASE_ADDR + 0x0a74}] +set CONTROL_CONF_GPMC_A0 [expr {$CONTROL_BASE_ADDR + 0x0840}] +set DDR_IO_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e04}] +set VTP_CTRL_REG [expr {$CONTROL_BASE_ADDR + 0x0e0c}] +set VREF_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e14}] +set DDR_CKE_CTRL [expr {$CONTROL_BASE_ADDR + 0x131c}] +set DDR_ADDRCTRL_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1404}] +set DDR_ADDRCTRL_WD0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1408}] +set DDR_ADDRCTRL_WD1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x140c}] +set DDR_DATA0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1440}] +set DDR_DATA1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1444}] +set DDR_DATA2_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1448}] +set DDR_DATA3_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x144c}] +set EMIF_SDRAM_CONFIG_EXT [expr {$CONTROL_BASE_ADDR + 0x1460}] +set EMIF_SDRAM_STATUS_EXT [expr {$CONTROL_BASE_ADDR + 0x1464}] set GPIO0_BASE_ADDR 0x44e07000 -set GPIO0_SYSCONFIG [expr $GPIO0_BASE_ADDR + 0x0010] -set GPIO0_SYSSTATUS [expr $GPIO0_BASE_ADDR + 0x0114] -set GPIO0_CTRL [expr $GPIO0_BASE_ADDR + 0x0130] -set GPIO0_OE [expr $GPIO0_BASE_ADDR + 0x0134] -set GPIO0_CLEARDATAOUT [expr $GPIO0_BASE_ADDR + 0x0190] -set GPIO0_SETDATAOUT [expr $GPIO0_BASE_ADDR + 0x0194] +set GPIO0_SYSCONFIG [expr {$GPIO0_BASE_ADDR + 0x0010}] +set GPIO0_SYSSTATUS [expr {$GPIO0_BASE_ADDR + 0x0114}] +set GPIO0_CTRL [expr {$GPIO0_BASE_ADDR + 0x0130}] +set GPIO0_OE [expr {$GPIO0_BASE_ADDR + 0x0134}] +set GPIO0_CLEARDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0190}] +set GPIO0_SETDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0194}] set GPIO5_BASE_ADDR 0x48322000 -set GPIO5_SYSCONFIG [expr $GPIO5_BASE_ADDR + 0x0010] -set GPIO5_SYSSTATUS [expr $GPIO5_BASE_ADDR + 0x0114] -set GPIO5_CTRL [expr $GPIO5_BASE_ADDR + 0x0130] -set GPIO5_OE [expr $GPIO5_BASE_ADDR + 0x0134] -set GPIO5_CLEARDATAOUT [expr $GPIO5_BASE_ADDR + 0x0190] -set GPIO5_SETDATAOUT [expr $GPIO5_BASE_ADDR + 0x0194] +set GPIO5_SYSCONFIG [expr {$GPIO5_BASE_ADDR + 0x0010}] +set GPIO5_SYSSTATUS [expr {$GPIO5_BASE_ADDR + 0x0114}] +set GPIO5_CTRL [expr {$GPIO5_BASE_ADDR + 0x0130}] +set GPIO5_OE [expr {$GPIO5_BASE_ADDR + 0x0134}] +set GPIO5_CLEARDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0190}] +set GPIO5_SETDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0194}] set GPIO1_BASE_ADDR 0x4804c000 -set GPIO1_SYSCONFIG [expr $GPIO1_BASE_ADDR + 0x0010] -set GPIO1_SYSSTATUS [expr $GPIO1_BASE_ADDR + 0x0114] -set GPIO1_CTRL [expr $GPIO1_BASE_ADDR + 0x0130] -set GPIO1_OE [expr $GPIO1_BASE_ADDR + 0x0134] -set GPIO1_CLEARDATAOUT [expr $GPIO1_BASE_ADDR + 0x0190] -set GPIO1_SETDATAOUT [expr $GPIO1_BASE_ADDR + 0x0194] +set GPIO1_SYSCONFIG [expr {$GPIO1_BASE_ADDR + 0x0010}] +set GPIO1_SYSSTATUS [expr {$GPIO1_BASE_ADDR + 0x0114}] +set GPIO1_CTRL [expr {$GPIO1_BASE_ADDR + 0x0130}] +set GPIO1_OE [expr {$GPIO1_BASE_ADDR + 0x0134}] +set GPIO1_CLEARDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0190}] +set GPIO1_SETDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0194}] set EMIF_BASE_ADDR 0x4c000000 -set EMIF_STATUS [expr $EMIF_BASE_ADDR + 0x0004] -set EMIF_SDRAM_CONFIG [expr $EMIF_BASE_ADDR + 0x0008] -set EMIF_SDRAM_CONFIG_2 [expr $EMIF_BASE_ADDR + 0x000c] -set EMIF_SDRAM_REF_CTRL [expr $EMIF_BASE_ADDR + 0x0010] -set EMIF_SDRAM_REF_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x0014] -set EMIF_SDRAM_TIM_1 [expr $EMIF_BASE_ADDR + 0x0018] -set EMIF_SDRAM_TIM_1_SHDW [expr $EMIF_BASE_ADDR + 0x001c] -set EMIF_SDRAM_TIM_2 [expr $EMIF_BASE_ADDR + 0x0020] -set EMIF_SDRAM_TIM_2_SHDW [expr $EMIF_BASE_ADDR + 0x0024] -set EMIF_SDRAM_TIM_3 [expr $EMIF_BASE_ADDR + 0x0028] -set EMIF_SDRAM_TIM_3_SHDW [expr $EMIF_BASE_ADDR + 0x002c] -set EMIF_LPDDR2_NVM_TIM [expr $EMIF_BASE_ADDR + 0x0030] -set EMIF_LPDDR2_NVM_TIM_SHDW [expr $EMIF_BASE_ADDR + 0x0034] -set EMIF_PWR_MGMT_CTRL [expr $EMIF_BASE_ADDR + 0x0038] -set EMIF_PWR_MGMT_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x003c] -set EMIF_LPDDR2_MODE_REG_DATA [expr $EMIF_BASE_ADDR + 0x0040] -set EMIF_LPDDR2_MODE_REG_CFG [expr $EMIF_BASE_ADDR + 0x0050] -set EMIF_OCP_CONFIG [expr $EMIF_BASE_ADDR + 0x0054] -set EMIF_OCP_CFG_VAL_1 [expr $EMIF_BASE_ADDR + 0x0058] -set EMIF_OCP_CFG_VAL_2 [expr $EMIF_BASE_ADDR + 0x005c] -set EMIF_IODFT_TLGC [expr $EMIF_BASE_ADDR + 0x0060] -set EMIF_IODFT_CTRL_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0064] -set EMIF_IODFT_ADDR_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0068] -set EMIF_IODFT_DATA_MISR_RSLT_1 [expr $EMIF_BASE_ADDR + 0x006c] -set EMIF_IODFT_DATA_MISR_RSLT_2 [expr $EMIF_BASE_ADDR + 0x0070] -set EMIF_IODFT_DATA_MISR_RSLT_3 [expr $EMIF_BASE_ADDR + 0x0074] -set EMIF_PERF_CNT_1 [expr $EMIF_BASE_ADDR + 0x0080] -set EMIF_PERF_CNT_2 [expr $EMIF_BASE_ADDR + 0x0084] -set EMIF_PERF_CNT_CFG [expr $EMIF_BASE_ADDR + 0x0088] -set EMIF_PERF_CNT_SEL [expr $EMIF_BASE_ADDR + 0x008c] -set EMIF_PERF_CNT_TIM [expr $EMIF_BASE_ADDR + 0x0090] -set EMIF_MISC_REG [expr $EMIF_BASE_ADDR + 0x0094] -set EMIF_DLL_CALIB_CTRL [expr $EMIF_BASE_ADDR + 0x0098] -set EMIF_DLL_CALIB_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x009c] -set EMIF_IRQ_EOI [expr $EMIF_BASE_ADDR + 0x00a0] -set EMIF_IRQSTATUS_RAW_SYS [expr $EMIF_BASE_ADDR + 0x00a4] -set EMIF_IRQSTATUS_SYS [expr $EMIF_BASE_ADDR + 0x00ac] -set EMIF_IRQENABLE_SET_SYS [expr $EMIF_BASE_ADDR + 0x00b4] -set EMIF_IRQENABLE_CLR_SYS [expr $EMIF_BASE_ADDR + 0x00bc] -set EMIF_ZQ_CONFIG [expr $EMIF_BASE_ADDR + 0x00c8] -set EMIF_TEMP_ALERT_CONFIG [expr $EMIF_BASE_ADDR + 0x00cc] -set EMIF_OCP_ERR_LOG [expr $EMIF_BASE_ADDR + 0x00d0] -set EMIF_RDWR_LVL_RMP_WIN [expr $EMIF_BASE_ADDR + 0x00d4] -set EMIF_RDWR_LVL_RMP_CTRL [expr $EMIF_BASE_ADDR + 0x00d8] -set EMIF_RDWR_LVL_CTRL [expr $EMIF_BASE_ADDR + 0x00dc] -set EMIF_DDR_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x00e4] -set EMIF_DDR_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x00e8] -set EMIF_DDR_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x00ec] -set EMIF_PRI_COS_MAP [expr $EMIF_BASE_ADDR + 0x0100] -set EMIF_CONNID_COS_1_MAP [expr $EMIF_BASE_ADDR + 0x0104] -set EMIF_CONNID_COS_2_MAP [expr $EMIF_BASE_ADDR + 0x0108] -set ECC_CTRL [expr $EMIF_BASE_ADDR + 0x0110] -set ECC_ADDR_RNG_1 [expr $EMIF_BASE_ADDR + 0x0114] -set ECC_ADDR_RNG_2 [expr $EMIF_BASE_ADDR + 0x0118] -set EMIF_RD_WR_EXEC_THRSH [expr $EMIF_BASE_ADDR + 0x0120] -set COS_CONFIG [expr $EMIF_BASE_ADDR + 0x0124] - -set PHY_STATUS_1 [expr $EMIF_BASE_ADDR + 0x0144] -set PHY_STATUS_2 [expr $EMIF_BASE_ADDR + 0x0148] -set PHY_STATUS_3 [expr $EMIF_BASE_ADDR + 0x014c] -set PHY_STATUS_4 [expr $EMIF_BASE_ADDR + 0x0150] -set PHY_STATUS_5 [expr $EMIF_BASE_ADDR + 0x0154] -set PHY_STATUS_6 [expr $EMIF_BASE_ADDR + 0x0158] -set PHY_STATUS_7 [expr $EMIF_BASE_ADDR + 0x015c] -set PHY_STATUS_8 [expr $EMIF_BASE_ADDR + 0x0160] -set PHY_STATUS_9 [expr $EMIF_BASE_ADDR + 0x0164] -set PHY_STATUS_10 [expr $EMIF_BASE_ADDR + 0x0168] -set PHY_STATUS_11 [expr $EMIF_BASE_ADDR + 0x016c] -set PHY_STATUS_12 [expr $EMIF_BASE_ADDR + 0x0170] -set PHY_STATUS_13 [expr $EMIF_BASE_ADDR + 0x0174] -set PHY_STATUS_14 [expr $EMIF_BASE_ADDR + 0x0178] -set PHY_STATUS_15 [expr $EMIF_BASE_ADDR + 0x017c] -set PHY_STATUS_16 [expr $EMIF_BASE_ADDR + 0x0180] -set PHY_STATUS_17 [expr $EMIF_BASE_ADDR + 0x0184] -set PHY_STATUS_18 [expr $EMIF_BASE_ADDR + 0x0188] -set PHY_STATUS_19 [expr $EMIF_BASE_ADDR + 0x018c] -set PHY_STATUS_20 [expr $EMIF_BASE_ADDR + 0x0190] -set PHY_STATUS_21 [expr $EMIF_BASE_ADDR + 0x0194] -set PHY_STATUS_22 [expr $EMIF_BASE_ADDR + 0x0198] -set PHY_STATUS_23 [expr $EMIF_BASE_ADDR + 0x019c] -set PHY_STATUS_24 [expr $EMIF_BASE_ADDR + 0x01a0] -set PHY_STATUS_25 [expr $EMIF_BASE_ADDR + 0x01a4] -set PHY_STATUS_26 [expr $EMIF_BASE_ADDR + 0x01a8] -set PHY_STATUS_27 [expr $EMIF_BASE_ADDR + 0x01ac] -set PHY_STATUS_28 [expr $EMIF_BASE_ADDR + 0x01b0] - -set EXT_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x0200] -set EXT_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x0204] -set EXT_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x0208] -set EXT_PHY_CTRL_2_SHDW [expr $EMIF_BASE_ADDR + 0x020c] -set EXT_PHY_CTRL_3 [expr $EMIF_BASE_ADDR + 0x0210] -set EXT_PHY_CTRL_3_SHDW [expr $EMIF_BASE_ADDR + 0x0214] -set EXT_PHY_CTRL_4 [expr $EMIF_BASE_ADDR + 0x0218] -set EXT_PHY_CTRL_4_SHDW [expr $EMIF_BASE_ADDR + 0x021c] -set EXT_PHY_CTRL_5 [expr $EMIF_BASE_ADDR + 0x0220] -set EXT_PHY_CTRL_5_SHDW [expr $EMIF_BASE_ADDR + 0x0224] -set EXT_PHY_CTRL_6 [expr $EMIF_BASE_ADDR + 0x0228] -set EXT_PHY_CTRL_6_SHDW [expr $EMIF_BASE_ADDR + 0x022c] -set EXT_PHY_CTRL_7 [expr $EMIF_BASE_ADDR + 0x0230] -set EXT_PHY_CTRL_7_SHDW [expr $EMIF_BASE_ADDR + 0x0234] -set EXT_PHY_CTRL_8 [expr $EMIF_BASE_ADDR + 0x0238] -set EXT_PHY_CTRL_8_SHDW [expr $EMIF_BASE_ADDR + 0x023c] -set EXT_PHY_CTRL_9 [expr $EMIF_BASE_ADDR + 0x0240] -set EXT_PHY_CTRL_9_SHDW [expr $EMIF_BASE_ADDR + 0x0244] -set EXT_PHY_CTRL_10 [expr $EMIF_BASE_ADDR + 0x0248] -set EXT_PHY_CTRL_10_SHDW [expr $EMIF_BASE_ADDR + 0x024c] -set EXT_PHY_CTRL_11 [expr $EMIF_BASE_ADDR + 0x0250] -set EXT_PHY_CTRL_11_SHDW [expr $EMIF_BASE_ADDR + 0x0254] -set EXT_PHY_CTRL_12 [expr $EMIF_BASE_ADDR + 0x0258] -set EXT_PHY_CTRL_12_SHDW [expr $EMIF_BASE_ADDR + 0x025c] -set EXT_PHY_CTRL_13 [expr $EMIF_BASE_ADDR + 0x0260] -set EXT_PHY_CTRL_13_SHDW [expr $EMIF_BASE_ADDR + 0x0264] -set EXT_PHY_CTRL_14 [expr $EMIF_BASE_ADDR + 0x0268] -set EXT_PHY_CTRL_14_SHDW [expr $EMIF_BASE_ADDR + 0x026c] -set EXT_PHY_CTRL_15 [expr $EMIF_BASE_ADDR + 0x0270] -set EXT_PHY_CTRL_15_SHDW [expr $EMIF_BASE_ADDR + 0x0274] -set EXT_PHY_CTRL_16 [expr $EMIF_BASE_ADDR + 0x0278] -set EXT_PHY_CTRL_16_SHDW [expr $EMIF_BASE_ADDR + 0x027c] -set EXT_PHY_CTRL_17 [expr $EMIF_BASE_ADDR + 0x0280] -set EXT_PHY_CTRL_17_SHDW [expr $EMIF_BASE_ADDR + 0x0284] -set EXT_PHY_CTRL_18 [expr $EMIF_BASE_ADDR + 0x0288] -set EXT_PHY_CTRL_18_SHDW [expr $EMIF_BASE_ADDR + 0x028c] -set EXT_PHY_CTRL_19 [expr $EMIF_BASE_ADDR + 0x0290] -set EXT_PHY_CTRL_19_SHDW [expr $EMIF_BASE_ADDR + 0x0294] -set EXT_PHY_CTRL_20 [expr $EMIF_BASE_ADDR + 0x0298] -set EXT_PHY_CTRL_20_SHDW [expr $EMIF_BASE_ADDR + 0x029c] -set EXT_PHY_CTRL_21 [expr $EMIF_BASE_ADDR + 0x02a0] -set EXT_PHY_CTRL_21_SHDW [expr $EMIF_BASE_ADDR + 0x02a4] -set EXT_PHY_CTRL_22 [expr $EMIF_BASE_ADDR + 0x02a8] -set EXT_PHY_CTRL_22_SHDW [expr $EMIF_BASE_ADDR + 0x02ac] -set EXT_PHY_CTRL_23 [expr $EMIF_BASE_ADDR + 0x02b0] -set EXT_PHY_CTRL_23_SHDW [expr $EMIF_BASE_ADDR + 0x02b4] -set EXT_PHY_CTRL_24 [expr $EMIF_BASE_ADDR + 0x02b8] -set EXT_PHY_CTRL_24_SHDW [expr $EMIF_BASE_ADDR + 0x02bc] -set EXT_PHY_CTRL_25 [expr $EMIF_BASE_ADDR + 0x02c0] -set EXT_PHY_CTRL_25_SHDW [expr $EMIF_BASE_ADDR + 0x02c4] -set EXT_PHY_CTRL_26 [expr $EMIF_BASE_ADDR + 0x02c8] -set EXT_PHY_CTRL_26_SHDW [expr $EMIF_BASE_ADDR + 0x02cc] -set EXT_PHY_CTRL_27 [expr $EMIF_BASE_ADDR + 0x02d0] -set EXT_PHY_CTRL_27_SHDW [expr $EMIF_BASE_ADDR + 0x02d4] -set EXT_PHY_CTRL_28 [expr $EMIF_BASE_ADDR + 0x02d8] -set EXT_PHY_CTRL_28_SHDW [expr $EMIF_BASE_ADDR + 0x02dc] -set EXT_PHY_CTRL_29 [expr $EMIF_BASE_ADDR + 0x02e0] -set EXT_PHY_CTRL_29_SHDW [expr $EMIF_BASE_ADDR + 0x02e4] -set EXT_PHY_CTRL_30 [expr $EMIF_BASE_ADDR + 0x02e8] -set EXT_PHY_CTRL_30_SHDW [expr $EMIF_BASE_ADDR + 0x02ec] -set EXT_PHY_CTRL_31 [expr $EMIF_BASE_ADDR + 0x02f0] -set EXT_PHY_CTRL_31_SHDW [expr $EMIF_BASE_ADDR + 0x02f4] -set EXT_PHY_CTRL_32 [expr $EMIF_BASE_ADDR + 0x02f8] -set EXT_PHY_CTRL_32_SHDW [expr $EMIF_BASE_ADDR + 0x02fc] -set EXT_PHY_CTRL_33 [expr $EMIF_BASE_ADDR + 0x0300] -set EXT_PHY_CTRL_33_SHDW [expr $EMIF_BASE_ADDR + 0x0304] -set EXT_PHY_CTRL_34 [expr $EMIF_BASE_ADDR + 0x0308] -set EXT_PHY_CTRL_34_SHDW [expr $EMIF_BASE_ADDR + 0x030c] -set EXT_PHY_CTRL_35 [expr $EMIF_BASE_ADDR + 0x0310] -set EXT_PHY_CTRL_35_SHDW [expr $EMIF_BASE_ADDR + 0x0314] -set EXT_PHY_CTRL_36 [expr $EMIF_BASE_ADDR + 0x0318] -set EXT_PHY_CTRL_36_SHDW [expr $EMIF_BASE_ADDR + 0x031c] +set EMIF_STATUS [expr {$EMIF_BASE_ADDR + 0x0004}] +set EMIF_SDRAM_CONFIG [expr {$EMIF_BASE_ADDR + 0x0008}] +set EMIF_SDRAM_CONFIG_2 [expr {$EMIF_BASE_ADDR + 0x000c}] +set EMIF_SDRAM_REF_CTRL [expr {$EMIF_BASE_ADDR + 0x0010}] +set EMIF_SDRAM_REF_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x0014}] +set EMIF_SDRAM_TIM_1 [expr {$EMIF_BASE_ADDR + 0x0018}] +set EMIF_SDRAM_TIM_1_SHDW [expr {$EMIF_BASE_ADDR + 0x001c}] +set EMIF_SDRAM_TIM_2 [expr {$EMIF_BASE_ADDR + 0x0020}] +set EMIF_SDRAM_TIM_2_SHDW [expr {$EMIF_BASE_ADDR + 0x0024}] +set EMIF_SDRAM_TIM_3 [expr {$EMIF_BASE_ADDR + 0x0028}] +set EMIF_SDRAM_TIM_3_SHDW [expr {$EMIF_BASE_ADDR + 0x002c}] +set EMIF_LPDDR2_NVM_TIM [expr {$EMIF_BASE_ADDR + 0x0030}] +set EMIF_LPDDR2_NVM_TIM_SHDW [expr {$EMIF_BASE_ADDR + 0x0034}] +set EMIF_PWR_MGMT_CTRL [expr {$EMIF_BASE_ADDR + 0x0038}] +set EMIF_PWR_MGMT_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x003c}] +set EMIF_LPDDR2_MODE_REG_DATA [expr {$EMIF_BASE_ADDR + 0x0040}] +set EMIF_LPDDR2_MODE_REG_CFG [expr {$EMIF_BASE_ADDR + 0x0050}] +set EMIF_OCP_CONFIG [expr {$EMIF_BASE_ADDR + 0x0054}] +set EMIF_OCP_CFG_VAL_1 [expr {$EMIF_BASE_ADDR + 0x0058}] +set EMIF_OCP_CFG_VAL_2 [expr {$EMIF_BASE_ADDR + 0x005c}] +set EMIF_IODFT_TLGC [expr {$EMIF_BASE_ADDR + 0x0060}] +set EMIF_IODFT_CTRL_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0064}] +set EMIF_IODFT_ADDR_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0068}] +set EMIF_IODFT_DATA_MISR_RSLT_1 [expr {$EMIF_BASE_ADDR + 0x006c}] +set EMIF_IODFT_DATA_MISR_RSLT_2 [expr {$EMIF_BASE_ADDR + 0x0070}] +set EMIF_IODFT_DATA_MISR_RSLT_3 [expr {$EMIF_BASE_ADDR + 0x0074}] +set EMIF_PERF_CNT_1 [expr {$EMIF_BASE_ADDR + 0x0080}] +set EMIF_PERF_CNT_2 [expr {$EMIF_BASE_ADDR + 0x0084}] +set EMIF_PERF_CNT_CFG [expr {$EMIF_BASE_ADDR + 0x0088}] +set EMIF_PERF_CNT_SEL [expr {$EMIF_BASE_ADDR + 0x008c}] +set EMIF_PERF_CNT_TIM [expr {$EMIF_BASE_ADDR + 0x0090}] +set EMIF_MISC_REG [expr {$EMIF_BASE_ADDR + 0x0094}] +set EMIF_DLL_CALIB_CTRL [expr {$EMIF_BASE_ADDR + 0x0098}] +set EMIF_DLL_CALIB_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x009c}] +set EMIF_IRQ_EOI [expr {$EMIF_BASE_ADDR + 0x00a0}] +set EMIF_IRQSTATUS_RAW_SYS [expr {$EMIF_BASE_ADDR + 0x00a4}] +set EMIF_IRQSTATUS_SYS [expr {$EMIF_BASE_ADDR + 0x00ac}] +set EMIF_IRQENABLE_SET_SYS [expr {$EMIF_BASE_ADDR + 0x00b4}] +set EMIF_IRQENABLE_CLR_SYS [expr {$EMIF_BASE_ADDR + 0x00bc}] +set EMIF_ZQ_CONFIG [expr {$EMIF_BASE_ADDR + 0x00c8}] +set EMIF_TEMP_ALERT_CONFIG [expr {$EMIF_BASE_ADDR + 0x00cc}] +set EMIF_OCP_ERR_LOG [expr {$EMIF_BASE_ADDR + 0x00d0}] +set EMIF_RDWR_LVL_RMP_WIN [expr {$EMIF_BASE_ADDR + 0x00d4}] +set EMIF_RDWR_LVL_RMP_CTRL [expr {$EMIF_BASE_ADDR + 0x00d8}] +set EMIF_RDWR_LVL_CTRL [expr {$EMIF_BASE_ADDR + 0x00dc}] +set EMIF_DDR_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x00e4}] +set EMIF_DDR_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x00e8}] +set EMIF_DDR_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x00ec}] +set EMIF_PRI_COS_MAP [expr {$EMIF_BASE_ADDR + 0x0100}] +set EMIF_CONNID_COS_1_MAP [expr {$EMIF_BASE_ADDR + 0x0104}] +set EMIF_CONNID_COS_2_MAP [expr {$EMIF_BASE_ADDR + 0x0108}] +set ECC_CTRL [expr {$EMIF_BASE_ADDR + 0x0110}] +set ECC_ADDR_RNG_1 [expr {$EMIF_BASE_ADDR + 0x0114}] +set ECC_ADDR_RNG_2 [expr {$EMIF_BASE_ADDR + 0x0118}] +set EMIF_RD_WR_EXEC_THRSH [expr {$EMIF_BASE_ADDR + 0x0120}] +set COS_CONFIG [expr {$EMIF_BASE_ADDR + 0x0124}] + +set PHY_STATUS_1 [expr {$EMIF_BASE_ADDR + 0x0144}] +set PHY_STATUS_2 [expr {$EMIF_BASE_ADDR + 0x0148}] +set PHY_STATUS_3 [expr {$EMIF_BASE_ADDR + 0x014c}] +set PHY_STATUS_4 [expr {$EMIF_BASE_ADDR + 0x0150}] +set PHY_STATUS_5 [expr {$EMIF_BASE_ADDR + 0x0154}] +set PHY_STATUS_6 [expr {$EMIF_BASE_ADDR + 0x0158}] +set PHY_STATUS_7 [expr {$EMIF_BASE_ADDR + 0x015c}] +set PHY_STATUS_8 [expr {$EMIF_BASE_ADDR + 0x0160}] +set PHY_STATUS_9 [expr {$EMIF_BASE_ADDR + 0x0164}] +set PHY_STATUS_10 [expr {$EMIF_BASE_ADDR + 0x0168}] +set PHY_STATUS_11 [expr {$EMIF_BASE_ADDR + 0x016c}] +set PHY_STATUS_12 [expr {$EMIF_BASE_ADDR + 0x0170}] +set PHY_STATUS_13 [expr {$EMIF_BASE_ADDR + 0x0174}] +set PHY_STATUS_14 [expr {$EMIF_BASE_ADDR + 0x0178}] +set PHY_STATUS_15 [expr {$EMIF_BASE_ADDR + 0x017c}] +set PHY_STATUS_16 [expr {$EMIF_BASE_ADDR + 0x0180}] +set PHY_STATUS_17 [expr {$EMIF_BASE_ADDR + 0x0184}] +set PHY_STATUS_18 [expr {$EMIF_BASE_ADDR + 0x0188}] +set PHY_STATUS_19 [expr {$EMIF_BASE_ADDR + 0x018c}] +set PHY_STATUS_20 [expr {$EMIF_BASE_ADDR + 0x0190}] +set PHY_STATUS_21 [expr {$EMIF_BASE_ADDR + 0x0194}] +set PHY_STATUS_22 [expr {$EMIF_BASE_ADDR + 0x0198}] +set PHY_STATUS_23 [expr {$EMIF_BASE_ADDR + 0x019c}] +set PHY_STATUS_24 [expr {$EMIF_BASE_ADDR + 0x01a0}] +set PHY_STATUS_25 [expr {$EMIF_BASE_ADDR + 0x01a4}] +set PHY_STATUS_26 [expr {$EMIF_BASE_ADDR + 0x01a8}] +set PHY_STATUS_27 [expr {$EMIF_BASE_ADDR + 0x01ac}] +set PHY_STATUS_28 [expr {$EMIF_BASE_ADDR + 0x01b0}] + +set EXT_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x0200}] +set EXT_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x0204}] +set EXT_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x0208}] +set EXT_PHY_CTRL_2_SHDW [expr {$EMIF_BASE_ADDR + 0x020c}] +set EXT_PHY_CTRL_3 [expr {$EMIF_BASE_ADDR + 0x0210}] +set EXT_PHY_CTRL_3_SHDW [expr {$EMIF_BASE_ADDR + 0x0214}] +set EXT_PHY_CTRL_4 [expr {$EMIF_BASE_ADDR + 0x0218}] +set EXT_PHY_CTRL_4_SHDW [expr {$EMIF_BASE_ADDR + 0x021c}] +set EXT_PHY_CTRL_5 [expr {$EMIF_BASE_ADDR + 0x0220}] +set EXT_PHY_CTRL_5_SHDW [expr {$EMIF_BASE_ADDR + 0x0224}] +set EXT_PHY_CTRL_6 [expr {$EMIF_BASE_ADDR + 0x0228}] +set EXT_PHY_CTRL_6_SHDW [expr {$EMIF_BASE_ADDR + 0x022c}] +set EXT_PHY_CTRL_7 [expr {$EMIF_BASE_ADDR + 0x0230}] +set EXT_PHY_CTRL_7_SHDW [expr {$EMIF_BASE_ADDR + 0x0234}] +set EXT_PHY_CTRL_8 [expr {$EMIF_BASE_ADDR + 0x0238}] +set EXT_PHY_CTRL_8_SHDW [expr {$EMIF_BASE_ADDR + 0x023c}] +set EXT_PHY_CTRL_9 [expr {$EMIF_BASE_ADDR + 0x0240}] +set EXT_PHY_CTRL_9_SHDW [expr {$EMIF_BASE_ADDR + 0x0244}] +set EXT_PHY_CTRL_10 [expr {$EMIF_BASE_ADDR + 0x0248}] +set EXT_PHY_CTRL_10_SHDW [expr {$EMIF_BASE_ADDR + 0x024c}] +set EXT_PHY_CTRL_11 [expr {$EMIF_BASE_ADDR + 0x0250}] +set EXT_PHY_CTRL_11_SHDW [expr {$EMIF_BASE_ADDR + 0x0254}] +set EXT_PHY_CTRL_12 [expr {$EMIF_BASE_ADDR + 0x0258}] +set EXT_PHY_CTRL_12_SHDW [expr {$EMIF_BASE_ADDR + 0x025c}] +set EXT_PHY_CTRL_13 [expr {$EMIF_BASE_ADDR + 0x0260}] +set EXT_PHY_CTRL_13_SHDW [expr {$EMIF_BASE_ADDR + 0x0264}] +set EXT_PHY_CTRL_14 [expr {$EMIF_BASE_ADDR + 0x0268}] +set EXT_PHY_CTRL_14_SHDW [expr {$EMIF_BASE_ADDR + 0x026c}] +set EXT_PHY_CTRL_15 [expr {$EMIF_BASE_ADDR + 0x0270}] +set EXT_PHY_CTRL_15_SHDW [expr {$EMIF_BASE_ADDR + 0x0274}] +set EXT_PHY_CTRL_16 [expr {$EMIF_BASE_ADDR + 0x0278}] +set EXT_PHY_CTRL_16_SHDW [expr {$EMIF_BASE_ADDR + 0x027c}] +set EXT_PHY_CTRL_17 [expr {$EMIF_BASE_ADDR + 0x0280}] +set EXT_PHY_CTRL_17_SHDW [expr {$EMIF_BASE_ADDR + 0x0284}] +set EXT_PHY_CTRL_18 [expr {$EMIF_BASE_ADDR + 0x0288}] +set EXT_PHY_CTRL_18_SHDW [expr {$EMIF_BASE_ADDR + 0x028c}] +set EXT_PHY_CTRL_19 [expr {$EMIF_BASE_ADDR + 0x0290}] +set EXT_PHY_CTRL_19_SHDW [expr {$EMIF_BASE_ADDR + 0x0294}] +set EXT_PHY_CTRL_20 [expr {$EMIF_BASE_ADDR + 0x0298}] +set EXT_PHY_CTRL_20_SHDW [expr {$EMIF_BASE_ADDR + 0x029c}] +set EXT_PHY_CTRL_21 [expr {$EMIF_BASE_ADDR + 0x02a0}] +set EXT_PHY_CTRL_21_SHDW [expr {$EMIF_BASE_ADDR + 0x02a4}] +set EXT_PHY_CTRL_22 [expr {$EMIF_BASE_ADDR + 0x02a8}] +set EXT_PHY_CTRL_22_SHDW [expr {$EMIF_BASE_ADDR + 0x02ac}] +set EXT_PHY_CTRL_23 [expr {$EMIF_BASE_ADDR + 0x02b0}] +set EXT_PHY_CTRL_23_SHDW [expr {$EMIF_BASE_ADDR + 0x02b4}] +set EXT_PHY_CTRL_24 [expr {$EMIF_BASE_ADDR + 0x02b8}] +set EXT_PHY_CTRL_24_SHDW [expr {$EMIF_BASE_ADDR + 0x02bc}] +set EXT_PHY_CTRL_25 [expr {$EMIF_BASE_ADDR + 0x02c0}] +set EXT_PHY_CTRL_25_SHDW [expr {$EMIF_BASE_ADDR + 0x02c4}] +set EXT_PHY_CTRL_26 [expr {$EMIF_BASE_ADDR + 0x02c8}] +set EXT_PHY_CTRL_26_SHDW [expr {$EMIF_BASE_ADDR + 0x02cc}] +set EXT_PHY_CTRL_27 [expr {$EMIF_BASE_ADDR + 0x02d0}] +set EXT_PHY_CTRL_27_SHDW [expr {$EMIF_BASE_ADDR + 0x02d4}] +set EXT_PHY_CTRL_28 [expr {$EMIF_BASE_ADDR + 0x02d8}] +set EXT_PHY_CTRL_28_SHDW [expr {$EMIF_BASE_ADDR + 0x02dc}] +set EXT_PHY_CTRL_29 [expr {$EMIF_BASE_ADDR + 0x02e0}] +set EXT_PHY_CTRL_29_SHDW [expr {$EMIF_BASE_ADDR + 0x02e4}] +set EXT_PHY_CTRL_30 [expr {$EMIF_BASE_ADDR + 0x02e8}] +set EXT_PHY_CTRL_30_SHDW [expr {$EMIF_BASE_ADDR + 0x02ec}] +set EXT_PHY_CTRL_31 [expr {$EMIF_BASE_ADDR + 0x02f0}] +set EXT_PHY_CTRL_31_SHDW [expr {$EMIF_BASE_ADDR + 0x02f4}] +set EXT_PHY_CTRL_32 [expr {$EMIF_BASE_ADDR + 0x02f8}] +set EXT_PHY_CTRL_32_SHDW [expr {$EMIF_BASE_ADDR + 0x02fc}] +set EXT_PHY_CTRL_33 [expr {$EMIF_BASE_ADDR + 0x0300}] +set EXT_PHY_CTRL_33_SHDW [expr {$EMIF_BASE_ADDR + 0x0304}] +set EXT_PHY_CTRL_34 [expr {$EMIF_BASE_ADDR + 0x0308}] +set EXT_PHY_CTRL_34_SHDW [expr {$EMIF_BASE_ADDR + 0x030c}] +set EXT_PHY_CTRL_35 [expr {$EMIF_BASE_ADDR + 0x0310}] +set EXT_PHY_CTRL_35_SHDW [expr {$EMIF_BASE_ADDR + 0x0314}] +set EXT_PHY_CTRL_36 [expr {$EMIF_BASE_ADDR + 0x0318}] +set EXT_PHY_CTRL_36_SHDW [expr {$EMIF_BASE_ADDR + 0x031c}] set WDT1_BASE_ADDR 0x44e35000 -set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034] -set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048] +set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}] +set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}] set RTC_BASE_ADDR 0x44e3e000 -set RTC_KICK0R [expr $RTC_BASE_ADDR + 0x6c] -set RTC_KICK1R [expr $RTC_BASE_ADDR + 0x70] +set RTC_KICK0R [expr {$RTC_BASE_ADDR + 0x6c}] +set RTC_KICK1R [expr {$RTC_BASE_ADDR + 0x70}] if { [info exists CHIPNAME] } { @@ -520,15 +520,15 @@ proc disable_watchdog { } { } proc ceil { x y } { - return [ expr ($x + $y - 1) / $y ] + return [ expr {($x + $y - 1) / $y} ] } proc device_type { } { global CONTROL_STATUS set tmp [ mrw $CONTROL_STATUS ] - set tmp [ expr $tmp & 0x700 ] - set tmp [ expr $tmp >> 8 ] + set tmp [ expr {$tmp & 0x700} ] + set tmp [ expr {$tmp >> 8} ] return $tmp } @@ -542,8 +542,8 @@ proc get_input_clock_frequency { } { } set freq [ mrw $CONTROL_STATUS ] - set freq [ expr $freq & 0x00c00000 ] - set freq [ expr $freq >> 22 ] + set freq [ expr {$freq & 0x00c00000} ] + set freq [ expr {$freq >> 22} ] switch $freq { 0 { @@ -578,12 +578,12 @@ proc mpu_pll_config { CLKIN N M M2 } { mww $CM_CLKMODE_DPLL_MPU 0x4 while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { } - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] mww $CM_CLKSEL_DPLL_MPU $clksel - set div_m2 [ expr $div_m2 & (~0x1f) ] - set div_m2 [ expr $div_m2 | $M2 ] + set div_m2 [ expr {$div_m2 & (~0x1f)} ] + set div_m2 [ expr {$div_m2 | $M2} ] mww $CM_DIV_M2_DPLL_MPU $div_m2 mww $CM_CLKMODE_DPLL_MPU 0x7 @@ -605,8 +605,8 @@ proc core_pll_config { CLKIN N M M4 M5 M6 } { mww $CM_CLKMODE_DPLL_CORE 0x4 while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { } - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] mww $CM_CLKSEL_DPLL_CORE $clksel mww $CM_DIV_M4_DPLL_CORE $M4 mww $CM_DIV_M5_DPLL_CORE $M5 @@ -624,8 +624,8 @@ proc per_pll_config { CLKIN N M M2 } { global CM_DIV_M2_DPLL_PER global CM_IDLEST_DPLL_PER - set x [ expr $M * $CLKIN / 1000000 ] - set y [ expr ($N + 1) * 250 ] + set x [ expr {$M * $CLKIN / 1000000} ] + set y [ expr {($N + 1) * 250} ] set sd [ ceil $x $y ] set clksel [ mrw $CM_CLKSEL_DPLL_PER ] @@ -634,12 +634,12 @@ proc per_pll_config { CLKIN N M M2 } { mww $CM_CLKMODE_DPLL_PER 0x4 while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { } - set clksel [ expr $clksel & (~0xff0fffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] - set clksel [ expr $clksel | ($sd << 24) ] + set clksel [ expr {$clksel & (~0xff0fffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] + set clksel [ expr {$clksel | ($sd << 24)} ] mww $CM_CLKSEL_DPLL_PER $clksel - set div_m2 [ expr 0xffffff80 | $M2 ] + set div_m2 [ expr {0xffffff80 | $M2} ] mww $CM_CLKMODE_DPLL_PER 0x7 while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { } @@ -660,11 +660,11 @@ proc ddr_pll_config { CLKIN N M M2 M4 } { mww $CM_CLKMODE_DPLL_DDR 0x4 while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { } - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 8) | $N ] + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 8) | $N} ] mww $CM_CLKSEL_DPLL_DDR $clksel - set div_m2 [ expr ($div_m2 & 0xffffffe0) | $M2 ] + set div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ] mww $CM_DIV_M2_DPLL_DDR $div_m2 mww $CM_DIV_M4_DPLL_DDR $M4 @@ -849,18 +849,18 @@ proc config_ddr_phy { } { set gatelvl_num_dq0 0x0f set wrlvl_num_dq0 0x0f - mww $EXT_PHY_CTRL_1 [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ] - mww $EXT_PHY_CTRL_1_SHDW [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ] - mww $EXT_PHY_CTRL_26 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_26_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_27 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_27_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_28 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_28_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_29 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_29_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_30 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_30_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] + mww $EXT_PHY_CTRL_1 [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ] + mww $EXT_PHY_CTRL_1_SHDW [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ] + mww $EXT_PHY_CTRL_26 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_26_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_27 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_27_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_28 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_28_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_29 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_29_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_30 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_30_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] mww $EXT_PHY_CTRL_31 0x00 mww $EXT_PHY_CTRL_31_SHDW 0x00 mww $EXT_PHY_CTRL_32 0x00 @@ -873,14 +873,14 @@ proc config_ddr_phy { } { mww $EXT_PHY_CTRL_35_SHDW 0x00 mww $EXT_PHY_CTRL_22 0x00 mww $EXT_PHY_CTRL_22_SHDW 0x00 - mww $EXT_PHY_CTRL_23 [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ] - mww $EXT_PHY_CTRL_23_SHDW [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ] - mww $EXT_PHY_CTRL_24 [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay ] - mww $EXT_PHY_CTRL_24_SHDW [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0 ] - mww $EXT_PHY_CTRL_25 [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ] - mww $EXT_PHY_CTRL_25_SHDW [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ] - mww $EXT_PHY_CTRL_36 [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ] - mww $EXT_PHY_CTRL_36_SHDW [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ] + mww $EXT_PHY_CTRL_23 [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ] + mww $EXT_PHY_CTRL_23_SHDW [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ] + mww $EXT_PHY_CTRL_24 [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ] + mww $EXT_PHY_CTRL_24_SHDW [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ] + mww $EXT_PHY_CTRL_25 [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ] + mww $EXT_PHY_CTRL_25_SHDW [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ] + mww $EXT_PHY_CTRL_36 [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ] + mww $EXT_PHY_CTRL_36_SHDW [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ] } proc config_ddr_timing { } { diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg index 7115a839d2..2e828de869 100644 --- a/tcl/target/ampere_emag.cfg +++ b/tcl/target/ampere_emag.cfg @@ -78,7 +78,7 @@ for {set _i 0} {$_i < $_NUMCORES} {incr _i} { # Create and configure Cross Trigger Interface (CTI) - required for halt and resume set _CTINAME $_TARGETNAME.cti - cti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr 0xFC020000 + ($_i << 20)] + cti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr {0xFC020000 + ($_i << 20)}] # Create the target target create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_DAPNAME -ap-num $_APNUM -cti $_CTINAME -coreid $_i diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg index a9d321ee6b..66473251fd 100644 --- a/tcl/target/bluenrg-x.cfg +++ b/tcl/target/bluenrg-x.cfg @@ -54,9 +54,9 @@ $_TARGETNAME configure -event halted { if {$_JTAG_IDCODE != 0x0201E041} { # Stop watchdog during halt, if enabled. Only Bluenrg-1/2 set WDOG_VALUE [mrw 0x40700008] - if [expr ($WDOG_VALUE & (1 << 1))] { + if [expr {$WDOG_VALUE & (1 << 1)}] { set WDOG_VALUE_SET 1 - mww 0x40700008 [expr ($WDOG_VALUE & 0xFFFFFFFD)] + mww 0x40700008 [expr {$WDOG_VALUE & 0xFFFFFFFD}] } } } diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl index 53b2c5d480..17639fd58c 100644 --- a/tcl/target/c100config.tcl +++ b/tcl/target/c100config.tcl @@ -111,23 +111,23 @@ proc setupGPIO {} { set GPIO_OE_REG [regs GPIO_OE_REG] # set GPIO29=GPIO17=1, GPIO5=0 - mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17] + mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}] # enable [as output] GPIO29,GPIO17,GPIO5 - mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5] + mww $GPIO_OE_REG [expr {1<<29 | 1<<17 | 1<<5}] } proc highGPIO5 {} { echo "GPIO5 high" set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=1 - mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0 + mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0 } proc lowGPIO5 {} { echo "GPIO5 low" set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=0 - mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5] + mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}] } proc boardID {id} { @@ -163,7 +163,7 @@ proc ooma_board_detect {} { set tmp [mrw $GPIO_BOOTSTRAP_REG] echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] # extract the GPBP bits - set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3] + set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}] # display board ID echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt] @@ -226,13 +226,13 @@ proc configureDDR2regs_256M {} { set wr_dqs_shift 0x40 # start DDRC - mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] # wait int_status[2] (DRAM init complete) echo -n "Waiting for DDR2 controller to init..." - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { sleep 1 - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] } echo "done." @@ -294,16 +294,16 @@ proc configureDDR2regs_128M {} { set wr_dqs_shift 0x40 # start DDRC - mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] # wait int_status[2] (DRAM init complete) echo -n "Waiting for DDR2 controller to init..." - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { sleep 1 - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] } # This is not necessary - #mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ] + #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ] echo "done." # do ddr2 training sequence @@ -341,14 +341,14 @@ proc setupUART0 {} { # Enable Divisor Latch access mmw $UART0_LCR $LCR_DLAB 0x0 # set the divisor to $tmp - mww $UART0_DLL [expr $tmp & 0xff] - mww $UART0_DLH [expr $tmp >> 8] + mww $UART0_DLL [expr {$tmp & 0xff}] + mww $UART0_DLH [expr {$tmp >> 8}] # Disable Divisor Latch access mmw $UART0_LCR 0x0 $LCR_DLAB # set the UART to 8N1 - mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0 + mmw $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0 # reset FIFO - mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0 + mmw $UART0_IIR [expr {$FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0 # enable FFUART mww $UART0_IER $IER_UUE } @@ -372,7 +372,7 @@ proc putsUART0 {str} { set len [string length $str] while { $index < $len } { putcUART0 [string index $str $index] - set index [expr $index + 1] + set index [expr {$index + 1}] } } diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index 725ba709c9..9b8256d7e4 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -37,11 +37,11 @@ proc mr64bit {reg} { # write a 64-bit register (memory mapped) proc mw64bit {reg value} { - set high [expr $value >> 32] - set low [expr $value & 0xffffffff] + set high [expr {$value >> 32}] + set low [expr {$value & 0xffffffff}] #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low] mww $reg $low - mww [expr $reg+4] $high + mww [expr {$reg+4}] $high } @@ -122,7 +122,7 @@ proc showAmbaClk {} { set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] echo [format "PLL bypass bit: %d" $bypass] if {$bypass == 1} { - echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]] + echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] } else { # nope, extract x,y,w and compute the PLL output freq. set x [expr ($value(0) & 0x0001F0000) >> 16] @@ -131,7 +131,7 @@ proc showAmbaClk {} { echo [format "y: %d" $y] set w [expr ($value(0) & 0x000000300) >> 8] echo [format "w: %d" $w] - echo [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]] + echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] } } @@ -154,7 +154,7 @@ proc setupAmbaClk {} { set x [config x_amba] set y [config y_amba] - echo [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]] + echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]] #echo [format "setupAmbaClk: w= %d" $w] #echo [format "setupAmbaClk: x= %d" $x] #echo [format "setupAmbaClk: y= %d" $y] @@ -174,7 +174,7 @@ proc setupAmbaClk {} { sleep 1 # set X, W and X mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF - mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0 + mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 } @@ -197,7 +197,7 @@ proc showArmClk {} { set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] echo [format "PLL bypass bit: %d" $bypass] if {$bypass == 1} { - echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]] + echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] } else { # nope, extract x,y,w and compute the PLL output freq. set x [expr ($value(0) & 0x0001F0000) >> 16] @@ -206,7 +206,7 @@ proc showArmClk {} { echo [format "y: %d" $y] set w [expr ($value(0) & 0x000000300) >> 8] echo [format "w: %d" $w] - echo [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]] + echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] } } @@ -228,7 +228,7 @@ proc setupArmClk {} { set x [config x_arm] set y [config y_arm] - echo [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]] + echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]] #echo [format "setupArmClk: w= %d" $w] #echo [format "setupArmaClk: x= %d" $x] #echo [format "setupArmaClk: y= %d" $y] @@ -248,7 +248,7 @@ proc setupArmClk {} { sleep 1 # set X, W and X mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF - mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0 + mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 } @@ -281,11 +281,11 @@ proc setupDDR2 {} { # and not reset. mmw $BLOCK_RESET_REG 0x0 $DDR_RST - set M [expr 1024 * 1024] - set DDR_SZ_1024M [expr 1024 * $M] - set DDR_SZ_256M [expr 256 * $M] - set DDR_SZ_128M [expr 128 * $M] - set DDR_SZ_64M [expr 64 * $M] + set M [expr {1024 * 1024}] + set DDR_SZ_1024M [expr {1024 * $M}] + set DDR_SZ_256M [expr {256 * $M}] + set DDR_SZ_128M [expr {128 * $M}] + set DDR_SZ_64M [expr {64 * $M}] # ooma_board_detect returns DDR2 memory size set tmp [ooma_board_detect] if {$tmp == "128M"} { @@ -299,7 +299,7 @@ proc setupDDR2 {} { } # Memory setup register - mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR] + mww $MEMORY_MAX_ADDR [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}] # disable ROM remap mww $MEMORY_CR 0x0 # Take DDR controller out of reset @@ -445,9 +445,9 @@ proc initC100 {} { mww [expr $APB_ACCESS_WS_REG] 0x40 # AHB init # // enable all 6 masters for ARAM - mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0 + mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 # // enable all 6 masters for EBUS - mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0 + mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 # ARAM init # // disable pipeline mode in ARAM diff --git a/tcl/target/c100regs.tcl b/tcl/target/c100regs.tcl index a2c7a60d05..9304808240 100644 --- a/tcl/target/c100regs.tcl +++ b/tcl/target/c100regs.tcl @@ -35,43 +35,43 @@ dict set regsC100 EXP_CS4_BASEADDR 0x30000000 dict set regsC100 DDR_BASEADDR 0x80000000 -dict set regsC100 TDM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x000000] -dict set regsC100 PHI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x010000] -dict set regsC100 TDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x020000] -dict set regsC100 ASA_DDR_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x040000] -dict set regsC100 ASA_ARAM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x048000] -dict set regsC100 TIMER_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x050000] -dict set regsC100 ASD_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x060000] -dict set regsC100 GPIO_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x070000] -dict set regsC100 UART0_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x090000] -dict set regsC100 UART1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x094000] -dict set regsC100 SPI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x098000] -dict set regsC100 I2C_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x09C000] -dict set regsC100 INTC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0A0000] -dict set regsC100 CLKCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000] -dict set regsC100 PUI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000] -dict set regsC100 GEMAC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0D0000] -dict set regsC100 IDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0E0000] -dict set regsC100 MEMCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0F0000] -dict set regsC100 ASA_EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x100000] -dict set regsC100 ASA_AAB_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x108000] -dict set regsC100 GEMAC1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x190000] -dict set regsC100 EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1A0000] -dict set regsC100 MDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1E0000] +dict set regsC100 TDM_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x000000}] +dict set regsC100 PHI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x010000}] +dict set regsC100 TDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x020000}] +dict set regsC100 ASA_DDR_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x040000}] +dict set regsC100 ASA_ARAM_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x048000}] +dict set regsC100 TIMER_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x050000}] +dict set regsC100 ASD_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x060000}] +dict set regsC100 GPIO_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x070000}] +dict set regsC100 UART0_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x090000}] +dict set regsC100 UART1_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x094000}] +dict set regsC100 SPI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x098000}] +dict set regsC100 I2C_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x09C000}] +dict set regsC100 INTC_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0A0000}] +dict set regsC100 CLKCORE_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}] +dict set regsC100 PUI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}] +dict set regsC100 GEMAC_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0D0000}] +dict set regsC100 IDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0E0000}] +dict set regsC100 MEMCORE_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0F0000}] +dict set regsC100 ASA_EBUS_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x100000}] +dict set regsC100 ASA_AAB_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x108000}] +dict set regsC100 GEMAC1_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x190000}] +dict set regsC100 EBUS_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1A0000}] +dict set regsC100 MDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1E0000}] #//////////////////////////////////////////////////////////// #// AHB block // #//////////////////////////////////////////////////////////// -dict set regsC100 ASA_ARAM_PRI_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00] -dict set regsC100 ASA_ARAM_TC_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04] -dict set regsC100 ASA_ARAM_TC_CR_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08] -dict set regsC100 ASA_ARAM_STAT_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C] +dict set regsC100 ASA_ARAM_PRI_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00}] +dict set regsC100 ASA_ARAM_TC_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04}] +dict set regsC100 ASA_ARAM_TC_CR_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08}] +dict set regsC100 ASA_ARAM_STAT_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C}] -dict set regsC100 ASA_EBUS_PRI_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00] -dict set regsC100 ASA_EBUS_TC_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04] -dict set regsC100 ASA_EBUS_TC_CR_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08] -dict set regsC100 ASA_EBUS_STAT_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C] +dict set regsC100 ASA_EBUS_PRI_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00}] +dict set regsC100 ASA_EBUS_TC_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04}] +dict set regsC100 ASA_EBUS_TC_CR_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08}] +dict set regsC100 ASA_EBUS_STAT_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C}] dict set regsC100 IDMA_MASTER 0 dict set regsC100 TDMA_MASTER 1 @@ -87,16 +87,16 @@ dict set regsC100 MDMA_MASTER 5 #define ARM1_PRIORITY(level) (level << 16) #define MDMA_PRIORITY(level) (level << 20) -dict set regsC100 ASA_TC_REQIDMAEN [expr 1<<18] -dict set regsC100 ASA_TC_REQTDMEN [expr 1<<19] -dict set regsC100 ASA_TC_REQIPSECUSBEN [expr 1<<20] -dict set regsC100 ASA_TC_REQARM0EN [expr 1<<21] -dict set regsC100 ASA_TC_REQARM1EN [expr 1<<22] -dict set regsC100 ASA_TC_REQMDMAEN [expr 1<<23] +dict set regsC100 ASA_TC_REQIDMAEN [expr {1<<18}] +dict set regsC100 ASA_TC_REQTDMEN [expr {1<<19}] +dict set regsC100 ASA_TC_REQIPSECUSBEN [expr {1<<20}] +dict set regsC100 ASA_TC_REQARM0EN [expr {1<<21}] +dict set regsC100 ASA_TC_REQARM1EN [expr {1<<22}] +dict set regsC100 ASA_TC_REQMDMAEN [expr {1<<23}] dict set regsC100 MEMORY_BASE_ADDR 0x80000000 -dict set regsC100 MEMORY_MAX_ADDR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x10] -dict set regsC100 MEMORY_CR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x14] +dict set regsC100 MEMORY_MAX_ADDR [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x10}] +dict set regsC100 MEMORY_CR [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x14}] dict set regsC100 ROM_REMAP_EN 0x1 #define HAL_asb_priority(level) \ @@ -115,33 +115,33 @@ dict set regsC100 ROM_REMAP_EN 0x1 #// INTC block // #//////////////////////////////////////////////////////////// -dict set regsC100 INTC_ARM1_CONTROL_REG [expr [dict get $regsC100 INTC_BASEADDR ] + 0x18] +dict set regsC100 INTC_ARM1_CONTROL_REG [expr {[dict get $regsC100 INTC_BASEADDR ] + 0x18}] #//////////////////////////////////////////////////////////// #// TIMER block // #//////////////////////////////////////////////////////////// -dict set regsC100 TIMER0_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x00] -dict set regsC100 TIMER0_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x04] -dict set regsC100 TIMER1_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x08] -dict set regsC100 TIMER1_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x0C] +dict set regsC100 TIMER0_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x00}] +dict set regsC100 TIMER0_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x04}] +dict set regsC100 TIMER1_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x08}] +dict set regsC100 TIMER1_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x0C}] -dict set regsC100 TIMER2_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x18] -dict set regsC100 TIMER2_LBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x10] -dict set regsC100 TIMER2_HBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x14] -dict set regsC100 TIMER2_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x1C] +dict set regsC100 TIMER2_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x18}] +dict set regsC100 TIMER2_LBOUND_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x10}] +dict set regsC100 TIMER2_HBOUND_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x14}] +dict set regsC100 TIMER2_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x1C}] -dict set regsC100 TIMER3_LOBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x20] -dict set regsC100 TIMER3_HIBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x24] -dict set regsC100 TIMER3_CTRL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x28] -dict set regsC100 TIMER3_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x2C] +dict set regsC100 TIMER3_LOBND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x20}] +dict set regsC100 TIMER3_HIBND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x24}] +dict set regsC100 TIMER3_CTRL [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x28}] +dict set regsC100 TIMER3_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x2C}] -dict set regsC100 TIMER_MASK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x40] -dict set regsC100 TIMER_STATUS [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50] -dict set regsC100 TIMER_ACK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50] -dict set regsC100 TIMER_WDT_HIGH_BOUND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD0] -dict set regsC100 TIMER_WDT_CONTROL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD4] -dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD8] +dict set regsC100 TIMER_MASK [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x40}] +dict set regsC100 TIMER_STATUS [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}] +dict set regsC100 TIMER_ACK [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}] +dict set regsC100 TIMER_WDT_HIGH_BOUND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD0}] +dict set regsC100 TIMER_WDT_CONTROL [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD4}] +dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD8}] @@ -149,40 +149,40 @@ dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEAD #// EBUS block #//////////////////////////////////////////////////////////// -dict set regsC100 EX_SWRST_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x00] -dict set regsC100 EX_CSEN_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x04] -dict set regsC100 EX_CS0_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x08] -dict set regsC100 EX_CS1_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x0C] -dict set regsC100 EX_CS2_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x10] -dict set regsC100 EX_CS3_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x14] -dict set regsC100 EX_CS4_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x18] -dict set regsC100 EX_CS0_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x1C] -dict set regsC100 EX_CS1_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x20] -dict set regsC100 EX_CS2_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x24] -dict set regsC100 EX_CS3_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x28] -dict set regsC100 EX_CS4_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x2C] -dict set regsC100 EX_CS0_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x30] -dict set regsC100 EX_CS1_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x34] -dict set regsC100 EX_CS2_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x38] -dict set regsC100 EX_CS3_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x3C] -dict set regsC100 EX_CS4_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x40] -dict set regsC100 EX_CS0_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x44] -dict set regsC100 EX_CS1_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x48] -dict set regsC100 EX_CS2_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x4C] -dict set regsC100 EX_CS3_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x50] -dict set regsC100 EX_CS4_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x54] -dict set regsC100 EX_CS0_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x58] -dict set regsC100 EX_CS1_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x5C] -dict set regsC100 EX_CS2_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x60] -dict set regsC100 EX_CS3_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x64] -dict set regsC100 EX_CS4_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x68] -dict set regsC100 EX_CLOCK_DIV_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x6C] - -dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100] -dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100] -dict set regsC100 EX_CSFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x104] -dict set regsC100 EX_WRFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x108] -dict set regsC100 EX_RDFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x10C] +dict set regsC100 EX_SWRST_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x00}] +dict set regsC100 EX_CSEN_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x04}] +dict set regsC100 EX_CS0_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x08}] +dict set regsC100 EX_CS1_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x0C}] +dict set regsC100 EX_CS2_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x10}] +dict set regsC100 EX_CS3_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x14}] +dict set regsC100 EX_CS4_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x18}] +dict set regsC100 EX_CS0_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x1C}] +dict set regsC100 EX_CS1_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x20}] +dict set regsC100 EX_CS2_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x24}] +dict set regsC100 EX_CS3_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x28}] +dict set regsC100 EX_CS4_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x2C}] +dict set regsC100 EX_CS0_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x30}] +dict set regsC100 EX_CS1_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x34}] +dict set regsC100 EX_CS2_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x38}] +dict set regsC100 EX_CS3_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x3C}] +dict set regsC100 EX_CS4_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x40}] +dict set regsC100 EX_CS0_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x44}] +dict set regsC100 EX_CS1_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x48}] +dict set regsC100 EX_CS2_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x4C}] +dict set regsC100 EX_CS3_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x50}] +dict set regsC100 EX_CS4_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x54}] +dict set regsC100 EX_CS0_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x58}] +dict set regsC100 EX_CS1_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x5C}] +dict set regsC100 EX_CS2_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x60}] +dict set regsC100 EX_CS3_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x64}] +dict set regsC100 EX_CS4_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x68}] +dict set regsC100 EX_CLOCK_DIV_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x6C}] + +dict set regsC100 EX_MFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}] +dict set regsC100 EX_MFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}] +dict set regsC100 EX_CSFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x104}] +dict set regsC100 EX_WRFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x108}] +dict set regsC100 EX_RDFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x10C}] dict set regsC100 EX_CLK_EN 0x00000001 @@ -211,21 +211,21 @@ dict set regsC100 EX_RDY_EDGE 0x00000800 #//////////////////////////////////////////////////////////// # GPIO outputs register -dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00] +dict set regsC100 GPIO_OUTPUT_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x00}] # GPIO Output Enable register -dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04] -dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08] -dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C] +dict set regsC100 GPIO_OE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x04}] +dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x08}] +dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x0C}] # GPIO input register -dict set regsC100 GPIO_INPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x10] -dict set regsC100 APB_ACCESS_WS_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x14] -dict set regsC100 MUX_CONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x18] -dict set regsC100 SYSCONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x1C] -dict set regsC100 GPIO_ARM_ID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x30] -dict set regsC100 GPIO_BOOTSTRAP_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x40] -dict set regsC100 GPIO_LOCK_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x38] -dict set regsC100 GPIO_IOCTRL_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x44] -dict set regsC100 GPIO_DEVID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x50] +dict set regsC100 GPIO_INPUT_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x10}] +dict set regsC100 APB_ACCESS_WS_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x14}] +dict set regsC100 MUX_CONF_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x18}] +dict set regsC100 SYSCONF_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x1C}] +dict set regsC100 GPIO_ARM_ID_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x30}] +dict set regsC100 GPIO_BOOTSTRAP_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x40}] +dict set regsC100 GPIO_LOCK_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x38}] +dict set regsC100 GPIO_IOCTRL_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x44}] +dict set regsC100 GPIO_DEVID_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x50}] dict set regsC100 GPIO_IOCTRL_A15A16 0x00000001 dict set regsC100 GPIO_IOCTRL_A17A18 0x00000002 @@ -258,31 +258,31 @@ dict set regsC100 GPIO_BOTH_EDGES 3 #// UART #//////////////////////////////////////////////////////////// -dict set regsC100 UART0_RBR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_THR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_DLL [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_IER [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04] -dict set regsC100 UART0_DLH [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04] -dict set regsC100 UART0_IIR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08] -dict set regsC100 UART0_FCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08] -dict set regsC100 UART0_LCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x0C] -dict set regsC100 UART0_MCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x10] -dict set regsC100 UART0_LSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x14] -dict set regsC100 UART0_MSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x18] -dict set regsC100 UART0_SCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x1C] - -dict set regsC100 UART1_RBR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_THR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_DLL [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_IER [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04] -dict set regsC100 UART1_DLH [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04] -dict set regsC100 UART1_IIR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08] -dict set regsC100 UART1_FCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08] -dict set regsC100 UART1_LCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x0C] -dict set regsC100 UART1_MCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x10] -dict set regsC100 UART1_LSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x14] -dict set regsC100 UART1_MSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18] -dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C] +dict set regsC100 UART0_RBR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_THR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_DLL [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_IER [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}] +dict set regsC100 UART0_DLH [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}] +dict set regsC100 UART0_IIR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}] +dict set regsC100 UART0_FCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}] +dict set regsC100 UART0_LCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x0C}] +dict set regsC100 UART0_MCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x10}] +dict set regsC100 UART0_LSR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x14}] +dict set regsC100 UART0_MSR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x18}] +dict set regsC100 UART0_SCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x1C}] + +dict set regsC100 UART1_RBR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_THR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_DLL [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_IER [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}] +dict set regsC100 UART1_DLH [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}] +dict set regsC100 UART1_IIR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}] +dict set regsC100 UART1_FCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}] +dict set regsC100 UART1_LCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x0C}] +dict set regsC100 UART1_MCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x10}] +dict set regsC100 UART1_LSR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x14}] +dict set regsC100 UART1_MSR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x18}] +dict set regsC100 UART1_SCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x1C}] # /* default */ dict set regsC100 LCR_CHAR_LEN_5 0x00 @@ -308,51 +308,51 @@ dict set regsC100 LCR_PSB 0x80 dict set regsC100 LCR_DLAB 0x80 #/* FIFO Error Status */ -dict set regsC100 LSR_FIFOE [expr 1 << 7] +dict set regsC100 LSR_FIFOE [expr {1 << 7}] #/* Transmitter Empty */ -dict set regsC100 LSR_TEMT [expr 1 << 6] +dict set regsC100 LSR_TEMT [expr {1 << 6}] #/* Transmit Data Request */ -dict set regsC100 LSR_TDRQ [expr 1 << 5] +dict set regsC100 LSR_TDRQ [expr {1 << 5}] #/* Break Interrupt */ -dict set regsC100 LSR_BI [expr 1 << 4] +dict set regsC100 LSR_BI [expr {1 << 4}] #/* Framing Error */ -dict set regsC100 LSR_FE [expr 1 << 3] +dict set regsC100 LSR_FE [expr {1 << 3}] #/* Parity Error */ -dict set regsC100 LSR_PE [expr 1 << 2] +dict set regsC100 LSR_PE [expr {1 << 2}] #/* Overrun Error */ -dict set regsC100 LSR_OE [expr 1 << 1] +dict set regsC100 LSR_OE [expr {1 << 1}] #/* Data Ready */ -dict set regsC100 LSR_DR [expr 1 << 0] +dict set regsC100 LSR_DR [expr {1 << 0}] #/* DMA Requests Enable */ -dict set regsC100 IER_DMAE [expr 1 << 7] +dict set regsC100 IER_DMAE [expr {1 << 7}] #/* UART Unit Enable */ -dict set regsC100 IER_UUE [expr 1 << 6] +dict set regsC100 IER_UUE [expr {1 << 6}] #/* NRZ coding Enable */ -dict set regsC100 IER_NRZE [expr 1 << 5] +dict set regsC100 IER_NRZE [expr {1 << 5}] #/* Receiver Time Out Interrupt Enable */ -dict set regsC100 IER_RTIOE [expr 1 << 4] +dict set regsC100 IER_RTIOE [expr {1 << 4}] #/* Modem Interrupt Enable */ -dict set regsC100 IER_MIE [expr 1 << 3] +dict set regsC100 IER_MIE [expr {1 << 3}] #/* Receiver Line Status Interrupt Enable */ -dict set regsC100 IER_RLSE [expr 1 << 2] +dict set regsC100 IER_RLSE [expr {1 << 2}] #/* Transmit Data request Interrupt Enable */ -dict set regsC100 IER_TIE [expr 1 << 1] +dict set regsC100 IER_TIE [expr {1 << 1}] #/* Receiver Data Available Interrupt Enable */ -dict set regsC100 IER_RAVIE [expr 1 << 0] +dict set regsC100 IER_RAVIE [expr {1 << 0}] #/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES1 [expr 1 << 7] +dict set regsC100 IIR_FIFOES1 [expr {1 << 7}] #/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES0 [expr 1 << 6] +dict set regsC100 IIR_FIFOES0 [expr {1 << 6}] #/* Time Out Detected */ -dict set regsC100 IIR_TOD [expr 1 << 3] +dict set regsC100 IIR_TOD [expr {1 << 3}] #/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID2 [expr 1 << 2] +dict set regsC100 IIR_IID2 [expr {1 << 2}] #/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID1 [expr 1 << 1] +dict set regsC100 IIR_IID1 [expr {1 << 1}] #/* Interrupt Pending (active low) */ -dict set regsC100 IIR_IP [expr 1 << 0] +dict set regsC100 IIR_IP [expr {1 << 0}] #/* UART 16550 FIFO Control Register */ dict set regsC100 FCR_FIFOEN 0x01 @@ -372,17 +372,17 @@ dict set regsC100 IER_TXTH 0x02 #// CLK + RESET block #//////////////////////////////////////////////////////////// -dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00] -dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x04] -dict set regsC100 CLKCORE_PLL_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x08] -dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C] -dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x10] -dict set regsC100 CLKCORE_FSYNC_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x14] -dict set regsC100 CLKCORE_CLK_PWR_DWN [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x18] -dict set regsC100 CLKCORE_RNG_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C] -dict set regsC100 CLKCORE_RNG_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x20] -dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x24] -dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x40] +dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x00}] +dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x04}] +dict set regsC100 CLKCORE_PLL_STATUS [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x08}] +dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C}] +dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x10}] +dict set regsC100 CLKCORE_FSYNC_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x14}] +dict set regsC100 CLKCORE_CLK_PWR_DWN [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x18}] +dict set regsC100 CLKCORE_RNG_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C}] +dict set regsC100 CLKCORE_RNG_STATUS [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x20}] +dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x24}] +dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x40}] dict set regsC100 ARM_PLL_BY_CTRL 0x80000000 dict set regsC100 ARM_AHB_BYP 0x04000000 @@ -429,8 +429,8 @@ dict set regsC100 FCLK_PLL_LOCK 0x00000001 #// reset block -dict set regsC100 BLOCK_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x100] -dict set regsC100 CSP_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x104] +dict set regsC100 BLOCK_RESET_REG [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x100}] +dict set regsC100 CSP_RESET_REG [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x104}] dict set regsC100 RNG_RST 0x1000 dict set regsC100 IPSEC_RST 0x0800 @@ -451,42 +451,42 @@ dict set regsC100 PCI_RST 0x0001 #//////////////////////////////////////////////////////////////// dict set regsC100 DDR_CONFIG_BASEADDR 0x0D000000 -dict set regsC100 DENALI_CTL_00_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00] -dict set regsC100 DENALI_CTL_01_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08] -dict set regsC100 DENALI_CTL_02_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10] -dict set regsC100 DENALI_CTL_03_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18] -dict set regsC100 DENALI_CTL_04_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20] -dict set regsC100 DENALI_CTL_05_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28] -dict set regsC100 DENALI_CTL_06_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30] -dict set regsC100 DENALI_CTL_07_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38] -dict set regsC100 DENALI_CTL_08_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40] -dict set regsC100 DENALI_CTL_09_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48] -dict set regsC100 DENALI_CTL_10_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50] -dict set regsC100 DENALI_CTL_11_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58] -dict set regsC100 DENALI_CTL_12_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60] -dict set regsC100 DENALI_CTL_13_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68] -dict set regsC100 DENALI_CTL_14_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70] -dict set regsC100 DENALI_CTL_15_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78] -dict set regsC100 DENALI_CTL_16_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80] -dict set regsC100 DENALI_CTL_17_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88] -dict set regsC100 DENALI_CTL_18_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90] -dict set regsC100 DENALI_CTL_19_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98] -dict set regsC100 DENALI_CTL_20_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0] +dict set regsC100 DENALI_CTL_00_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00}] +dict set regsC100 DENALI_CTL_01_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08}] +dict set regsC100 DENALI_CTL_02_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10}] +dict set regsC100 DENALI_CTL_03_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18}] +dict set regsC100 DENALI_CTL_04_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20}] +dict set regsC100 DENALI_CTL_05_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28}] +dict set regsC100 DENALI_CTL_06_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30}] +dict set regsC100 DENALI_CTL_07_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38}] +dict set regsC100 DENALI_CTL_08_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40}] +dict set regsC100 DENALI_CTL_09_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48}] +dict set regsC100 DENALI_CTL_10_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50}] +dict set regsC100 DENALI_CTL_11_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58}] +dict set regsC100 DENALI_CTL_12_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60}] +dict set regsC100 DENALI_CTL_13_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68}] +dict set regsC100 DENALI_CTL_14_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70}] +dict set regsC100 DENALI_CTL_15_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78}] +dict set regsC100 DENALI_CTL_16_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80}] +dict set regsC100 DENALI_CTL_17_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88}] +dict set regsC100 DENALI_CTL_18_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90}] +dict set regsC100 DENALI_CTL_19_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98}] +dict set regsC100 DENALI_CTL_20_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0}] # 32-bit value -dict set regsC100 DENALI_READY_CHECK [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44] +dict set regsC100 DENALI_READY_CHECK [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44}] # 8-bit -dict set regsC100 DENALI_WR_DQS [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D] +dict set regsC100 DENALI_WR_DQS [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D}] # 8-bit -dict set regsC100 DENALI_DQS_OUT [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A] +dict set regsC100 DENALI_DQS_OUT [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY0 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F] +dict set regsC100 DENALI_DQS_DELAY0 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY1 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50] +dict set regsC100 DENALI_DQS_DELAY1 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY2 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51] +dict set regsC100 DENALI_DQS_DELAY2 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY3 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52] +dict set regsC100 DENALI_DQS_DELAY3 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52}] # end of proc regsC100 diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index 859a92539a..ef07856d21 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -22,53 +22,53 @@ source [find mem_helper.tcl] # PLL version 0x02: tested on dm355 # REVISIT: On dm6446/dm357 the PLLRST polarity is different. proc pll_v02_setup {pll_addr mult config} { - set pll_ctrl_addr [expr $pll_addr + 0x100] + set pll_ctrl_addr [expr {$pll_addr + 0x100}] set pll_ctrl [mrw $pll_ctrl_addr] # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator # NOTE: this assumes we should clear that bit - set pll_ctrl [expr $pll_ctrl & ~0x0100] + set pll_ctrl [expr {$pll_ctrl & ~0x0100}] mww $pll_ctrl_addr $pll_ctrl # 2 - clear PLLENSRC (bit 5) - set pll_ctrl [expr $pll_ctrl & ~0x0020] + set pll_ctrl [expr {$pll_ctrl & ~0x0020}] mww $pll_ctrl_addr $pll_ctrl # 3 - clear PLLEN (bit 0) ... enter bypass mode - set pll_ctrl [expr $pll_ctrl & ~0x0001] + set pll_ctrl [expr {$pll_ctrl & ~0x0001}] mww $pll_ctrl_addr $pll_ctrl # 4 - wait at least 4 refclk cycles sleep 1 # 5 - set PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl | 0x0008] + set pll_ctrl [expr {$pll_ctrl | 0x0008}] mww $pll_ctrl_addr $pll_ctrl # 6 - set PLLDIS (bit 4) - set pll_ctrl [expr $pll_ctrl | 0x0010] + set pll_ctrl [expr {$pll_ctrl | 0x0010}] mww $pll_ctrl_addr $pll_ctrl # 7 - clear PLLPWRDN (bit 1) - set pll_ctrl [expr $pll_ctrl & ~0x0002] + set pll_ctrl [expr {$pll_ctrl & ~0x0002}] mww $pll_ctrl_addr $pll_ctrl # 8 - clear PLLDIS (bit 4) - set pll_ctrl [expr $pll_ctrl & ~0x0010] + set pll_ctrl [expr {$pll_ctrl & ~0x0010}] mww $pll_ctrl_addr $pll_ctrl # 9 - optional: write prediv, postdiv, and pllm # NOTE: for dm355 PLL1, postdiv is controlled via MISC register - mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff] + mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}] if { [dict exists $config prediv] } { set div [dict get $config prediv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0114] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0114}] $div } if { [dict exists $config postdiv] } { set div [dict get $config postdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0128] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0128}] $div } # 10 - optional: set plldiv1, plldiv2, ... @@ -78,47 +78,47 @@ proc pll_v02_setup {pll_addr mult config} { set go 0 if { [dict exists $config div1] } { set div [dict get $config div1] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0118] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0118}] $div set go 1 } if { [dict exists $config div2] } { set div [dict get $config div2] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x011c] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x011c}] $div set go 1 } if { [dict exists $config div3] } { set div [dict get $config div3] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0120] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0120}] $div set go 1 } if { [dict exists $config div4] } { set div [dict get $config div4] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0160] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0160}] $div set go 1 } if { [dict exists $config div5] } { set div [dict get $config div5] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0164] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0164}] $div set go 1 } if {$go != 0} { # write pllcmd.GO; poll pllstat.GO - mww [expr $pll_addr + 0x0138] 0x01 - set pllstat [expr $pll_addr + 0x013c] + mww [expr {$pll_addr + 0x0138}] 0x01 + set pllstat [expr {$pll_addr + 0x013c}] while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } } - mww [expr $pll_addr + 0x0138] 0x00 + mww [expr {$pll_addr + 0x0138}] 0x00 # 11 - wait at least 5 usec for reset to finish # (assume covered by overheads including JTAG messaging) # 12 - clear PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl & ~0x0008] + set pll_ctrl [expr {$pll_ctrl & ~0x0008}] mww $pll_ctrl_addr $pll_ctrl # 13 - wait at least 8000 refclk cycles for PLL to lock @@ -126,53 +126,53 @@ proc pll_v02_setup {pll_addr mult config} { sleep 3 # 14 - set PLLEN (bit 0) ... leave bypass mode - set pll_ctrl [expr $pll_ctrl | 0x0001] + set pll_ctrl [expr {$pll_ctrl | 0x0001}] mww $pll_ctrl_addr $pll_ctrl } # PLL version 0x03: tested on dm365 proc pll_v03_setup {pll_addr mult config} { - set pll_ctrl_addr [expr $pll_addr + 0x100] - set pll_secctrl_addr [expr $pll_addr + 0x108] + set pll_ctrl_addr [expr {$pll_addr + 0x100}] + set pll_secctrl_addr [expr {$pll_addr + 0x108}] set pll_ctrl [mrw $pll_ctrl_addr] # 1 - power up the PLL - set pll_ctrl [expr $pll_ctrl & ~0x0002] + set pll_ctrl [expr {$pll_ctrl & ~0x0002}] mww $pll_ctrl_addr $pll_ctrl # 2 - clear PLLENSRC (bit 5) - set pll_ctrl [expr $pll_ctrl & ~0x0020] + set pll_ctrl [expr {$pll_ctrl & ~0x0020}] mww $pll_ctrl_addr $pll_ctrl # 2 - clear PLLEN (bit 0) ... enter bypass mode - set pll_ctrl [expr $pll_ctrl & ~0x0001] + set pll_ctrl [expr {$pll_ctrl & ~0x0001}] mww $pll_ctrl_addr $pll_ctrl # 3 - wait at least 4 refclk cycles sleep 1 # 4 - set PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl | 0x0008] + set pll_ctrl [expr {$pll_ctrl | 0x0008}] mww $pll_ctrl_addr $pll_ctrl # 5 - wait at least 5 usec sleep 1 # 6 - clear PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl & ~0x0008] + set pll_ctrl [expr {$pll_ctrl & ~0x0008}] mww $pll_ctrl_addr $pll_ctrl # 9 - optional: write prediv, postdiv, and pllm - mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] + mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}] if { [dict exists $config prediv] } { set div [dict get $config prediv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0114] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0114}] $div } if { [dict exists $config postdiv] } { set div [dict get $config postdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0128] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0128}] $div } # 10 - write start sequence to PLLSECCTL @@ -187,99 +187,99 @@ proc pll_v03_setup {pll_addr mult config} { set aln 0 if { [dict exists $config div1] } { set div [dict get $config div1] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0118] $div - set aln [expr $aln | 0x1] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0118}] $div + set aln [expr {$aln | 0x1}] } else { - mww [expr $pll_addr + 0x0118] 0 + mww [expr {$pll_addr + 0x0118}] 0 } if { [dict exists $config div2] } { set div [dict get $config div2] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x011c] $div - set aln [expr $aln | 0x2] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x011c}] $div + set aln [expr {$aln | 0x2}] } else { - mww [expr $pll_addr + 0x011c] 0 + mww [expr {$pll_addr + 0x011c}] 0 } if { [dict exists $config div3] } { set div [dict get $config div3] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0120] $div - set aln [expr $aln | 0x4] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0120}] $div + set aln [expr {$aln | 0x4}] } else { - mww [expr $pll_addr + 0x0120] 0 + mww [expr {$pll_addr + 0x0120}] 0 } if { [dict exists $config oscdiv] } { set div [dict get $config oscdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0124] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0124}] $div } else { - mww [expr $pll_addr + 0x0124] 0 + mww [expr {$pll_addr + 0x0124}] 0 } if { [dict exists $config div4] } { set div [dict get $config div4] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0160] $div - set aln [expr $aln | 0x8] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0160}] $div + set aln [expr {$aln | 0x8}] } else { - mww [expr $pll_addr + 0x0160] 0 + mww [expr {$pll_addr + 0x0160}] 0 } if { [dict exists $config div5] } { set div [dict get $config div5] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0164] $div - set aln [expr $aln | 0x10] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0164}] $div + set aln [expr {$aln | 0x10}] } else { - mww [expr $pll_addr + 0x0164] 0 + mww [expr {$pll_addr + 0x0164}] 0 } if { [dict exists $config div6] } { set div [dict get $config div6] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0168] $div - set aln [expr $aln | 0x20] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0168}] $div + set aln [expr {$aln | 0x20}] } else { - mww [expr $pll_addr + 0x0168] 0 + mww [expr {$pll_addr + 0x0168}] 0 } if { [dict exists $config div7] } { set div [dict get $config div7] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x016c] $div - set aln [expr $aln | 0x40] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x016c}] $div + set aln [expr {$aln | 0x40}] } else { - mww [expr $pll_addr + 0x016c] 0 + mww [expr {$pll_addr + 0x016c}] 0 } if { [dict exists $config div8] } { set div [dict get $config div8] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0170] $div - set aln [expr $aln | 0x80] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0170}] $div + set aln [expr {$aln | 0x80}] } else { - mww [expr $pll_addr + 0x0170] 0 + mww [expr {$pll_addr + 0x0170}] 0 } if { [dict exists $config div9] } { set div [dict get $config div9] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0174] $div - set aln [expr $aln | 0x100] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0174}] $div + set aln [expr {$aln | 0x100}] } else { - mww [expr $pll_addr + 0x0174] 0 + mww [expr {$pll_addr + 0x0174}] 0 } if {$aln != 0} { # clear pllcmd.GO - mww [expr $pll_addr + 0x0138] 0x00 + mww [expr {$pll_addr + 0x0138}] 0x00 # write alingment flags - mww [expr $pll_addr + 0x0140] $aln + mww [expr {$pll_addr + 0x0140}] $aln # write pllcmd.GO; poll pllstat.GO - mww [expr $pll_addr + 0x0138] 0x01 - set pllstat [expr $pll_addr + 0x013c] + mww [expr {$pll_addr + 0x0138}] 0x01 + set pllstat [expr {$pll_addr + 0x013c}] while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } } - mww [expr $pll_addr + 0x0138] 0x00 + mww [expr {$pll_addr + 0x0138}] 0x00 set addr [dict get $config ctladdr] while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 } # 12 - set PLLEN (bit 0) ... leave bypass mode - set pll_ctrl [expr $pll_ctrl | 0x0001] + set pll_ctrl [expr {$pll_ctrl | 0x0001}] mww $pll_ctrl_addr $pll_ctrl } @@ -290,26 +290,26 @@ proc pll_v03_setup {pll_addr mult config} { proc psc_enable {module} { set psc_addr 0x01c41000 # write MDCTL - mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f + mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f } # prepare a non-DSP module to be reset; finish with psc_go proc psc_reset {module} { set psc_addr 0x01c41000 # write MDCTL - mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f + mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f } # execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc proc psc_go {} { set psc_addr 0x01c41000 - set ptstat_addr [expr $psc_addr + 0x0128] + set ptstat_addr [expr {$psc_addr + 0x0128}] # just in case PTSTAT.go isn't clear while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } # write PTCMD.go ... ignoring any DSP power domain - mww [expr $psc_addr + 0x0120] 1 + mww [expr {$psc_addr + 0x0120}] 1 # wait for PTSTAT.go to clear (again ignoring DSP power domain) while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } @@ -344,34 +344,34 @@ proc davinci_wdog_reset {} { # # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt - mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr {$timer2_phys + 0x28}] 0x00004000 # # Part II -- in case watchdog hasn't been set up # # TCR: disable, force internal clock source - mww phys [expr $timer2_phys + 0x20] 0 + mww phys [expr {$timer2_phys + 0x20}] 0 # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state) - mww phys [expr $timer2_phys + 0x24] 0 - mww phys [expr $timer2_phys + 0x24] 0x110b + mww phys [expr {$timer2_phys + 0x24}] 0 + mww phys [expr {$timer2_phys + 0x24}] 0x110b # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers # so watchdog triggers ASAP - mww phys [expr $timer2_phys + 0x10] 0 - mww phys [expr $timer2_phys + 0x14] 0 - mww phys [expr $timer2_phys + 0x18] 0 - mww phys [expr $timer2_phys + 0x1c] 0 + mww phys [expr {$timer2_phys + 0x10}] 0 + mww phys [expr {$timer2_phys + 0x14}] 0 + mww phys [expr {$timer2_phys + 0x18}] 0 + mww phys [expr {$timer2_phys + 0x1c}] 0 # WDTCR: put into pre-active state, then active - mww phys [expr $timer2_phys + 0x28] 0xa5c64000 - mww phys [expr $timer2_phys + 0x28] 0xda7e4000 + mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000 + mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000 # # Part III -- it's ready to rumble # # WDTCR: write invalid WDKEY to trigger reset - mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr {$timer2_phys + 0x28}] 0x00004000 } diff --git a/tcl/target/fm4_mb9bf.cfg b/tcl/target/fm4_mb9bf.cfg index e53fdc8787..ca4e5f92ee 100644 --- a/tcl/target/fm4_mb9bf.cfg +++ b/tcl/target/fm4_mb9bf.cfg @@ -11,7 +11,7 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x8000 } -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \ +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \ -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash diff --git a/tcl/target/fm4_s6e2cc.cfg b/tcl/target/fm4_s6e2cc.cfg index 60b73b9747..c6f835daec 100644 --- a/tcl/target/fm4_s6e2cc.cfg +++ b/tcl/target/fm4_s6e2cc.cfg @@ -11,7 +11,7 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x18000 } -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \ +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \ -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg index d1250711bf..cdf4f24f4f 100644 --- a/tcl/target/icepick.cfg +++ b/tcl/target/icepick.cfg @@ -84,7 +84,7 @@ proc icepick_c_tapenable {jrc port} { set block 0x2 } elseif { $port < 32 } { # Test tap - set tap [expr ($port - 16)] + set tap [expr {$port - 16}] set block 0x1 } else { echo "ERROR: Invalid ICEPick C port number: $port" diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg index ccfddb6f7c..e2bee7a7a7 100644 --- a/tcl/target/imx.cfg +++ b/tcl/target/imx.cfg @@ -10,7 +10,7 @@ proc setc15 {regs value} { echo [format "set p15 0x%04x, 0x%08x" $regs $value] - arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value + arm mcr 15 [expr {($regs>>12)&0x7}] [expr {($regs>>0)&0xf}] [expr {($regs>>4)&0xf}] [expr {($regs>>8)&0x7}] $value } diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg index 624fe29da8..ee10b2157c 100644 --- a/tcl/target/ixp42x.cfg +++ b/tcl/target/ixp42x.cfg @@ -72,11 +72,11 @@ proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } { switch $CASLAT { 2 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ] + set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL2} ] set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD } 3 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ] + set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL3} ] set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD } default { error [format "unsupported cas latency \"%s\" " $CASLAT] } diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg index 6e3e78d37f..5b9e23c2ae 100644 --- a/tcl/target/omap4430.cfg +++ b/tcl/target/omap4430.cfg @@ -91,7 +91,7 @@ set _TARGETNAME $_CHIPNAME.cpu # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) set _coreid 0 -set _dbgbase [expr 0x80000000 | ($_coreid << 13)] +set _dbgbase [expr {0x80000000 | ($_coreid << 13)}] echo "Using dbgbase = [format 0x%x $_dbgbase]" dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg index 218eb64e92..fb76e136b8 100644 --- a/tcl/target/omap4460.cfg +++ b/tcl/target/omap4460.cfg @@ -91,7 +91,7 @@ set _TARGETNAME $_CHIPNAME.cpu # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) set _coreid 0 -set _dbgbase [expr 0x80000000 | ($_coreid << 13)] +set _dbgbase [expr {0x80000000 | ($_coreid << 13)}] echo "Using dbgbase = [format 0x%x $_dbgbase]" dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu diff --git a/tcl/target/or1k.cfg b/tcl/target/or1k.cfg index 360a0ddf3d..f85c2ee63a 100644 --- a/tcl/target/or1k.cfg +++ b/tcl/target/or1k.cfg @@ -69,4 +69,4 @@ set ENABLE_JSP_MULTI 4 # on burst reads and writes to improve download speeds. # This option must match the RTL configured option. -du_select adv [expr $ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI] +du_select adv [expr {$ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI}] diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg index 51a6bbddb2..f15924fc25 100644 --- a/tcl/target/pic32mx.cfg +++ b/tcl/target/pic32mx.cfg @@ -42,7 +42,7 @@ target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAM global _PIC32MX_DATASIZE global _WORKAREASIZE set _PIC32MX_DATASIZE 0x800 -set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)] +set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}] $_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0 $_TARGETNAME configure -event reset-init { diff --git a/tcl/target/psoc5lp.cfg b/tcl/target/psoc5lp.cfg index b4e8d05fa6..c90fd422d2 100644 --- a/tcl/target/psoc5lp.cfg +++ b/tcl/target/psoc5lp.cfg @@ -34,7 +34,7 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x2000 } -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE / 2] \ +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \ -work-area-size $_WORKAREASIZE -work-area-backup 0 source [find mem_helper.tcl] @@ -43,15 +43,15 @@ $_TARGETNAME configure -event reset-init { # Configure Target Device (PSoC 5LP Device Programming Specification 5.2) set PANTHER_DBG_CFG 0x4008000C - set PANTHER_DBG_CFG_BYPASS [expr 1 << 1] + set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}] mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0 set PM_ACT_CFG0 0x400043A0 mww $PM_ACT_CFG0 0xBF set FASTCLK_IMO_CR 0x40004200 - set FASTCLK_IMO_CR_F_RANGE_2 [expr 2 << 0] - set FASTCLK_IMO_CR_F_RANGE_MASK [expr 7 << 0] + set FASTCLK_IMO_CR_F_RANGE_2 [expr {2 << 0}] + set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}] mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK } diff --git a/tcl/target/snps_em_sk_fpga.cfg b/tcl/target/snps_em_sk_fpga.cfg index 2f7fecbe32..d09561f387 100644 --- a/tcl/target/snps_em_sk_fpga.cfg +++ b/tcl/target/snps_em_sk_fpga.cfg @@ -20,7 +20,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \ -expected-id 0x200044b1 set _coreid 0 -set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +set _dbgbase [expr {0x00000000 | ($_coreid << 13)}] target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \ -coreid 0 -dbgbase $_dbgbase -endian little diff --git a/tcl/target/snps_hsdk.cfg b/tcl/target/snps_hsdk.cfg index 634e07adc4..372b406f93 100644 --- a/tcl/target/snps_hsdk.cfg +++ b/tcl/target/snps_hsdk.cfg @@ -13,7 +13,7 @@ source [find cpu/arc/hs.tcl] set _coreid 0 -set _dbgbase [expr ($_coreid << 13)] +set _dbgbase [expr {$_coreid << 13}] # CHIPNAME will be used to choose core family (600, 700 or EM). As far as # OpenOCD is concerned EM and HS are identical. @@ -30,8 +30,8 @@ $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase # Flush L2$. $_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] arc_hs_init_regs @@ -46,8 +46,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] arc_hs_init_regs @@ -62,8 +62,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] arc_hs_init_regs @@ -78,8 +78,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {0x00000000 | ($_coreid << 13)}] arc_hs_init_regs # Enable L2 cache support for core 1. diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index 26d0d9301a..877976c1ac 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -208,7 +208,7 @@ proc stm32h7x_get_chipname {} { if {$sep == -1} { return $t } - return [string range $t 0 [expr $sep - 1]] + return [string range $t 0 [expr {$sep - 1}]] } if {[set $_CHIPNAME.DUAL_CORE]} { @@ -240,7 +240,7 @@ proc stm32h7x_mrw {used_target reg} { # like mmw, but with target selection proc stm32h7x_mmw {used_target reg setbits clearbits} { set old [stm32h7x_mrw $used_target $reg] - set new [expr ($old & ~$clearbits) | $setbits] + set new [expr {($old & ~$clearbits) | $setbits}] $used_target mww $reg $new } @@ -251,10 +251,10 @@ proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} { if {![using_hla]} { set _CHIPNAME [stm32h7x_get_chipname] set used_target $_CHIPNAME.ap2 - set reg_addr [expr 0xE00E1000 + $reg_offset] + set reg_addr [expr {0xE00E1000 + $reg_offset}] } { set used_target [target current] - set reg_addr [expr 0x5C001000 + $reg_offset] + set reg_addr [expr {0x5C001000 + $reg_offset}] } stm32h7x_mmw $used_target $reg_addr $setbits $clearbits diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg index 91c008765d..19fb0b6252 100644 --- a/tcl/target/ti_dm355.cfg +++ b/tcl/target/ti_dm355.cfg @@ -90,7 +90,7 @@ target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, # and that the work area is used only with a kernel mmu context ... $_TARGETNAME configure \ - -work-area-virt [expr 0xfffe0000 + 0x4000] \ + -work-area-virt [expr {0xfffe0000 + 0x4000}] \ -work-area-phys [dict get $dm355 sram1] \ -work-area-size 0x4000 \ -work-area-backup 0 diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg index 8b52746bd1..f71a77aa8b 100644 --- a/tcl/target/ti_dm365.cfg +++ b/tcl/target/ti_dm365.cfg @@ -82,7 +82,7 @@ target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, # and that the work area is used only with a kernel mmu context ... $_TARGETNAME configure \ - -work-area-virt [expr 0xfffe0000 + 0x4000] \ + -work-area-virt [expr {0xfffe0000 + 0x4000}] \ -work-area-phys [dict get $dm365 sram1] \ -work-area-size 0x4000 \ -work-area-backup 0 diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index 36e0db71d2..5ef98e9e13 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -4,13 +4,13 @@ proc mmu_off {} { set cp [arm mrc 15 0 1 0 0] - set cp [expr ($cp & ~1)] + set cp [expr {$cp & ~1}] arm mcr 15 0 1 0 0 $cp } proc mmu_on {} { set cp [arm mrc 15 0 1 0 0] - set cp [expr ($cp | 1)] + set cp [expr {$cp | 1}] arm mcr 15 0 1 0 0 $cp } diff --git a/tcl/test/selftest.cfg b/tcl/test/selftest.cfg index be420ca0ca..0331b482f5 100644 --- a/tcl/test/selftest.cfg +++ b/tcl/test/selftest.cfg @@ -3,11 +3,11 @@ add_help_text selftest "run selftest using working ram