From 6a2fd7cad507ef24a7dc4ce3c5f8b5351dd12656 Mon Sep 17 00:00:00 2001 From: Yauheni Kaliuta Date: Tue, 13 Oct 2009 20:00:46 +0300 Subject: [PATCH] Cleanup: nuke trailling whitespaces Signed-off-by: Yauheni Kaliuta --- contrib/libdcc/dcc_stdio.c | 4 ++-- contrib/libdcc/example.c | 6 +++--- ecosflash/flash.c | 12 ++++++------ src/flash/lpc2900.c | 2 +- src/target/arm11.c | 2 +- src/target/armv7a.c | 6 +++--- src/target/cortex_a8.c | 20 ++++++++++---------- 7 files changed, 26 insertions(+), 26 deletions(-) diff --git a/contrib/libdcc/dcc_stdio.c b/contrib/libdcc/dcc_stdio.c index a25e7dd169..08a49abf1b 100644 --- a/contrib/libdcc/dcc_stdio.c +++ b/contrib/libdcc/dcc_stdio.c @@ -99,7 +99,7 @@ void dbg_write_u16(const unsigned short *val, long len) while (len > 0) { - dcc_data = val[0] + dcc_data = val[0] | ((len > 1) ? val[1] << 16: 0x0000); dbg_write(dcc_data); @@ -145,7 +145,7 @@ void dbg_write_str(const char *msg) | ((len > 2) ? msg[2] << 16 : 0x00) | ((len > 3) ? msg[3] << 24 : 0x00); dbg_write(dcc_data); - + msg += 4; len -= 4; } diff --git a/contrib/libdcc/example.c b/contrib/libdcc/example.c index d456f39551..0814c9ce8b 100644 --- a/contrib/libdcc/example.c +++ b/contrib/libdcc/example.c @@ -23,11 +23,11 @@ #include "dcc_stdio.h" /* enable openocd debugmsg at the gdb prompt: - * monitor target_request debugmsgs enable - * + * monitor target_request debugmsgs enable + * * create a trace point: * monitor trace point 1 - * + * * to show how often the trace point was hit: * monitor trace point */ diff --git a/ecosflash/flash.c b/ecosflash/flash.c index 81f7d07dac..c8ac353f49 100644 --- a/ecosflash/flash.c +++ b/ecosflash/flash.c @@ -53,7 +53,7 @@ int init() *t=0; } return flash_init((_printf *)&myprintf); - + } @@ -68,15 +68,15 @@ int checkFlash(void *addr, int len) } -int erase(void *address, int len) +int erase(void *address, int len) { int retval; void *failAddress; - + retval=checkFlash(address, len); if (retval!=0) return retval; - + retval=init(); if (retval!=0) return retval; @@ -88,14 +88,14 @@ int erase(void *address, int len) extern char _end; // Data follows immediately after program, long word aligned. -int program(void *buffer, void *address, int len) +int program(void *buffer, void *address, int len) { int retval; void *failAddress; retval=checkFlash(address, len); if (retval!=0) return retval; - + retval=init(); if (retval!=0) return retval; diff --git a/src/flash/lpc2900.c b/src/flash/lpc2900.c index e39c53195d..902180cbe3 100644 --- a/src/flash/lpc2900.c +++ b/src/flash/lpc2900.c @@ -528,7 +528,7 @@ static uint32_t lpc2900_calc_tr( uint32_t clock, uint32_t time ) * FPTR.TR = ------------------------------- * 512 * - * The result is the + * The result is the */ uint32_t tr_val = (uint32_t)((((time / 1e6) * clock) + 511.0) / 512.0); diff --git a/src/target/arm11.c b/src/target/arm11.c index c41adfa3bf..f46e424b90 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -1203,7 +1203,7 @@ int arm11_assert_reset(target_t *target) /* FIX! we really should assert srst here, but * how do we reset the target into the halted state? - * + * * Also arm11 behaves "funny" when srst is asserted * (as of writing the rules are not understood). */ diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 499d592d1e..1e0e02f189 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -176,7 +176,7 @@ reg_t armv7a_gdb_dummy_fp_reg = void armv7a_show_fault_registers(target_t *target) { uint32_t dfsr, ifsr, dfar, ifar; - + /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; armv7a_common_t *armv7a = armv4_5->arch_info; @@ -186,9 +186,9 @@ void armv7a_show_fault_registers(target_t *target) armv7a->read_cp15(target, 0, 0, 6, 0, &dfar); armv7a->read_cp15(target, 0, 2, 6, 0, &ifar); - LOG_USER("Data fault registers DFSR: %8.8" PRIx32 + LOG_USER("Data fault registers DFSR: %8.8" PRIx32 ", DFAR: %8.8" PRIx32, dfsr, dfar); - LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32 + LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32 ", IFAR: %8.8" PRIx32, ifsr, ifar); } diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 846d90c343..025a468a86 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -140,13 +140,13 @@ int cortex_a8_init_debug_access(target_t *target) /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy); - /* Enabling of instruction execution in debug mode is done in debug_entry code */ - + /* Enabling of instruction execution in debug mode is done in debug_entry code */ + /* Resync breakpoint registers */ - + /* Since this is likley called from init or reset, update targtet state information*/ cortex_a8_poll(target); - + return retval; } @@ -254,7 +254,7 @@ int cortex_a8_write_cp(target_t *target, uint32_t value, /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); } - + retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_DTRRX, value); /* Move DTRRX to r0 */ @@ -331,7 +331,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r armv4_5_common_t *armv4_5 = target->arch_info; armv7a_common_t *armv7a = armv4_5->arch_info; swjdp_common_t *swjdp = &armv7a->swjdp_info; - + LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); /* Check that DCCRX is not full */ @@ -343,7 +343,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); } - + if (Rd > 16) return retval; @@ -1237,7 +1237,7 @@ int cortex_a8_assert_reset(target_t *target) armv4_5_invalidate_core_regs(target); target->state = TARGET_RESET; - + return ERROR_OK; } @@ -1444,7 +1444,7 @@ int cortex_a8_examine(struct target_s *target) uint32_t didr, ctypr, ttypr, cpuid; LOG_DEBUG("TODO"); - + /* Here we shall insert a proper ROM Table scan */ armv7a->debug_base = OMAP3530_DEBUG_BASE; @@ -1521,7 +1521,7 @@ int cortex_a8_examine(struct target_s *target) /* Configure core debug access */ cortex_a8_init_debug_access(target); - + target->type->examined = 1; return retval; -- 2.30.2