From 8c8c93c185f9cce51855bf2d495fd2aaec16d6c1 Mon Sep 17 00:00:00 2001 From: Marc Schink Date: Tue, 26 Feb 2019 14:03:27 +0100 Subject: [PATCH] target/armv7m: Use 'bool' data type Change-Id: I9cfbba9d81601cc72e2b54ec410e21c7edc4f1c4 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/4955 Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/target/armv7m.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/target/armv7m.c b/src/target/armv7m.c index ef00b94275..3d73b29544 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -205,8 +205,8 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; buf_cpy(buf, reg->value, reg->size); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } @@ -244,8 +244,8 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r, buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value); } - armv7m->arm.core_cache->reg_list[num].valid = 1; - armv7m->arm.core_cache->reg_list[num].dirty = 0; + armv7m->arm.core_cache->reg_list[num].valid = true; + armv7m->arm.core_cache->reg_list[num].dirty = false; return retval; } @@ -283,8 +283,8 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r, goto out_error; } - armv7m->arm.core_cache->reg_list[num].valid = 1; - armv7m->arm.core_cache->reg_list[num].dirty = 0; + armv7m->arm.core_cache->reg_list[num].valid = true; + armv7m->arm.core_cache->reg_list[num].dirty = false; return ERROR_OK; @@ -424,8 +424,8 @@ int armv7m_start_algorithm(struct target *target, */ struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR]; buf_set_u32(reg->value, 0, 32, 0x01000000); - reg->valid = 1; - reg->dirty = 1; + reg->valid = true; + reg->dirty = true; } if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY && @@ -440,8 +440,8 @@ int armv7m_start_algorithm(struct target *target, LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); - armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; - armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true; } /* save previous core mode */ @@ -535,8 +535,8 @@ int armv7m_wait_algorithm(struct target *target, armv7m_algorithm_info->context[i]); buf_set_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32, armv7m_algorithm_info->context[i]); - armv7m->arm.core_cache->reg_list[i].valid = 1; - armv7m->arm.core_cache->reg_list[i].dirty = 1; + armv7m->arm.core_cache->reg_list[i].valid = true; + armv7m->arm.core_cache->reg_list[i].dirty = true; } } @@ -545,8 +545,8 @@ int armv7m_wait_algorithm(struct target *target, LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); - armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; - armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true; } armv7m->arm.core_mode = armv7m_algorithm_info->core_mode; @@ -619,8 +619,8 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target) if (storage_size < 4) storage_size = 4; reg_list[i].value = calloc(1, storage_size); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].type = &armv7m_reg_type; reg_list[i].arch_info = &arch_info[i]; -- 2.30.2