From a34e4b39c47cd9f67f3f70be36c1b2f25ab23f5f Mon Sep 17 00:00:00 2001 From: mifi Date: Wed, 6 Feb 2008 19:25:42 +0000 Subject: [PATCH] =?utf8?q?-=20added=20patch=20to=20solve=20problem=20with?= =?utf8?q?=20AT91SAM9260=20(dirty=20register)=20(thanks=20to=20=C3=98yvind?= =?utf8?q?=20Harboe=20for=20the=20patch)?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit git-svn-id: svn://svn.berlios.de/openocd/trunk@282 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm7_9_common.c | 8 ++++---- src/target/arm920t.c | 42 +++++++++++++++++++------------------- src/target/armv7m.c | 2 +- src/target/cortex_m3.c | 12 +++++------ 4 files changed, 32 insertions(+), 32 deletions(-) diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index af3b7b3213..825f7fac82 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -1146,8 +1146,8 @@ int arm7_9_debug_entry(target_t *target) } /* r0 and r15 (pc) have to be restored later */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid; if ((retval = jtag->execute_queue()) != ERROR_OK) return retval; @@ -1908,7 +1908,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count } for (i=0; i<=last_reg; i++) - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -2073,7 +2073,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun embeddedice_store_reg(dbg_ctrl); for (i=0; i<=last_reg; i++) - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); if ((retval = jtag_execute_queue()) != ERROR_OK) diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 882fec2fe3..ef95581008 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -989,17 +989,17 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c fclose(output); - /* mark registers dirty */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1; + /* mark registers dirty. */ + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; return ERROR_OK; } @@ -1251,16 +1251,16 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd fclose(output); /* mark registers dirty */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; return ERROR_OK; } diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 22ffb5e7d5..8b4fd44ba1 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -287,7 +287,7 @@ int armv7m_write_core_reg(struct target_s *target, int num) if (retval != ERROR_OK) { ERROR("JTAG failure"); - armv7m->core_cache->reg_list[num].dirty = 1; + armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid; return ERROR_JTAG_DEVICE_ERROR; } DEBUG("write core reg %i value 0x%x", num , reg_value); diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 279d986a6b..db9dd0547f 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -137,7 +137,7 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval ahbap_write_system_u32(swjdp, 0x20000000, opcode); ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); - armv7m->core_cache->reg_list[15].dirty = 1; + armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); return retvalue; @@ -320,7 +320,7 @@ int cortex_m3_debug_entry(target_t *target) /* For IT instructions xPSR must be reloaded on resume and clear on debug exec*/ if (xPSR & 0xf00) { - armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid; cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } @@ -1149,8 +1149,8 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); ahbap_read_coreregister_u32(swjdp, value, 0); - armv7m->core_cache->reg_list[0].dirty = 1; - armv7m->core_cache->reg_list[15].dirty = 1; + armv7m->core_cache->reg_list[0].dirty = armv7m->core_cache->reg_list[0].valid; + armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; ahbap_write_system_u32(swjdp, 0x20000000, savedram); swjdp_transaction_endcheck(swjdp); DEBUG("load from special reg %i value 0x%x", SYSm, *value); @@ -1175,7 +1175,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty if (retval != ERROR_OK) { ERROR("JTAG failure %i", retval); - armv7m->core_cache->reg_list[num].dirty = 1; + armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid; return ERROR_JTAG_DEVICE_ERROR; } DEBUG("write core reg %i value 0x%x", num, value); @@ -1195,7 +1195,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); ahbap_write_coreregister_u32(swjdp, tempr0, 0); - armv7m->core_cache->reg_list[15].dirty = 1; + armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; ahbap_write_system_u32(swjdp, 0x20000000, savedram); swjdp_transaction_endcheck(swjdp); DEBUG("write special reg %i value 0x%x ", SYSm, value); -- 2.30.2