From a640f139baa9fe4f44d428b1e4e1a9da245532ca Mon Sep 17 00:00:00 2001 From: Matthias Welwarsky Date: Mon, 22 Jan 2018 12:28:37 +0100 Subject: [PATCH 1/1] aarch64: implement mmu on/off for aarch32 add decoding of aarch32 core modes (register layout is compatible) Change-Id: I34c3146a7b1f836d3006be2b76b036da055b3d3e Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/4374 Tested-by: jenkins Reviewed-by: Forest Crossman Reviewed-by: Matthias Welwarsky --- src/target/aarch64.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 784274a0e5..bcfce65924 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -161,8 +161,16 @@ static int aarch64_mmu_modify(struct target *target, int enable) case ARMV8_64_EL3T: instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0); break; + + case ARM_MODE_SVC: + case ARM_MODE_ABT: + case ARM_MODE_FIQ: + case ARM_MODE_IRQ: + instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0); + break; + default: - LOG_DEBUG("unknown cpu state 0x%x" PRIx32, armv8->arm.core_state); + LOG_DEBUG("unknown cpu state 0x%" PRIx32, armv8->arm.core_mode); break; } -- 2.30.2