From af3575b931b2bbd8b82d64f2f4495bae1741a1b1 Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Fri, 26 Mar 2021 13:27:52 +0100 Subject: [PATCH] flash/stm32l4x: add support of STM32G05/G06x this device has single bank flash architecture up to 64KB (page 2KB) reference: RM0444 rev 5 Change-Id: Ia213c01accb950fcbb7519e08057dae11b4443dd Signed-off-by: Tarek BOCHKATI Reviewed-on: https://review.openocd.org/c/openocd/+/6128 Tested-by: jenkins Reviewed-by: Oleksij Rempel --- src/flash/nor/stm32l4x.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index ef15013ea4..1ebf833b86 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -279,6 +279,10 @@ static const struct stm32l4_rev stm32_435_revs[] = { { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" }, }; +static const struct stm32l4_rev stm32_456_revs[] = { + { 0x1000, "A" }, +}; + static const struct stm32l4_rev stm32_460_revs[] = { { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" }, }; @@ -368,6 +372,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_base = 0x1FFF7000, .otp_size = 1024, }, + { + .id = 0x456, + .revs = stm32_456_revs, + .num_revs = ARRAY_SIZE(stm32_456_revs), + .device_str = "STM32G05/G06xx", + .max_flash_size_kb = 64, + .flags = F_NONE, + .flash_regs_base = 0x40022000, + .fsize_addr = 0x1FFF75E0, + .otp_base = 0x1FFF7000, + .otp_size = 1024, + }, { .id = 0x460, .revs = stm32_460_revs, @@ -1809,6 +1825,7 @@ static int stm32l4_probe(struct flash_bank *bank) } break; case 0x435: /* STM32L43/L44xx */ + case 0x456: /* STM32G05/G06xx */ case 0x460: /* STM32G07/G08xx */ case 0x462: /* STM32L45/L46xx */ case 0x464: /* STM32L41/L42xx */ -- 2.30.2