From f86137066a6b42c46c457c9837a8015990bf71e6 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Mon, 16 Nov 2009 16:36:09 -0800 Subject: [PATCH] ARM: "armv4_5" command prefix becomes "arm" Rename the "armv4_5" command prefix to straight "arm" so it makes more sense for newer cores. Add a simple compatibility script. Make sure all the commands give the same "not an ARM" diagnostic message (and fail properly) when called against non-ARM targets. Signed-off-by: David Brownell --- NEWS | 2 ++ doc/openocd.texi | 14 ++++++-------- src/helper/startup.tcl | 9 +++++++++ src/target/armv4_5.c | 18 +++++++++--------- tcl/board/mini2440.cfg | 2 +- tcl/target/lpc1768.cfg | 2 +- tcl/target/lpc2148.cfg | 2 +- tcl/target/lpc2378.cfg | 2 +- tcl/target/lpc2478.cfg | 2 +- 9 files changed, 31 insertions(+), 22 deletions(-) diff --git a/NEWS b/NEWS index 7387d70574..1a024e4542 100644 --- a/NEWS +++ b/NEWS @@ -8,6 +8,8 @@ JTAG Layer: Boundary Scan: Target Layer: + ARM + - renamed "armv4_5" command prefix as "arm" ARM11 - Preliminary ETM and ETB hookup - accelerated "flash erase_check" diff --git a/doc/openocd.texi b/doc/openocd.texi index 81409acce7..092de7d37e 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5515,16 +5515,14 @@ Reports whether the capture clock is locked or not. @end deffn -@section ARMv4 and ARMv5 Architecture -@cindex ARMv4 -@cindex ARMv5 +@section Generic ARM +@cindex ARM -These commands are specific to ARM architecture v4 and v5, -including all ARM7 or ARM9 systems and Intel XScale. +These commands should be available on all ARM processors. They are available in addition to other core-specific commands that may be available. -@deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}] +@deffn Command {arm core_state} [@option{arm}|@option{thumb}] Displays the core_state, optionally changing it to process either @option{arm} or @option{thumb} instructions. The target may later be resumed in the currently set core_state. @@ -5532,7 +5530,7 @@ The target may later be resumed in the currently set core_state. that is not currently supported in OpenOCD.) @end deffn -@deffn Command {armv4_5 disassemble} address [count [@option{thumb}]] +@deffn Command {arm disassemble} address [count [@option{thumb}]] @cindex disassemble Disassembles @var{count} instructions starting at @var{address}. If @var{count} is not specified, a single instruction is disassembled. @@ -5543,7 +5541,7 @@ else ARM (32-bit) instructions are used. those instructions are not currently understood by OpenOCD.) @end deffn -@deffn Command {armv4_5 reg} +@deffn Command {arm reg} Display a table of all banked core registers, fetching the current value from every core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current register value. diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl index 73c4cf19ca..096f03a8e8 100644 --- a/src/helper/startup.tcl +++ b/src/helper/startup.tcl @@ -142,6 +142,15 @@ proc ocd_gdb_restart {target_id} { reset halt } +######### + +# Temporary migration aid. May be removed starting in January 2011. +proc armv4_5 params { + echo "DEPRECATED! use 'arm $params' not 'armv4_5 $params'" + arm $params +} + +######### # This reset logic may be overridden by board/target/... scripts as needed # to provide a reset that, if possible, is close to a power-up reset. diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index e112e7b11c..7c4861ffff 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -363,10 +363,10 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) struct target *target = get_current_target(cmd_ctx); struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) + if (!is_arm(armv4_5)) { - command_print(cmd_ctx, "current target isn't an ARMV4/5 target"); - return ERROR_OK; + command_print(cmd_ctx, "current target isn't an ARM"); + return ERROR_FAIL; } if (target->state != TARGET_HALTED) @@ -412,10 +412,10 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command) struct target *target = get_current_target(cmd_ctx); struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) + if (!is_arm(armv4_5)) { - command_print(cmd_ctx, "current target isn't an ARMV4/5 target"); - return ERROR_OK; + command_print(cmd_ctx, "current target isn't an ARM"); + return ERROR_FAIL; } if (argc > 0) @@ -471,7 +471,7 @@ COMMAND_HANDLER(handle_armv4_5_disassemble_command) default: usage: command_print(cmd_ctx, - "usage: armv4_5 disassemble
[ ['thumb']]"); + "usage: arm disassemble
[ ['thumb']]"); count = 0; retval = ERROR_FAIL; } @@ -510,9 +510,9 @@ int armv4_5_register_commands(struct command_context *cmd_ctx) { struct command *armv4_5_cmd; - armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", + armv4_5_cmd = register_command(cmd_ctx, NULL, "arm", NULL, COMMAND_ANY, - "armv4/5 specific commands"); + "generic ARM commands"); register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index d17b1076b4..0f7ebf8a44 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -292,7 +292,7 @@ proc load_uboot { } { proc s {} { step reg - armv4_5 disassemble 0x33F80068 0x10 + arm disassemble 0x33F80068 0x10 } proc help_2440 {} { diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg index 9f6bcffc88..0b07d51ffb 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc1768.cfg @@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-a $_TARGETNAME configure -event reset-init { # Force target into ARM state - armv4_5 core_state arm + arm core_state arm #do not remap 0x0000-0x0020 to anything but the flash # mwb 0xE01FC040 0x01 mwb 0xE000ED08 0x00 diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg index ce672c8874..1f833e72bd 100644 --- a/tcl/target/lpc2148.cfg +++ b/tcl/target/lpc2148.cfg @@ -39,7 +39,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-a $_TARGETNAME configure -event reset-init { # Force target into ARM state - armv4_5 core_state arm + arm core_state arm # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select # "User Flash Mode" where interrupt vectors are _not_ remapped, diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg index 7f716f3def..aa3fad26c4 100644 --- a/tcl/target/lpc2378.cfg +++ b/tcl/target/lpc2378.cfg @@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x8000 -work-a $_TARGETNAME configure -event reset-init { # Force target into ARM state - armv4_5 core_state arm + arm core_state arm #do not remap 0x0000-0x0020 to anything but the flash mwb 0xE01FC040 0x01 } diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg index e78afa1ac2..b0af4c02d7 100644 --- a/tcl/target/lpc2478.cfg +++ b/tcl/target/lpc2478.cfg @@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x10000 -work- $_TARGETNAME configure -event reset-init { # Force target into ARM state - armv4_5 core_state arm + arm core_state arm # Do not remap 0x0000-0x0020 to anything but the Flash mwb 0xE01FC040 0x01 } -- 2.30.2